KR20090054093A

KR20090054093A - Voltage generating device for semiconductor device

Info

Publication number: KR20090054093A
Application number: KR1020070120789A
Authority: KR
Inventors: 박진호
Original assignee: 주식회사 동부하이텍
Priority date: 2007-11-26
Filing date: 2007-11-26
Publication date: 2009-05-29

Abstract

The embodiment relates to an internal voltage generator of a semiconductor device capable of reducing standby current. According to an embodiment, a voltage generator of a semiconductor device may include a control transistor for controlling a power supply voltage applied from the outside, a control unit for applying a control signal to the control transistor, and a control transistor for generating a reference voltage at the power supply voltage. It characterized in that it comprises a reference voltage generating means for. The embodiment has the effect of reducing the standby power consumption by cutting off the power in the standby state in the internal voltage generation circuit of the semiconductor device, it can be applied to semiconductor products that require super power.

Reference voltage

Description

Voltage generator for semiconductor devices {VOLTAGE GENERATING DEVICE FOR SEMICONDUCTOR DEVICE}

The embodiment relates to a voltage generator for generating an internal reference voltage of a semiconductor device.

The semiconductor memory device requires an active current and a standby current to speed up. However, the semiconductor memory requires less power consumption in the standby state, and the high speed and the low power consumption are a problem to be solved in the semiconductor memory device which desires high speed.

The internal voltage generator in the CMOS chip always flows leakage current from VDD to VSS when power is applied regardless of chip operation.

In general, CMOS chips are not always used when operating as a component of electronics. For example, when you finish a call on your cell phone, it enters a Stand-By state, which goes to standby mode to reduce power consumption.

Recently, due to rapid technology development, products are miniaturized, and thus the operating voltage is also lowered, and standby power consumption is a big issue.

The embodiment provides an internal voltage generator of a semiconductor device capable of reducing standby current.

According to an embodiment, a voltage generator of a semiconductor device may include a control transistor for controlling a power supply voltage applied from the outside, a control unit for applying a control signal to the control transistor, and a control transistor for generating a reference voltage at the power supply voltage. It characterized in that it comprises a reference voltage generating means for.

The embodiment has the effect of reducing the standby power consumption by cutting off the power in the standby state in the internal voltage generation circuit of the semiconductor device, it can be applied to semiconductor products that require super power.

The embodiment can quickly control the current flow from the input power terminal (VDD) to the ground terminal (VSS) in the active state and the standby state in the internal voltage generator circuit, thereby reducing the control response time and reducing the power consumption, as well as fast time. Current can be supplied inside the circuit.

Hereinafter, an internal voltage generator of a semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings. However, one of ordinary skill in the art who understands the spirit of the present invention may easily propose another embodiment by adding, adding, deleting, or modifying elements within the scope of the same spirit, but this also belongs to the scope of the present invention. I will say.

With reference to the accompanying drawings will be described in detail the internal voltage generator of the semiconductor device according to the embodiments. Hereinafter, when referred to as "first", "second", and the like, this is not intended to limit the members but to show that the members are divided and have at least two. Thus, when referred to as "first", "second", etc., it is apparent that a plurality of members are provided, and each member may be used selectively or interchangeably. In addition, not all components shown in the drawings are necessarily included or limited to the present invention, and components other than the essential features of the present invention may be added or deleted.

In describing the embodiments, when it is determined that detailed descriptions of related known configurations or functions may obscure the gist of the present invention, the detailed descriptions thereof will be omitted.

1 is an internal voltage generation circuit diagram of a semiconductor device according to a first embodiment.

As shown in FIG. 1, the internal voltage generation circuit of the semiconductor device includes first to fourth transistors 101, 102, 103, and 104 as reference voltage generating means.

The first and second transistors 101 and 102 are PMOS transistors, and the third and fourth transistors 103 and 104 are NMOS transistors.

The first and third transistors 101 and 103 have drains connected in series with each other, and the second and fourth transistors 102 and 104 have drains connected in series with each other.

Sources of the first and second transistors 101 and 102 are connected, and the third and fourth transistors 103 and 104 are respectively connected to a ground terminal.

Gates of the first and second transistors 101 and 102 are connected to each other, and gates of the third and fourth transistors 103 and 104 are connected to each other.

A resistor 105 may be connected between the third transistor 103 and the ground terminal GND.

Gates of the first and second transistors 101 and 102 are connected to drains of the first and third transistors 101 and 103.

Gates of the third and fourth transistors 103 and 104 are connected to drains of the second and fourth transistors 102 and 104 to output a reference voltage Vref to an output terminal.

The first to fourth transistors 101, 102, 103, and 104 of the internal voltage generation circuit may be designed in a current mirror type structure.

An input power supply terminal VDD is connected to a control transistor 121 for controlling an input power supply, and the control transistor 121 is connected to a source of the first and second transistors 101 and 102.

The control transistor 121 includes an NMOS transistor.

The gate of the control transistor 121 is connected to the control unit 122, the drain is supplied with VDD from the input power supply terminal.

When the internal voltage generation circuit is in an active state, the controller 122 inputs a 'high' signal, that is, the same VDD as that of the input power supply terminal, to the gate of the control transistor 121, and VGS (the gate and the gate). Voltage between the sources) becomes VDD and is turned on. Accordingly, an active current flows from the power input terminal to the internal voltage generation circuit.

When the internal voltage generation circuit is in a standby state, the controller 122 inputs a 'low' signal to the gate of the control transistor 121 and turns off when VGS becomes zero. Therefore, the standby current can be reduced by blocking the current flow from the power input terminal to the internal voltage generation circuit.

Therefore, in the embodiment, the control transistor 121 is disposed at the input power supply terminal in the internal voltage generation circuit to cut off the power supply in the standby state, thereby reducing standby power consumption, and to be applied to a semiconductor product requiring super power. Can be.

2 is an internal voltage generation circuit diagram of the semiconductor device according to the second embodiment.

As shown in FIG. 2, an input power supply terminal VDD is connected to a control transistor 221 for controlling an input power supply, and the control transistor 221 is connected to a current mirror type circuit as in the first embodiment. do.

The control transistor 221 includes a PMOS transistor.

The gate of the control transistor 221 is connected to the control unit 222, the source is supplied with VDD from the input power supply terminal.

When the internal voltage generation circuit is active, the controller 222 inputs a 'low' signal to the gate of the control transistor 221, and VGS (voltage between the gate and the source) becomes | VDD | Is turned on. Accordingly, an active current flows from the power input terminal to the internal voltage generation circuit.

When the internal voltage generation circuit is in a standby state, the controller 222 inputs a 'high' signal, ie, the same VDD as the input power supply terminal, to the gate of the control transistor 221 and turns off when VGS becomes 0. do. Therefore, the standby current can be reduced by blocking the current flow from the power input terminal to the internal voltage generation circuit.

Therefore, in the embodiment, since the control transistor 221 is disposed at the input power supply terminal VDD in the internal voltage generation circuit, the power is cut off in the standby state, thereby reducing standby power consumption. Applicable to

3 is an internal voltage generation circuit diagram of the semiconductor device according to the third embodiment.

As shown in FIG. 3, an input power supply terminal VDD is connected to a drain of the first control transistor 321 for controlling the input power supply, and the input power supply terminal VDD is a source of the second control transistor 322. Connected with.

The source of the first control transistor 321 and the drain of the second control transistor 322 are connected to each other, and the first and second control transistors 321 and 322 are the current mirror type as in the first embodiment. Connected to the circuit.

The first control transistor 321 is an NMOS transistor, and the second control transistor 322 is a PMOS transistor.

The gate of the first control transistor 321 is connected to the first control unit 331, and the gate of the second control transistor 322 is connected to the second control unit 332.

The first control unit 331 and the second control unit 332 apply opposite signals to the gates of the first and second control transistors 321 and 322, respectively. 1 may be connected to the control unit 331 and an inverter (inverter). Therefore, not only the first control transistor 321 but also the second control transistor 322 may be controlled by the signal generated by the first controller 331.

When the internal voltage generation circuit is in an active state, the first control unit 331 inputs a 'high' signal, that is, the same VDD as the input power supply terminal, to the gate of the first control transistor 321, and VGS (gate Voltage between and source) becomes VDD and is turned on. Accordingly, an active current flows from the power input terminal to the internal voltage generation circuit.

In addition, when the internal voltage generation circuit is in an active state, the second controller 332 inputs a 'low' signal to the gate of the second control transistor 322, and VGS (voltage between gate and source). Becomes | VDD | and is turned on. Accordingly, an active current flows from the power input terminal to the internal voltage generation circuit.

Therefore, since both of the first and second control transistors 321 and 322 are turned on, current may flow quickly from the power input terminal to the internal voltage generation circuit.

Therefore, the embodiment can quickly provide a current flow from the input power supply terminal VDD to the ground terminal VSS in the active state in the internal voltage generation circuit, thereby reducing the control response time and supplying the current inside the circuit in a short time. .

When the internal voltage generation circuit is in the standby state, the first controller 331 inputs a 'low' signal to the gate of the first control transistor 321, and turns off when VGS becomes zero. Therefore, the standby current can be reduced by blocking the current flow from the power input terminal to the internal voltage generation circuit.

In addition, when the internal voltage generation circuit is in a standby state, the second controller 332 inputs a 'high' signal, that is, the same VDD as that of the input power supply terminal, to the gate of the second control transistor 322, and VGS. Becomes 0 and is turned off. Therefore, the standby current can be reduced by blocking the current flow from the power input terminal to the internal voltage generation circuit.

Therefore, the embodiment can quickly cut off the current flow from the input power supply terminal VDD to the ground terminal VSS in the standby state in the internal voltage generation circuit, thereby reducing the control response time and reducing the power consumption as well as blocking the leakage current. Can be.

Although described above with reference to the embodiments, which are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains are not exemplified above without departing from the essential characteristics of the present invention. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment of the present invention can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

Claims

A control transistor for controlling a power supply voltage applied from the outside;

A control unit applying a control signal to the control transistor; And

And a reference voltage generating means connected to the control transistor to generate a reference voltage at the power supply voltage.

The method of claim 1,

The reference voltage generating means,

A first transistor and a second transistor connected in parallel with the control transistor;

A third transistor connected with the first transistor; And

A fourth transistor connected to the second transistor,

Gates of the first and second transistors are connected to drains of the first and third transistors, and gates of the third and fourth transistors are connected to drains of the second and fourth transistors to output a reference voltage. A voltage generator of a semiconductor device, characterized in that.

The method of claim 1,

Wherein the first and second transistors are PMOS transistors, and the third and fourth transistors are NMOS transistors.

The method of claim 1,

The control transistor is an NMOS transistor, when the control unit applies a 'high' signal, the control transistor passes a current to the reference voltage generating means in response to the power supply voltage, and the control unit 'low' And the control transistor cuts the power supply voltage when the signal is applied.

The method of claim 1,

The control transistor is a PMOS transistor, when the control unit applies a 'low' signal, the control transistor passes a current to the reference voltage generating means in response to the power supply voltage, and the control unit is 'high' And the control transistor cuts the power supply voltage when the signal is applied.

The method of claim 1,

The control transistor includes an NMOS transistor and a PMOS transistor connected in parallel with a power supply voltage terminal.

A first control unit for applying a first control signal to a gate of the NMOS transistor; And

And a second control unit for applying a second control signal to the gate of the PMOS transistor.

The method of claim 6,

And the first control signal and the second control signal are signals of opposite levels.

The method of claim 6,

The first control unit and the second control unit are connected to an inverter, the voltage generating device of a semiconductor device, characterized in that to control the NMOS transistor and the PMOS transistor at the same time with the first control signal.