JPS6424505A - Logic circuit device - Google Patents

Logic circuit device

Info

Publication number
JPS6424505A
JPS6424505A JP62180736A JP18073687A JPS6424505A JP S6424505 A JPS6424505 A JP S6424505A JP 62180736 A JP62180736 A JP 62180736A JP 18073687 A JP18073687 A JP 18073687A JP S6424505 A JPS6424505 A JP S6424505A
Authority
JP
Japan
Prior art keywords
level
storage part
signal
reset
master
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62180736A
Other languages
Japanese (ja)
Inventor
Koichi Tatsuke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP62180736A priority Critical patent/JPS6424505A/en
Publication of JPS6424505A publication Critical patent/JPS6424505A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a master-slave delay type logic circuit device whose operation speed is made fast while decreasing in number of elements by composing a data storage means of an inverting circuit. CONSTITUTION:A reset signal R is supplied to a reset terminal 14 and supplied to the gate terminal of a pull-down element 6. When a set signal S is lowered to 'L' level and the reset signal R is raised to 'H' level at the time of resetting, a 1st clock signal CK1 goes up to 'H' level and a 2nd clock signal CK2 falls to 'L' level. Consequently, a 1st transmission gate 4 turns off and a 2nd transmission gate 8 turns on to reset a master storage part 7 and a slave storage part 9 forcibly. When the set signal S is raised to 'H' level and the reset signal R is lowered to 'L' level at the time of setting, the master storage part and slave storage part 9 are set forcibly. Consequently, the number of the elements constituting the storage circuit is reduced and the operation speed is made fast.
JP62180736A 1987-07-20 1987-07-20 Logic circuit device Pending JPS6424505A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62180736A JPS6424505A (en) 1987-07-20 1987-07-20 Logic circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62180736A JPS6424505A (en) 1987-07-20 1987-07-20 Logic circuit device

Publications (1)

Publication Number Publication Date
JPS6424505A true JPS6424505A (en) 1989-01-26

Family

ID=16088411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62180736A Pending JPS6424505A (en) 1987-07-20 1987-07-20 Logic circuit device

Country Status (1)

Country Link
JP (1) JPS6424505A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5831462A (en) * 1995-03-08 1998-11-03 Advanced Micro Devices, Inc. Conditional latching mechanism and pipelined microprocessor employing the same
JP2002208841A (en) * 2001-01-11 2002-07-26 Seiko Instruments Inc Dynamic flip-flop
KR20170090336A (en) * 2016-01-28 2017-08-07 삼성전자주식회사 Semiconductor device comprising retset retention flip-flop

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5831462A (en) * 1995-03-08 1998-11-03 Advanced Micro Devices, Inc. Conditional latching mechanism and pipelined microprocessor employing the same
JP2002208841A (en) * 2001-01-11 2002-07-26 Seiko Instruments Inc Dynamic flip-flop
KR20170090336A (en) * 2016-01-28 2017-08-07 삼성전자주식회사 Semiconductor device comprising retset retention flip-flop

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