KR102495033B1 - An electronic device and a system including the same - Google Patents

Abstract

The embodiment has an input/output port connected to a communication line, a first power supply as a driving power supply, an amplification unit for amplifying and outputting an input signal, and an input terminal connected to the output terminal of the amplification unit, based on the voltage of the input terminal. An output unit that outputs an output of the amplification unit to the input/output port, and a first node connected between an output terminal of the amplification unit and an input terminal of the output unit, and a second power supply, and a level of the first power supplied to the amplification unit. Based on, it includes an output control unit for controlling the voltage of the first node.

Description

Electronic device and system including the same {AN ELECTRONIC DEVICE AND A SYSTEM INCLUDING THE SAME}

The embodiment relates to an electronic device and a system including the same.

A final output terminal of an I/O interface of a typical electric device includes an inverter including a PMOS transistor and an NMOS transistor. On the other hand, a final output terminal of an I/O interface of an electric device using an I2C interface may include an inverter including a PMOS transistor and an NMOS transistor, and the gate and source of the PMOS transistor may have a structure connected to each other.

In a system having a plurality of electronic elements commonly connected to a bus, communication may be performed between two or more electronic elements among the plurality of electronic elements through an I/O interface. At this time, since electronic elements that do not communicate also share the bus, power may be required to maintain the state of the input/output port or terminal. Power consumption may occur due to power provided to electronic devices that do not communicate. Power consumption in a system can be reduced by cutting off power provided to electronic devices that do not communicate.

The embodiment provides an electronic device capable of reducing power consumption and preventing communication failure, and a system including the same.

An electronic device according to an embodiment includes an input/output port connected to a communication line; an amplification unit provided with a first power source as a driving power source and amplifying an input signal and outputting the amplified signal; an output unit having an input terminal connected to an output terminal of the amplification unit and outputting an output of the amplification unit to the input/output port based on a voltage of the input terminal; and a first node connected between an output terminal of the amplification unit and an input terminal of the output unit and a second power source, and controlling a voltage of the first node based on a level of the first power supply provided to the amplification unit. It includes an output control unit.

The output controller controls the voltage of the first node so that the voltage of the first node is maintained lower than a reference voltage when the level of the first power is a low level.

The output unit may include an output transistor including a gate connected to the first node, a source and a drain connected between the input/output port and the second power supply. The reference voltage may be a threshold voltage of the output transistor.

The output controller includes a first control transistor including a first gate to which the first power is supplied, and a first source and a first drain connected between the first node and the second node; a second control transistor including a second gate connected to the second node, and a second source and a second drain connected between the first node and the second power source; and a third control transistor including a third gate through which the first power is supplied, and a third source and a third drain connected between the second node and the second power.

The amplifier may be an inverter that inverts the input signal.

The input/output port may be connected to a communication line communicating according to a bus communication protocol.

The output controller may float the first node from the second power when the level of the first power is a high level.

The electronic device may further include a receiver connected to the input/output port and receiving a signal provided to the input/output port.

A signal provided to the input/output port may be a pulse signal.

An electronic device according to another embodiment includes an input/output port connected to a communication line; an inverter connected between the first power source and the second power source and inverting an input signal and outputting the inverted signal; an output transistor including a gate connected to the output terminal of the inverter, and a source and drain connected between the input/output port and the second power source; and an output control unit connected between a first node connected to an output terminal of the inverter and a gate of the output transistor and the second power supply, and controlling a voltage of the first node based on a level of the first power supply. .

The output control unit may control the voltage of the first node so that the voltage of the first node is maintained lower than the threshold voltage of the output transistor when the level of the first power is at a low level.

The output controller may disconnect the electrical connection between the first node and the second power when the level of the first power is a high level.

A signal provided to the input/output port may be a data or clock signal.

A system according to an embodiment includes a first communication line; and a plurality of electronic elements, each of the plurality of electronic elements including a first input/output interface connected to the first communication line, and the first input/output interface connected to the first communication line. port; a first amplifier provided with a first power source as a driving power source and amplifying a first input signal and outputting the amplified signal; a first output unit having a first input terminal connected to the first output terminal of the first amplifier unit and outputting an output of the first amplifier unit to the first input/output port based on a voltage of the first input terminal; And connected between a first node and a second power supply to which the first output terminal of the first amplifier unit and the first input terminal of the first output unit connect, based on the level of the first power supply provided to the first amplifier unit. , and a first output controller for controlling the voltage of the first node.

Each of the plurality of electronic elements may further include a second input/output interface connected to a second communication line, wherein the second input/output interface includes a second input/output port connected to the second communication line; a second amplifying unit provided with the first power as a driving power and amplifying and outputting a second input signal; a second output unit having a second input terminal connected to the second output terminal of the second amplifier unit and outputting an output of the second amplifier unit to the second input/output port based on a voltage of the second input terminal; and a second node connected between a second output terminal of the second amplification unit and a second input terminal of the second output unit and the second power supply, based on a level of the first power supplied to the second amplifier unit. Thus, it may include a second output controller for controlling the voltage of the second node.

The system includes a first resistor connected between a third power source and the first communication line; and a power supply unit selectively providing the first power to each of the plurality of electronic elements.

Data may be provided to the first communication line, and a clock may be provided to the second communication line.

The output controller controls the voltage of the first node to maintain a voltage of the first node lower than a reference voltage when the level of the first power is low, and when the level of the first power is high , the first node may be floated from the second power source.

The embodiment can reduce power consumption and prevent communication failure.

1 shows a configuration diagram of an electronic device according to an embodiment.
FIG. 2 shows a circuit diagram according to an embodiment of the electronic device shown in FIG. 1 .
FIG. 3A is a circuit diagram for explaining a first operation of the output control unit shown in FIG. 2 .
FIG. 3B is a circuit diagram for explaining a second operation of the output controller shown in FIG. 2 .
FIG. 4 shows a case in which there is no output controller in FIG. 3B.
5 shows an electronic device according to another embodiment.
6 shows a system including electronic devices according to an embodiment.
FIG. 7 shows data communication between the second and third electronic devices shown in FIG. 5 .
8 shows a system according to another embodiment.
FIG. 9 shows simulation results of leakage current of an output unit when the output control unit shown in FIG. 4 is not present.
FIG. 10 shows simulation results of leakage current of the output unit of the embodiment shown in FIG. 2 .
FIG. 11 shows simulation results of gate voltage and leakage current of the output transistor of FIG. 4 and gate voltage and leakage current of the output transistor of FIG. 2 when the frequency of the signal is 100 Mhz.

Hereinafter, embodiments will be clearly revealed through the accompanying drawings and description of the embodiments. In the description of the embodiment, each layer (film), region, pattern or structure is “on” or “under” the substrate, each layer (film), region, pad or pattern. In the case where it is described as being formed in, "up / on" and "under / under" include both "directly" or "indirectly" formed through another layer. do. In addition, the criterion for the upper/upper or lower/lower of each layer will be described based on the drawings.

In the drawings, sizes are exaggerated, omitted, or schematically illustrated for convenience and clarity of explanation. Also, the size of each component does not fully reflect the actual size. Also, like reference numerals denote like elements throughout the description of the drawings.

1 shows a configuration diagram of an electronic device 100 according to an embodiment, and FIG. 2 shows a circuit diagram of the electronic device 100 shown in FIG. 1 according to an embodiment.

Referring to FIGS. 1 and 2 , the electronic device 100 may include an input/output interface that communicates with other electronic devices through a communication line, for example, a bus (BUS, not shown), for example, I2C communication. there is.

The electronic device 100 receives an input signal Sa through an input/output port 110 connected to a communication line, for example, a bus (BUS, not shown), and amplifies the received input signal Sa. It has an input terminal (IN1) connected to the amplification unit 120 and the output terminal (OUT1) of the amplification unit 120, and outputs As of the amplification unit 120 based on the voltage applied to the input terminal (IN1) to the input/output port ( 110), the output terminal (OUT1) of the amplification unit 120 and the input terminal (IN1) of the output unit 130 are based on the level of the power supply (DVDD1) provided to the output unit 130 and the amplification unit 120. and an output control unit 140 that controls the voltage of the first node NG1 to which this connection is connected. In addition, the input/output interface of the electronic device 100 may further include an input/output port 110 .

2, the amplification unit 120 is implemented in the form of an inverter, but the embodiment is not limited thereto, and in another embodiment, the amplification unit 120 is in the form of a buffer, operational amplifier, or differential amplifier. may be implemented.

For example, the amplifier 120 may be a CMOS inverter including a PMOS transistor PM1 and an NMOS transistor. A first power source DVDD1 and a second power source Vss may be provided to the amplifier 120 as driving power sources. For example, the first power supply DVDD1 may be provided to the source and bulk (or substrate) of the PMOS transistor PM1, and the second power supply Vss may be provided to the source and bulk (or substrate) of the NMOS transistor NM1. can be provided in For example, the level of the first power source DVDD1 may be higher than that of the second power source. The first power source DVDD1 and the second power source Vss of the amplifier 120 may be power sources for driving the input/output interface of the electronic device 100 .

The amplifier 120 may invert the input signal Sa and output the inverted signal As through the output terminal OUT1.

The output unit 130 may be implemented as an amplification element including an input terminal IN1 connected to the output terminal OUT1 of the amplifier 120 and an output terminal OUT2 connected to the input/output port 110, for example, a transistor. there is.

For example, the output unit 130 includes an output transistor OM including a gate connected to the output terminal OUT1 of the amplifier 120 and a source and drain connected between the second power supply Vss and the input/output port 110. ) may be included.

For example, the output transistor OM may be an NMOS transistor, the drain of the output transistor OM is connected to the input/output port 110, and the source and bulk (or substrate) of the output transistor OM are connected to the second power source Vss. ) can be accessed.

The output control unit 140 is connected between the first node NG1 and the second power supply Vss, and based on the level of the driving power provided to the amplifier 120, for example, the first power supply DVDD1, the first The voltage of the node NG1 is controlled.

For example, the output control unit 140 outputs the first node NG1 when the level of driving power (eg, the first power supply DVDD1) provided to the amplifier 120 is a low level (eg, 0[V]). The voltage of the first node NG1 may be controlled so that the voltage of NG1 is maintained lower than the reference voltage. Here, the reference voltage may be a threshold voltage of the output transistor MO of the output controller 140 .

Also, for example, when the level of the first power source DVDD1 is at a high level, the output control unit 140 floats the first node NG1 from the second power source Vss or causes the first node NG1 to float. and the second power supply (Vss) are electrically disconnected.

For example, the output controller 140 may include first to third control transistors PM2, NM2, and NM3.

The first control transistor PM2 is connected between a first gate to which the driving power supply of the amplifier 120, for example, the first power supply DVDD1 is provided, and a first node NG1 and a second node NG2. 1 may include a source and a first drain.

The second control transistor NM2 may include a second gate connected to the second node NG2, and a second source and a second drain connected between the first node NG1 and the second power source Vss. there is.

The third control transistor NM3 is connected between a third gate provided with a driving power source of the amplifier 120, for example, the first power source DVDD1, and a second node GN2 and the second power source Vss. It may include 3 sources and a 3rd drain.

For example, the second node NG2 may be a node to which the second drain of the first control transistor PM2, the second gate of the second transistor NM2, and the drain of the third control transistor NM3 are commonly connected. .

The output control unit 140 floats the first node NG1 from the second power supply Vss based on the driving power of the amplifier 120, for example, the level of the first power supply DVDD1, or The first node NG1 may be connected to the second power source Vss.

The output control unit 140 is an amplification unit ( ) according to the voltage level of the signal provided to the input/output port 110 when the driving power provided to the amplifier 120 is cut off or the level of the driving power is 0 [V]. 120) serves to prevent power consumption from occurring.

That is, the output control unit 140 reduces unnecessary power consumption by preventing power consumption from occurring in the amplification unit 120 by a signal applied to the bus even if the driving power for driving the input/output interface of the electronic device 100 is cut off. can play a role

FIG. 3A is a circuit diagram for explaining a first operation of the output control unit 140 shown in FIG. 2 , and FIG. 3B is a circuit diagram for explaining a second operation of the output control unit 140 shown in FIG. 2 .

A first operation of the output controller 140 will be described with reference to FIG. 3A.

The first operation of the output control unit 140 is an operation when the level of the driving power (eg, the first power supply DVDD1) of the amplification unit 120 is the second level (eg, DVDD1 = 5 [V]), and the output The second operation of the control unit 140 may be an operation when the level of the driving power supply (eg, the first power supply DVDD1) of the amplifier 120 is the first level (eg, DVDD1 = 0 [V]).

When the level of the driving power supply (eg, the first power supply DVDD1) of the amplifier 120 is the second level (eg, DVDD1 = 5 [V]), the first control transistor PM2 of the output controller 140 When the third control transistor NM3 is turned on, the voltage of the second gate of the second control transistor NM2 changes to that of the second power source Vss. When the voltage (eg, 0 [V]) is reached, the second control transistor NM2 is turned off.

When the level of the driving power supply (eg, the first power supply DVDD1) of the amplifier 120 is the second level (eg, DVDD1 = 5 [V]), the third control transistor NM3 is turned on, and And since the second control transistors PM2 and NM2 are turned off, the output controller 140 does not have any effect on the voltage of the first node NG1, and the first node NG1 supplies the second power source Vss. That is, in the first operation, regardless of the level of the signal DVVD2 applied to the input/output port 110, the first node GN1 floats from the second power supply Vss, and the amplifier 120 And the output unit 130 operates normally.

Next, referring to FIG. 3B , the second operation of the output controller 140 will be described.

The level of the driving power supply (eg, the first power source DVDD1) of the amplifier 120 is the first level (eg, DVDD1 = 0[V]), and the signal DVD2 applied to the input/output port 110 is the first level. The voltage of the first node NG1 rises during a period 301 (see FIG. 3B ) changing from a level (eg, 0 [V]) to a second level (eg, 5 [V]).

The reason why the voltage of the first node NG1 rises during the changing period 301 of the signal SG is the drain and gate of the output transistor OM of the output unit 130 during the changing period 301 of the signal SG. This is because a surge current flows into the first node NG1 through a capacitor Cgd generated therebetween, for example, an intrinsic or parasitic capacitor.

Unnecessary power consumption may occur due to the surge current generated during the change period 301 .

FIG. 4 shows a case in which there is no output controller 140 in FIG. 3B.

Referring to FIG. 4 , the voltage of the first node NG may increase due to a surge current flowing through the output specific capacitor Cgd during a change period 301 of the signal SG. Since the level of the driving power supplied to the amplification unit 120 is 0 [V], there is a gap between the drain of the PMOS transistor PM1 of the amplification unit 120 and the first power supply terminal 121 to which the first power supply DVDD1 is provided. A junction diode may be formed, and when the rising voltage of the first node NG becomes higher than the operating voltage of the junction diode, the first power supply terminal 121 is connected to the first node NG through the junction diode. As a result, the voltage of the first node NG may drop and the output transistor OM may not be turned on. In this case, unnecessary power consumption does not occur or the amount of power consumption is small. may be

However, when the operating voltage of the junction diode is higher than the threshold voltage of the output transistor OM, when the rising voltage of the first node NG becomes higher than the threshold voltage of the output transistor OM, the output transistor MO is turned on. can As the output transistor MO is turned on, leakage current Ie flows between the input/output port 110 and the second power source Vss, and unnecessary power consumption may occur due to the leakage current Ie.

FIG. 9 shows simulation results of the leakage current Ie1 of the output unit 130 when the output control unit 140 shown in FIG. 4 is not present.

The output transistor OM is a 0.18 μm, 5V CMOS transistor, has a threshold voltage of 689mV in the change period 301, and has an intrinsic capacitance Cgd of 40 fF (femtoFarads). The frequency of the signal SG of the communication line 501 and the connection node 601 (see FIG. 6) of the resistor Rp is 400 kHz.

Referring to FIG. 9, in the change period 301, for example, 5.1 μs, the voltage (V _NG ) of the gate of the output transistor OM is 695 mV and the threshold voltage of the output transistor OM is 689 mV, so that the output transistor OM can be turned on, and the leakage current Ie1 becomes 74.3 μA.

The leakage current Ie1 may be a factor inducing power consumption in an electronic device that is powered off.

As the gate voltage V _NG of the output transistor OM of the electronic device is higher than the threshold voltage of the output transistor OM, the resistance value of the turn-on resistance of the output transistor OM may decrease. The connection node of the communication line 501 and the resistance Rp is determined by the ratio of the turn-on resistance of the output transistor OM and the resistance value of the resistance Rp (see FIG. 6) connected to the communication line 510 (see FIG. 6). The voltage of (601, see FIG. 6) may be determined, and if the resistance value of the turn-on resistor becomes small, a communication error or failure may occur.

An operation of the output controller 140 to prevent unnecessary power consumption is as follows.

As shown in FIG. 3 , when the level of the driving power supply (eg, the first power supply DVDD1) of the amplifier 120 is the first level (eg, DVDD1 = 0[V]), the first control transistor PM2 ) is turned on, and the third control transistor NM3 is turned off.

When the first control transistor PM2 is turned on, the second gate and the second drain of the second control transistor NM2 may be connected in common to the first node NG1. That is, the first node NG1 and the second node NG2 may be connected to each other. In addition, when the third control transistor NM3 is turned off, the second gate of the second control transistor NM2 or the second node NG2 floats from the second power source Vss or is connected to the second power source Vss. can be cut off.

As the voltage of the first node NG1 increases in the change period 301 of the signal SG, the voltage of the second gate of the second control transistor NM2 (Vg2 or the voltage of the second node NG2) increases. together can rise.

When the voltage Vg2 of the second gate of the second control transistor NM2 gradually rises and the voltage Vg2 of the second gate becomes higher than the threshold voltage Vth2 (threshold voltage) of the second control transistor NM2 ( Vg2>Vth2), the second control transistor NM2 can be turned on, and as the second control transistor NM2 is turned on, a current path is formed between the first node NG1 and the second power source Vss. , the voltage of the first node NG1 decreases.

And, when the voltage of the first node NG1 to be reduced becomes lower than the threshold voltage of the output transistor OM of the output unit 130, the output transistor OM can be turned off, and the output transistor OM can be turned off and removed from the input/output port 110. It is possible to block the flow of leakage current with the second power source, thereby reducing power consumption during the second operation, and preventing communication errors and failures described in FIG. 4 .

By controlling the voltage (V _NG1 ) of the first node (NG1) to be lower than the threshold voltage of the output transistor (MO) during the second operation by the output control unit 140, the output transistor (MO) in the second operation It is possible to prevent unnecessary power consumption by the output unit 130 by preventing it from being turned on.

FIG. 10 shows simulation results of leakage current Ie2 of the output unit 130 according to the embodiment shown in FIG. 2 . The output transistor OM of FIG. 10 has the same simulation conditions as those of FIG. 9 .

Referring to FIG. 10 , in a change period 301, for example, 5.1 μs, the voltage V _NG 1 of the gate of the output transistor OM is 516 μV and the leakage current Ie2 is 495 μV. Compared to FIG. 9 , the leakage current Ie2 of FIG. 10 can be reduced by about 1/150, thereby reducing unnecessary power consumption.

FIG. 11 shows the voltage (V _NG ) and leakage current (Ie1) of the gate of the output transistor OM in the case of FIG. 4 and the gate of the output transistor OM in FIG. 2 when the frequency of the signal SG is 100 Mhz. The simulation results of the voltage (V _NG 1) and leakage current (Ie2) of

Referring to FIG. 11, the voltage V _NG of the gate of the output transistor OM in the case of FIG. 4 is 742 mV in the change period 301', for example, 24.8 ns, and the gate voltage of the output transistor OM of FIG. The voltage V _NG 1 is 945 nV, and the leakage current Ie1 in the case of Fig. 4 is 154 μA, and the leakage current Ie2 in the case of Fig. 2 is 9.68 pA. During the high half cycle, the average leakage current in the case of FIG. 4 is 276 μA, and the average leakage current in the case of FIG. 2 is 0.67 μA, which reduces power consumption.

5 shows an electronic device 100a according to another embodiment. The same reference numerals as those in FIGS. 2 and 3 denote the same configurations, and descriptions of the same configurations are simplified or omitted.

Referring to FIG. 5 , the electronic device 100a further includes a receiver 150 in addition to the electronic device 100 shown in FIG. 2 .

The receiving unit 150 is connected to the input/output port 110 and receives a signal provided to the input/output port 110 . For example, the receiver 150 may amplify or buffer a signal provided to the input/output port 110 and output the amplified or buffered signal.

The receiver 150 is implemented in the form of an inverter, but the embodiment is not limited thereto, and in other embodiments, the amplifier 120 may be implemented in the form of a buffer, operational amplifier, or differential amplifier. .

For example, the receiver 150 may be a CMOS inverter including a PMOS transistor and an NMOS transistor, and an input end of the CNOS inverter may be connected to the input/output port 110 .

Details described in FIGS. 2 to 4 may be equally applied to FIG. 5 .

6 shows a system 200 including electronic devices 501-1 to 501-m, where m is a natural number > 1, according to an embodiment.

Referring to FIG. 6 , the system 200 includes a communication line 510, a resistor Rp connected between the communication line 510 and a power source DVDD2, and a plurality of electronic elements connected to the communication line 510 ( 501-1 to 501-m, where m is a natural number > 1), and a power supply unit 520 that supplies power to electronic devices (501-1 to 501-m, where m is a natural number > 1).

The communication line 510 may be a bus (BUS) that communicates according to a bus communication protocol. For example, the communication line 510 may be a serial data line or a serial clock line.

The electronic elements 501-1 to 501-m (where m is a natural number > 1) may exchange signals SG with each other through the communication line 510. For example, the signal SG may be a pulse type signal.

Each of the plurality of electronic devices 501-1 to 501-m, where m is a natural number > 1, may be an electronic device according to the embodiments 100 and 100a of FIG. 2 or FIG. 5 . For example, each of the plurality of electronic elements (501-1 to 501-m, where m is a natural number > 1) has an input/output interface that communicates according to a bus communication protocol, such as a memory element and a sensing element. , or a processor, or an integrated device.

Each of the input/output ports (110-1 to 110-m, where m is a natural number > 1) of the plurality of electronic devices (501-1 to 501-m, where m is a natural number > 1) shown in FIG. 2 or FIG. 5 may correspond to the input/output port 110 of the embodiments 100 and 100a.

The input/output ports 110 - 1 to 110 - m (where m is a natural number > 1) may be commonly connected to the communication line 510 .

The power supply 520 may selectively supply the first power DVDD1 to the plurality of electronic elements 501-1 to 501-m (where m is a natural number > 1).

For example, the power supply 520 supplies power to electronic elements that communicate among a plurality of electronic elements (501-1 to 501-m, where m is a natural number > 1), and supplies power to electronic elements that do not communicate. may not supply.

That is, the voltage of the first power source DVDD1 provided to the electronic device that communicates by the power supply 520 may be a preset first voltage (eg, DVDD1 = 5 [V]), and the electronic device that does not communicate The voltage of the first power source DVDD1 provided to may be the second voltage (eg, 0 [V]).

The signal SG provided to the communication line may be serial data DATA or clock CLK, but is not limited thereto.

FIG. 7 illustrates data communication between the second and third electronic devices 110-2 and 110-3 shown in FIG.

Referring to FIG. 7 , in order to reduce power consumption, the second and third electronic elements 501-2 and 501-3 to be communicated by the power supply unit 520 receive a first voltage (5 [V]). 1 power source DVDD1 may be provided, and the first power source DVDD1 of the second voltage (0 [V]) may be provided to the first electronic element 501-1 that does not communicate.

When the input signal Sa of the second electronic element 501-2 is at the first level, the second electronic element 510-2 has a resistance Rp and the connection node 701 of the communication line 510 is low. In this state, the resistor Rp may be in a high state to transfer data to the receiving unit 150 of the third electronic device 510-3.

At this time, as described in FIG. 3B, in the first electronic element 501-1 to which the second voltage (0 [V]) is provided, the level of the data DATA provided to the communication line 510 is the first level (low). level, eg, 0 [V]) to the second level (high level, eg, 5 [V]), leakage current can be suppressed by the operation of the output controller 140, thereby reducing unnecessary power consumption can be reduced.

8 shows a system 300 according to another embodiment.

Referring to FIG. 8 , the system 300 includes first and second communication lines 510-1 and 510-2, and a first resistor connected between the first communication line 510-1 and the power source DVDD2. (Rp1), a second resistor Rp2 connected between the second communication line 510-2 and the power source DVDD2, and a plurality of electronic elements 701-1 to 701-1 connected to the first and second communication lines. 701-m), and a power supply unit 720 providing a first power source DVDD1 to the electronic devices 701-1 to 701-m.

Each of the first and second communication lines 510-1 and 510-2 may be a bus that communicates according to a bus communication protocol, for example, the first communication line 510-1 may be a serial clock line that transmits a clock signal, and the second communication line 510-2 may be a serial data line that transmits data.

Each of the plurality of electronic elements 701-1 to 701-m has a first input/output interface 710A connected to the first communication line 510, and a second input/output interface connected to the second communication line 510 ( 710B) may be included.

Each of the first and second input/output interfaces 710A and 710B may include the components shown in FIG. 2 or FIG. 5 .

For example, each of the first and second input/output interfaces 710A and 710B may include an input/output port 110, an amplifier 120, an output unit 130, an output control unit 140, and a receiver 150. there is.

The power supply 720 may selectively supply the first power DVDD1 to the plurality of electronic devices 701-1 to 701-m.

Features, structures, effects, etc. described in the embodiments above are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. illustrated in each embodiment can be combined or modified with respect to other embodiments by a person having ordinary knowledge in the field to which the embodiments belong. Therefore, contents related to these combinations and variations should be construed as being included in the scope of the present invention.

110: input/output port 120: amplification unit
130: output unit 140: output control unit
150: receiver.

Claims (20)

an input/output port connected to a communication line;
an amplification unit provided with a first power source as a driving power source and amplifying an input signal and outputting the amplified signal;
an output unit having an input terminal connected to an output terminal of the amplification unit and outputting an output of the amplification unit to the input/output port based on a voltage of the input terminal; and
An output connected between a first node connected to an output terminal of the amplification unit and an input terminal of the output unit and a second power supply, and controlling a voltage of the first node based on a level of the first power supply provided to the amplification unit. An electronic device comprising a control unit. The method of claim 1, wherein the output control unit,
When the level of the first power is a low level, the electronic device characterized in that for controlling the voltage of the first node so that the voltage of the first node is maintained lower than a reference voltage. According to claim 2,
The output unit includes an output transistor including a gate connected to the first node, a source and a drain connected between the input/output port and the second power supply,
The electronic device, characterized in that the reference voltage is a threshold voltage of the output transistor. The method of claim 1, wherein the output control unit,
a first control transistor including a first gate to which the first power is supplied, and a first source and a first drain connected between the first node and a second node;
a second control transistor including a second gate connected to the second node, and a second source and a second drain connected between the first node and the second power source; and
and a third control transistor including a third gate to which the first power is supplied, and a third source and a third drain connected between the second node and the second power. According to claim 1,
The electronic device, characterized in that the amplification unit is an inverter for inverting the input signal. According to claim 1,
The input/output port is connected to a communication line communicating according to a bus communication protocol. The method of claim 1, wherein the output control unit,
When the level of the first power is high, the first node is floated from the second power. According to claim 1,
The electronic device further includes a receiver connected to the input/output port and receiving a signal provided to the input/output port. According to claim 1,
The electronic device, characterized in that the signal provided to the input and output port is a pulse signal. an input/output port connected to a communication line;
an inverter connected between the first power source and the second power source and inverting an input signal and outputting the inverted signal;
an output transistor including a gate connected to the output terminal of the inverter, and a source and drain connected between the input/output port and the second power source; and
and an output controller connected between a first node connected to the output terminal of the inverter and a gate of the output transistor and the second power supply, and controlling a voltage of the first node based on a level of the first power supply. device. According to claim 10,
The electronic device, characterized in that, when the level of the first power supply is a low level, the output controller controls the voltage of the first node so that the voltage of the first node is maintained lower than the threshold voltage of the output transistor. According to claim 11,
The electronic device according to claim 1 , wherein the output control unit disconnects an electrical connection between the first node and the second power when the level of the first power is at a high level. 11. The method of claim 10, wherein the output control unit,
a first control transistor including a first gate to which the first power is supplied, and a first source and a first drain connected between the first node and a second node;
a second control transistor including a second gate connected to the second node, and a second source and a second drain connected between the first node and the second power source; and
and a third control transistor including a third gate to which the first power is supplied, and a third source and a third drain connected between the second node and the second power. According to claim 10,
The electronic device further includes a receiver connected to the input/output port and receiving a signal provided to the input/output port. According to claim 10,
The electronic device, characterized in that the signal provided to the input and output port is a data or clock signal. a first communication line; and
Including a plurality of electronic elements,
Each of the plurality of electronic elements includes a first input/output interface connected to the first communication line,
The first input/output interface,
a first input/output port connected to the first communication line;
a first amplifier provided with a first power source as a driving power source and amplifying a first input signal and outputting the amplified signal;
a first output unit having a first input terminal connected to the first output terminal of the first amplifier unit and outputting an output of the first amplifier unit to the first input/output port based on a voltage of the first input terminal; and
Based on the level of the first power supplied to the first amplifier, A system comprising a first output controller for controlling the voltage of the first node. According to claim 16,
Each of the plurality of electronic elements further includes a second input/output interface connected to a second communication line,
The second input/output interface,
a second input/output port connected to the second communication line;
a second amplifying unit provided with the first power as a driving power and amplifying and outputting a second input signal;
a second output unit having a second input terminal connected to the second output terminal of the second amplifier unit and outputting an output of the second amplifier unit to the second input/output port based on a voltage of the second input terminal; and
Based on the level of the first power connected between the second power supply and a second node to which the second output terminal of the second amplifier and the second input terminal of the second output unit connect, and provided to the second amplifier, , The system characterized in that it comprises a second output control unit for controlling the voltage of the second node. According to claim 16,
a first resistor connected between a third power source and the first communication line; and
The system further comprises a power supply unit selectively providing the first power to each of the plurality of electronic elements. According to claim 17,
Data is provided to the first communication line, and a clock is provided to the second communication line. According to claim 16,
The output control unit,
Controlling the voltage of the first node so that the voltage of the first node is maintained lower than a reference voltage when the level of the first power supply is at a low level;
When the level of the first power supply is at a high level, the first node is floated from the second power supply.

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