KR102461251B1 - Weighting device, neural network, and operating method of the weighting device - Google Patents

Abstract

Disclosed are a weighting element capable of being driven at a low voltage and implementing multilevel, a neural network, and a method of operating the weighting element. The weight element includes a switching layer that can be switched between a high resistance state and a low resistance state according to voltage application, and a charge trapping material layer that traps or releases charges according to the resistance state of the switching layer. Such a weight element may be used to adjust a weight in a neural network.

Description

Weighting device, neural network, and operating method of the weighting device

The present disclosure relates to a weight element capable of implementing multi-level weighting, a neural network, and a method of operating the weight element.

There are hundreds of billions of neurons in the brain, and they are intricately connected to each other to form a neural network. These neurons have synapses that can send and receive signals with other neurons, so they can perform roles such as learning and memory. A synapse refers to a junction where the axon of the pre-synapse through which a signal is transmitted and the dendrite of the post-synapse at which the signal is received are connected, teaching the junction between neurons. In general, one neuron has synapses with thousands of other neurons. The development of a neuromorphic network for simulating such a biological neural network is being attempted. In the development of such a circuit, a device having characteristics similar to a neural phenomenon is required. A neural network using electronic calculations of the existing Von Neuman structure has been proposed. The core element of this neural network is a weighting device, which has a function of accumulating information by repetitive input signals. Small is required.

An object of the present invention is to provide a weight element capable of being driven at a low voltage and implementing multi-level, a neural network, and an operation method of the weight element.

A weight element according to the present disclosure includes: a substrate; On the substrate, a source region and a common region are spaced apart from each other, a source electrode electrically connected to the source region, a first channel region positioned between the source region and the common region, and on the first channel region A first gate insulating layer provided, a charge trapping material layer provided on the first gate insulating layer, a switching layer provided on the charge trapping material layer and capable of switching between a high resistance state and a low resistance state, and on the switching layer a first transistor including a first gate electrode provided on the junction, wherein the charge trapping material layer faces a region adjacent to the first channel region in the common region with the first gate insulating layer interposed therebetween; and a drain region spaced apart from the common region on the substrate, a drain electrode electrically connected to the drain region, a second channel region positioned between the common region and the drain region, and provided on the second channel region and a second transistor including a second gate insulating layer, a second gate insulating layer, a second gate electrode provided on the second gate insulating layer, and using the common region as a source.

The first transistor may be disposed on the substrate in contact with the source region and further include a leakage preventing region forming a PN diode structure with the source region, and the source electrode may be in contact with the leakage preventing region.

The leakage preventing region may be surrounded by the source region except for an area in contact with the source electrode.

The first channel region and the second channel region may have opposite conductivity.

The first transistor may further include a well surrounding the source region, the first channel region, and the common region in the substrate and having a conductivity opposite to that of the second channel region.

The first gate electrode and the source electrode may be electrically connected to each other.

A boosting electrode facing the charge trapping material layer with the first gate insulating layer and the substrate interposed therebetween may be further included.

The switching layer may include a nanofilamentary material capable of being switched to the low resistance state by forming conductive nanofilaments according to voltage application.

The switching layer may include a PN diode layer.

A method of operating a weight element according to the present disclosure, comprising: opening the second channel region by applying a selection voltage to the second gate electrode; applying a write voltage to the drain electrode; and grounding the first gate electrode, wherein an electric charge flows into the charge trapping material layer through the first gate electrode by the write voltage to write information into the charge trapping material layer.

or, applying a selection voltage to the second gate electrode to open the second channel region; applying an erase voltage to the first gate electrode; and grounding the drain electrode, wherein the information may be erased by removing the charge trapped in the charge trapping material layer by the erase voltage.

or, applying a selection voltage to the second gate electrode to open the second channel region; applying a read voltage to the source electrode; and reading the amount of charge captured in the charge trapping material layer by measuring the measurement current at the drain electrode.

The applying of the write voltage may include applying a pulse voltage to the drain electrode to reflect a weight, and the reflection of the weight may be controlled by the number of times the pulse voltage is applied.

The applying of the erasing voltage may include applying a pulse voltage to the first gate electrode to reflect a weight, and the reflection of the weight may be controlled by the number of times the pulse voltage is applied.

A neural network according to the present disclosure includes a plurality of weight elements described above; and a plurality of neuron transistors selectively switching gate voltages applied to the plurality of weight elements.

The plurality of neuron transistors are two-dimensionally arranged, and drain electrodes of the plurality of neuron transistors are respectively connected to the first gate electrodes of the plurality of weight elements, and are connected to the gate electrodes of the neuron transistors located in the same column to apply a selection voltage. selectable line; and an input line connected to a source electrode of a neuron transistor positioned in the same row to apply an input voltage.

The plurality of weight elements may be one-dimensionally arranged or two-dimensionally arranged.

In the method of operating a neural network according to the present disclosure, input information input through the plurality of neuron transistors and output information output through the plurality of weight elements are predetermined, and a weight value of the neural network corresponding thereto is determined. It may be supervised learning.

Alternatively, it may be an unsupervised learning method in which a weight value of a neural network is autonomously determined according to input information input through a neuron transistor.

A weighting device according to another embodiment includes a third transistor including a third gate electrode, a first electrode, and a second electrode; a fourth transistor sharing the third transistor and the second electrode and having a fourth gate electrode and a third electrode; a fifth transistor having a fifth gate electrode and a fourth electrode and having a common area as a drain; a sixth transistor having a sixth gate electrode and a fifth electrode and using the common area as a source; a switching layer formed on the first electrode and the third electrode and capable of being switched between a high resistance state and a low resistance state; a charge trapping material layer disposed on the switching layer and configured to trap or release charges according to a resistance state of the switching layer; and an interconnect connecting the charge trapping material layer and the sixth gate electrode.

According to the disclosed embodiments, it is possible to implement a weight element having a multi-level characteristic. According to the disclosed embodiments, it is possible to implement a weight element that can be operated with a low voltage.

According to the disclosed embodiments, the 4-terminal weight element may perform read, write, and erase operations.

According to the disclosed embodiments, the three-terminal weight element can prevent current leakage to the source electrode as a modification of the four-terminal weight element.

According to the disclosed embodiments, the 6-terminal weight element may have a relatively large multilevel characteristic.

According to the disclosed embodiments, it can be utilized in a neural network through connection between weight elements.

1 is a cross-sectional view illustrating a weighting element according to an exemplary embodiment.
FIG. 2 is a cross-sectional view illustrating a writing operation of the weight element of FIG. 1 .
3 is a cross-sectional view illustrating an erase operation of the weight element of FIG. 1 .
4A to 4C are cross-sectional views illustrating a read operation of the weight element of FIG. 1 .
5 is a cross-sectional view illustrating a weighting element according to another exemplary embodiment.
6 is a cross-sectional view showing a weight element according to another embodiment.
7 is a cross-sectional view illustrating a weighting device according to another exemplary embodiment.
8 is a cross-sectional view illustrating a write operation of the weight element of FIG. 7 .
9 is a cross-sectional view illustrating an erase operation of the weight element of FIG. 7 .
10A and 10B are diagrams illustrating an operation method for adjusting a weight of a weight element.
11 is a cross-sectional view illustrating a weighting device according to another exemplary embodiment.
12 is a cross-sectional view illustrating a weight element according to another embodiment.
13 is a cross-sectional view illustrating a weighting device according to another exemplary embodiment.
14 is a diagram illustrating a current curve versus applied voltage of the PN diode layer according to FIG. 13 .
15A to 15D are diagrams schematically illustrating another weight element and an operation method thereof.
16 is a diagram schematically illustrating the principle of a neural network.
17A to 17C are schematic diagrams illustrating a method of driving a weight element in a neural network.
18A to 18C are diagrams schematically illustrating the operation of a neural network composed of a plurality of columns of synapses and a single column of perceptrons.
19 is a diagram related to learning using a neural network.
20 is a graph of controlled learning.
21 is a graph related to uncontrolled learning.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only the embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. The same reference numerals refer to the same components throughout the specification, and the size or thickness of each component in the drawings may be exaggerated for clarity of description. Descriptions of the same reference numerals may be omitted within the overlapping range.

Terms used in this specification will be briefly described, and the present invention will be described in detail.

The terms used in the present invention have been selected as currently widely used general terms as possible while considering the functions in the present invention, but these may vary depending on the intention or precedent of a person skilled in the art, the emergence of new technology, and the like. In addition, in a specific case, there is a term arbitrarily selected by the applicant, and in this case, the meaning will be described in detail in the description of the corresponding invention. Therefore, the term used in the present invention should be defined based on the meaning of the term and the overall content of the present invention, rather than the name of a simple term.

In the entire specification, when a part "includes" a certain component, it means that other components may be further included, rather than excluding other components, unless otherwise stated.

Hereinafter, with reference to the accompanying drawings, the embodiments of the present invention will be described in detail so that those skilled in the art can easily carry out the embodiments of the present invention. And in order to clearly explain the present invention in the drawings, parts irrelevant to the description will be omitted.

1 is a cross-sectional view showing a weighting element according to an embodiment of the present invention. The weighting element according to the present embodiment may be understood as a weighting element having 4 terminals. In neuroscience or computer science, weight means the strength or strength of the connection between two nodes. In particular, in a neural network, a weight may mean the strength of a signal transmitted to a plurality of neurons connected to one neuron. Mathematically, when the input value from the pre-neuron is x, the output value from the post-neuron is y, and the weight matrix values of the pre-neuron and the post-neuron are w _ij , x, y, w _ij The following equation can be established between:

The following Equation 1 may be established.

Equation 1 means that the sum of the product of the input value x of the pre-neurons and the weight w _ij is the output value y. Accordingly, when specific input information is applied in a neural network in which a plurality of neurons are complicatedly entangled, each pre-neuron is The output value to be transmitted to the post-neuron may vary according to the corresponding weight value. This is similar to the neurotransmission process in living things. Electrical pulse signals generated from pre-neurons of living things reach synapses and cause chemical processes. Neurotransmitters formed through chemical processes are transmitted to post-neurons. At this time, the amount of the transmitted neurotransmitter determines whether the post-neuron will generate an electric pulse signal again, and thus the amount of the neurotransmitter may correspond to the weight w _ij . The weight element is an element constituting a neural network simulating an actual neural network, and may be an element capable of storing and reading a weight value w _ij in a multi-level memory. The weight element may have a transistor structure and may include a charge trapping material layer CL and a threshold voltage conversion layer TL. The weight element may receive a pulse signal as an input value. The charge trapping material layer CL may store electric charges of various values according to the number of input pulse signals. The switching layer SL may prevent leakage of an amount of charges trapped in the charge trapping material layer CL. Details will be described below.

Referring to FIG. 1 , the weight element according to the present embodiment may be provided on a substrate SUB. The substrate SUB may be a semiconductor substrate. For example, the substrate SUB may include a group element such as silicon (Si). The weight element may include a first transistor TR1 and a second transistor TR2.

The first transistor TR1 may include a source electrode SE and a first gate electrode GE1, and the common area SD may serve as a drain. The first transistor TR1 may include a charge trapping layer M1 capable of storing a weight value. The charge trapping layer M1 includes a switching layer SL that can be switched between a high resistance state and a low resistance state according to voltage application, and a charge trapping material that traps or releases charges according to the resistance state of the switching layer SL. A layer CL may be included.

The first transistor TR1 may include a first channel region C1. The first transistor TR1 may be of a depletion type. The first channel region C1 of the depletion-type first transistor TR1 may have an open state in which electricity can flow through the first channel region C1 even when no voltage is applied to the first gate electrode GE1. have. The first channel region C1 may have a closed state in which electricity cannot flow when a negative voltage is applied to the first channel region C1 . For example, when charges are sufficiently accumulated in the charge trapping material layer CL located on the first channel region C1 , a negative voltage due to the charges is applied to the first channel region C1 and thus the first channel region (C1) can be closed.

The second transistor TR2 may include a second gate electrode GE2 and a drain electrode DE, and may use the common area SD as a source. The first transistor TR1 may use the common area SD as a drain, and at the same time, the second transistor TR2 may use the common area SD as a source. The substrate SUB may include a source region S1 and a common region SD spaced apart from each other. The first channel region C1 may be provided between the source region S1 and the common region SD.

The second transistor TR2 may include a second channel region C2. The second channel region C2 may be provided between the common region SD and the drain region D1 . The second channel region C2 may be of an enhancement type. The second channel region C2 of the increase-type second transistor may have an open state in which electricity can flow through the second channel region C2 when a voltage is applied to the second gate electrode GE2 . The second channel region C2 may have a closed state in which electricity cannot flow through the second channel region C2 when no voltage is applied.

A gate insulating layer GO may be provided on the substrate SUB. The gate insulating layer GO may be formed by oxidizing the surface of the substrate SUB. For example, when the substrate SUB includes silicon, the gate insulating layer GO may be formed of silicon oxide. The gate insulating layer GO may serve as a buffer layer. The gate insulating layer GO may serve as an insulating layer to insulate each gate electrode and the channel region of the first transistor TR1 and the second transistor TR2 . For example, the gate insulating layer GO may serve as a first gate insulating layer GO1 insulating the first channel region C1 of the first transistor TR1 and the charge trapping layer M1 from each other. . For example, the gate insulating layer GO may serve as a second gate insulating layer GO2 insulating the second channel region C2 of the second transistor TR2 and the second gate electrode GE2 from each other. The weight element 100 formed on the substrate SUB may be of an NMOS type or a PMOS type. For example, the NMOS-type weighting device 100 may include a substrate SUB doped with a p-type dopant, a source region S1 doped with an n-type dopant, a common region SD, and a drain region D1. have. The PMOS-type weight element may be doped with a dopant having a conductivity opposite to that of the above-described NMOS-type weight element. The NMOS type and the PMOS type only have the opposite operation method, and the technical characteristics are not different. Therefore, although the present embodiment discloses an NMOS type weight element, the present invention is not limited thereto and may include a PMOS type weight element. In addition, the weight element may include N-Well, which is a well formed with an n-type dopant, or P-Well, which is a well formed with a p-type dopant, which will be described in detail later.

The charge trap layer M1 includes a first channel region C1 and a charge trap layer CL formed on a portion of the common region SD adjacent to the first channel region C1, and A switching layer SL formed on the capture material layer CL may be included.

A partial surface of the charge trapping material layer CL may face a partial surface of the common area SD with the first gate insulating layer GO1 interposed therebetween. Details will be described later with reference to FIG. 2 .

The material constituting the charge trapping material layer CL may include, for example, silicon nitride (Si _x N _y ) or polycrystalline silicon. Alternatively, the charge trapping material layer CL may be formed of a metal such as tungsten, molybdenum, cobalt, nickel, platinum, rhodium, palladium and iridium, a mixture thereof, or an alloy thereof. Alternatively, the charge trapping material layer (CL) is silicon, germanium, a mixture of silicon and germanium, a group III-V compound (a combination of Al, Ga, In of group III and P, As, and Sb of group V) or II-VI It may be formed of a semiconductor material such as a group compound (a combination of Zn, Cd, Hg of group II and O, S, Se, and Te of group VI). Alternatively, the charge trapping material layer CL is an insulator having a high trapping density for charges, such as an aluminum oxide film (Al ₂ O ₃ ), a hafnium oxide film (HfO), a hafnium aluminum oxide film (HfAlO), a hafunium silicon oxide film (HfSiO), and the like. can also be formed.

The maximum amount of charge that can be stored in the charge trapping material layer CL may be proportional to the volume of the charge trapping material layer CL. The charge trapping material layer CL may store binary information depending on whether or not charges are stored. For example, it can be regarded as 1 when the charge is stored and 0 when it is not stored, and through this, a digital signal can be stored. Furthermore, it may have a multi-level weight value capable of storing a plurality of information in stages according to the amount of stored charge. For example, assuming that 100% is when the maximum charge is stored in the charge trapping material layer (CL), 0 when no charge is stored, 1 when 25% of charge is stored, and 50% when the charge is stored. can be viewed as 2, when 75% of the charge is stored as 3, and when 100% of the charge is stored as 4. One such weight element can be regarded as storing 4 bits of information. As the amount of stored charge is divided more precisely, more weights can be stored in one device, but errors may increase. The total amount of charges that can be stored in the charge trapping material layer CL and the volume of the charge trapping material layer CL may be proportional to each other. Accordingly, as the volume of the charge trapping material layer CL increases, more multi-level weights can be implemented. Since the multi-level is determined according to the amount of charges trapped in the charge trapping material layer CL, the charge trapping layer M1 is designed to have non-volatility so that charges do not escape even when no voltage is applied to the charge trapping material layer CL. It may include a switching layer SL.

The switching layer SL may have a property of a variable resistance material whose resistance changes according to a voltage applied to the switching layer SL. The resistance of the switching layer SL is divided into a high resistance state and a low resistance state, and may be switched according to an applied voltage. For example, the resistance of the switching layer SL may non-linearly change according to an applied voltage, and when a specific voltage or more is applied, the resistance value may non-linearly decrease. The resistance state of the switching layer SL when no voltage is applied to the switching layer SL or when a voltage smaller than the above-described specific voltage is applied may be viewed as a high resistance state. In addition, a resistance state when a voltage higher than the above-described specific voltage is applied to the switching layer SL and the resistance of the switching layer SL is non-linearly lowered may be regarded as a low resistance state. This specific voltage may be referred to as a threshold switching voltage. In addition, since the weight element according to the present embodiment can store electric charges in the charge trapping material layer CL without using the charge tunneling method, deterioration of the interface state due to repeated use of the element can be prevented.

The switching layer SL may be formed of a threshold voltage converting material. The threshold voltage conversion material is a property that normally maintains a high resistance state, but changes to a low resistance state only while a voltage greater than or equal to a threshold voltage unique to the threshold voltage conversion material is applied, and returns to a high resistance state when the applied voltage is removed refers to a substance with The switching layer SL made of such a material blocks the movement of charges between the first gate electrode GE1 and the charge trapping material layer CL in a high resistance state to which no voltage is applied, In the resistance state, the movement of charges between the first gate electrode GE1 and the charge trapping material layer CL is possible.

The threshold voltage converting material may include, for example, a chalcogenide-based material or a transition metal oxide. The chalcogenide-based material is, for example, at least one transition metal among Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, and Re and at least one chalcogen (chalcogen) of S, Se, and Te. ) may be formed by including the element. Transition metal oxides include, for example, Ti oxide, Ta oxide, Ni oxide, Zn oxide, W oxide, Co oxide, Nb oxide, TiNi oxide, LiNi oxide, InZn oxide, V oxide, SrZr oxide, SrTi oxide, Cr oxide, It may include at least one of Fe oxide, Cu oxide, Hf oxide, Zr oxide, Al oxide, and mixtures thereof.

The switching layer SL may include a nano-filamentary material in which a low resistance state is formed by nano-filaments. Details will be described later with reference to FIG. 12 .

The switching layer SL may be formed of a PN diode. Details will be described later with reference to FIG. 13 .

The weight element according to the present embodiment may have four terminals. The operation of the weight element can be controlled through each terminal. The electrode may include a source electrode SE, a first gate electrode GE1 , a second gate electrode GE2 , and a drain electrode DE. The source electrode SE is connected to the source region S1. The drain electrode DE is connected to the drain region D1. The meaning of 'connection' may include the meaning of electrical contact. The electrode may use a metal material with high electrical conductivity, for example, a material such as Pd, Pt, Ru, Au, Ag, Mo, Mg, Al, W, Ti, Ir, Ni, Cr, Nd or Cu. In addition, graphene or a transparent conductive metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), or gallium zinc oxide (GZO) may be used.

A voltage may be applied to each electrode of the 4-terminal weight element to operate the weight element. The operation of each electrode will be looked at below. Hereinafter, it is assumed that the first channel region C1 is a depletion type and the second channel region C2 is an increase type, but the present invention is not limited thereto. The first channel region C1 may be of a depletion type or an increase type, and the second channel region C2 may have a depletion type or an increase type. Whether the first channel region C1 and the second channel region C2 is a depletion type or an increase type may only change the operation method of the weight element, but may not change the characteristics of the weight element.

The source electrode SE may be related to a read operation. When a read voltage is applied to the source electrode SE, a sensing current may flow through the first channel region C1. The magnitude of the measurement current may be changed according to the amount of charge trapped in the charge trapping material layer CL located on the first channel region C1 . For example, when holes in the first channel region C1 are pulled up by an electric field caused by charges trapped in the charge trapping material layer CL, the amount of current flowing along the first channel region C1 may decrease. have. As more charges are trapped in the charge trapping material layer CL, the amount of current flowing along the first channel region C1 is further reduced. Accordingly, the amount of charge captured in the charge trapping material layer CL may be determined according to the magnitude of the measurement current. For example, the amount of charge trapped in the charge trapping material layer CL may be measured from the decrease in the measured current based on the measured current value when there is no charge trapped in the charge trapping material layer CL. .

The first gate electrode GE1 may be related to an erase operation. The erase voltage applied to the first gate electrode GE1 may be transferred to the common region SD through the second channel region C2 . The erase voltage may be distributed to the switching layer SL, the charge trapping material layer CL, and the gate insulating layer GO. When the magnitude of the voltage applied to the switching layer SL exceeds the threshold voltage, the charge trapping material layer CL may discharge charges. If the magnitude of the voltage applied to the switching layer SL does not exceed the threshold voltage, the trapping charge trapping material layer CL cannot discharge charges.

The second gate electrode GE2 may be related to selection of a weight element. When a selection voltage equal to or higher than a predetermined level is applied to the second gate electrode GE2 , the second channel region C2 of the second transistor TR2 may be opened. In the writing, erasing, and erasing operations of the weight element according to the present embodiment, the second channel region C2 of the second transistor TR2 must be in an open state, so whether a selection voltage is applied to the second gate electrode GE2 Whether or not the weight element is selected may be determined.

The drain electrode DE may be related to a write operation. A write voltage may be applied to the drain electrode DE. The write voltage applied to the drain electrode DE may be distributed to the switching layer SL, the charge trapping material layer CL, and the gate insulating layer GO. When the voltage distributed to the switching layer SL is equal to or greater than the threshold voltage, the charge trapping material layer CL may trap charges. When the voltage distributed to the switching layer SL is less than or equal to the threshold voltage, the charge trapping material layer CL cannot trap charges. As described above, the weight element according to the present embodiment may have a multi-level memory function according to the amount of charge stored in the charge trapping material layer CL.

FIG. 2 is a cross-sectional view illustrating a writing operation of the weight element of FIG. 1 .

Referring to FIG. 2 , the write voltage Vb may be applied to the drain electrode DE of the weight element, the selection voltage Vw may be applied to the second gate electrode GE2 , and the first gate electrode GE1 may be grounded. The second channel region C2 is opened due to the selection voltage Vw, and the write voltage Vb applied to the drain electrode DE may be transferred to the common region SD. The write voltage Vb transferred to the common area SD may have a slight voltage drop across the second channel area. Since a partial surface of the common area SD faces a partial surface of the charge trapping material layer CL, the write voltage Vb transferred to the common area may contribute to an electric field formed in the charge trapping material layer CL.

A voltage applied to the charge trapping material layer CL may be applied through a portion of the interface SD facing the charge trapping material layer CL. Referring to FIG. 2 , the first upper surface 11 is a partial surface close to the interface SD of the charge trapping material layer, and the first lower surface 12 is a region adjacent to the first channel region C1 in the interface SD. can face each other. An electric field due to the write voltage Vb may be formed between the first upper surface 11 and the first lower surface 12 . The first upper surface 11 and the first lower surface 12 facing each other may have a width sufficient to sufficiently form an electric field between the common area SD and the charge trapping material layer CL. For example, if the widths of the first upper surface 11 and the first lower surface 12 facing each other are too small, a sufficient electric field may not be formed between the common area SD and the charge trapping material layer CL.

Since the first gate electrode GE1 is grounded, the write voltage Vb may be distributed to the gate insulating layer GO, the charge trapping layer M1 and the first gate electrode GE1 of the first transistor TR1 . The voltage division may be divided according to the voltage division law according to the resistance value of each layer. For example, the write voltage Vb may be divided into a voltage Vt applied to the switching layer SL, a voltage Vc applied to the charge trap material layer CL, and a voltage Vi applied to the gate insulating layer GO. For example, when the voltage Vt is greater than the threshold voltage Vth of the switching layer SL, the switching layer SL is switched to a low resistance state, so that the charge trapping material layer CL may trap charges. The amount of charge captured by the charge trapping material layer CL may be determined according to the magnitude and duration of the voltage Vt applied to the switching layer SL.

The size of the write voltage Vb may change depending on the material, size, and shape of the charge trapping material layer CL and the switching layer SL, and may be, for example, 0V to 10V. The weighting device according to the present exemplary embodiment may operate at a relatively low voltage compared to 15V to 20V of a write voltage required for a floating gate type weighting device.

3 is a cross-sectional view illustrating an erase operation of the weight element of FIG. 1 .

Referring to FIG. 3 , the erase voltage Vw' may be applied to the first gate electrode GE1, the selection voltage Vw may be applied to the second gate electrode GE2, and the drain electrode DE may be grounded. The second channel region C2 is opened due to the selection voltage Vw, and the erase voltage Vw' is applied to the gate insulating layer GO, the charge trapping layer M1, and the first gate electrode GE1 of the first transistor TR1. can be distributed. In the erase operation, an electric field opposite to the write operation is formed through a partial surface of the common area SD and a partial surface of the charge trapping material layer CL facing each other.

When the voltage Vt applied to the switching layer SL is greater than the threshold voltage Vth, the charge trapping material layer CL may release the trapped charge. The size of the erasing voltage Vw' may vary depending on the material, size, and shape of the charge trapping material layer CL and the switching layer SL, and may be, for example, 0V to 10V. The level of the erase voltage Vw' may be selected to be the same as the level of the above-described write voltage Vb. The weight element according to the present embodiment may operate at a relatively low voltage compared to the level of the erase voltage required for the weight element of the floating gate type is 15V to 20V.

4A to 4C are cross-sectional views illustrating a read operation of the weight element of FIG. 1 .

As described above, since the first transistor (TR1 in FIG. 1 ) may be of a depletion type, the first channel region C1 may be in an open state even when no voltage is applied. As the amount of charges trapped in the charge trapping material layer CL increases, the magnitude of the current passing through the first channel region C1 may decrease. As the amount of charges trapped in the charge trapping material layer CL increases, the resistance of the first channel region C1 may increase. The read voltage Vr may be applied to the source electrode SE. When the selection voltage Vw is applied to the second gate electrode GE2 , the second channel region C2 may be opened.

The measurement current may flow through the drain electrode DE through the first channel region C1 and the second channel region C2. The measured current may correspond to the amount of charge captured in the charge trapping material layer CL, and the amount of charge may correspond to a weight value of the weight element. for example,

In the case of FIG. 4A , since there is no charge stored in the charge trapping material layer CL, the measurement current Ia may flow relatively large. When the measurement current Ia is measured in this way, it can be seen that the weight value 2 is stored in the weight element.

In the case of FIG. 4B , about half of the charge may be stored in the charge trapping material layer CL, and the measurement current Ib may flow smaller than the measurement current Ia. When the measurement current Ib is measured in this way, it can be considered that the weight value 1 is stored in the weight element.

In the case of FIG. 4C , charges may be fully stored in the charge trapping material layer CL, and the measurement current Ic may be smaller than the measurement current Ib. When the measurement current Ic is measured in this way, it can be considered that the weight value 0 is stored in the weight element.

The weight element according to the above-described example may store three types of multi-level weight values. However, the present invention is not limited thereto, and it goes without saying that the weight element may have various multi-level weights according to the volume and shape of the charge trapping material layer CL. The specific determination of the weight value may be made from the measured current value measured by a galvanometer connected to the drain electrode DE, a sensing analyzer, or the like.

In the present embodiment, the measurement current is measured at the drain electrode DE to determine the weight value, but the present invention is not limited thereto. For example, since the amount of charge captured in the charge trapping material layer CL may change the degree of passing the current in the first channel region C1, it may be sufficient to measure a criterion for quantitatively or qualitatively judging it. have. When determining qualitatively, it may be difficult to determine the multilevel in detail, and when determining quantitatively, it may be possible to determine the multilevel in detail. Any physical quantity, measurement current, voltage, resistance, etc. that can reflect the characteristics of the first channel region C1 may be measured, and a specific measurement method is not limited.

A specific value of the read voltage Vr may be selected to be smaller than the write voltage Vb and the erase voltage Vw' described above. For example, the read voltage may be selected from 0V to 4V. However, the read voltage is not limited to the above example, and an optimal value may be selected according to the material, size, and shape of the weight element.

5 is a cross-sectional view illustrating a weighting element according to another exemplary embodiment. The weight element according to the present embodiment is substantially the same as the weight element of the embodiment described with reference to FIGS. 1 to 4 except that the boosting electrode BE is formed on the rear surface of the substrate of the weight element. Therefore, the overlapping description will be omitted, and only the boosting electrode BE will be described.

Referring to FIG. 5 , the boosting electrode BE is positioned on the first channel region C1, but is spaced apart from the region where the common region SD and the charge trapping material layer CL face each other, and the source It may be located close to the region S1. The boosting electrode BE and the charge trapping material layer CL may face each other. For example, the second upper surface 21, which is a partial surface close to the source region S1, of the charge trapping material layer CL, and the second lower surface 21, which is a surface where the boosting electrode BE is in contact with the substrate SUB, face each other. can do. Referring to FIG. 5 , in the erase operation, a boosting voltage Vw' equal to the erase voltage Vw' applied to the first gate electrode GE1 may be applied to the boosting electrode BE located opposite to the substrate SUB. . For example, the boosting voltage Vw' applied to the boosting electrode BE may be applied to the second lower surface 22 , and may be offset from the erase voltage Vw' applied to the second upper surface 21 . This method of operation can be referred to as global self-boosting.

Since the boosting voltage Vw' and the erasing voltage Vw' cancel each other out, leakage of current to the source electrode SE may be prevented. The boosting electrode BE may be positioned to be sufficiently spaced apart from the common area SD, so that the boosting voltage VW' applied to the boosting electrode BE does not affect the electric field near the common area SD. have. For example, the second upper surface 21 and the first upper surface 11 may be sufficiently spaced apart. For example, the second lower surface 22 and the first lower surface 12 may be sufficiently spaced apart. Referring to FIG. 5 , the electric field between the second upper surface 21 and the second lower surface 22 may not affect each other with the electric field between the first upper surface 11 and the second lower surface 12 .

6 is a cross-sectional view showing a weight element according to another embodiment.

The weight element according to the present embodiment is substantially the same as the weight element of the embodiment described with reference to FIGS. 1 to 4 except that the weight element further includes a leak prevention region S2. Therefore, overlapping descriptions will be omitted, and descriptions will be made focusing on differences.

Referring to FIG. 6 , the weight element according to the present embodiment may include a leak prevention region S2 in contact with the source region S1 . The leakage preventing region S2 may prevent current leakage from the first channel region C1 to the source electrode SE. The leakage preventing region S2 may have a conductivity opposite to that of the source region S1 . The source electrode SE is formed on the leakage preventing region S2 and may not directly contact the source region S1 . For example, the leakage preventing region S2 may be surrounded by the source region S1 except for a surface in contact with the source electrode SE.

For example, in an NMOS-type weighting device, the source region S1 may have n-type conductivity, and the leakage prevention region S2 may have p-type conductivity. Since the leakage preventing region S2 and the source region S1 have a PN diode structure, a leakage current flowing from the first channel region C1 to the source electrode SE may be prevented.

7 is a cross-sectional view showing a weight element according to another embodiment of the present invention. This embodiment can be understood as a weighting element having three terminals. The weight element according to this embodiment is substantially the same as the weight element of the embodiment described with reference to FIGS. 1 to 4 except that the first gate electrode GE1 and the source electrode SE of the weight element are electrically connected to each other. is the same as Therefore, overlapping descriptions will be omitted, and descriptions will be made focusing on differences.

Referring to FIG. 7 , the first gate electrode GE1 and the source electrode SE may be electrically connected to each other. . The source electrode SE and the first gate electrode GE1 of the weight element according to the present embodiment may function as one terminal. A neural network composed of weight elements having a three-terminal structure may have a smaller area than a neural network composed of weight elements having a four-terminal structure. The three-terminal weight element can be operated in a similar manner to the four-terminal weight element described above. Three terminals of the three-terminal weight element are the first gate electrode GE1 connected to the source electrode SE, the second gate electrode GE2, and the drain electrode DE.

8 is a diagram illustrating a write operation of the weight element of FIG. 7 .

Referring to FIG. 8 , the write voltage Vb may be applied to the drain electrode DE of the weight element, the selection voltage Vw may be applied to the second gate electrode GE2 , and the first gate electrode GE1 may be grounded. The second channel region C2 is opened due to the selection voltage Vw, and the write voltage Vb applied to the drain electrode DE may be transferred to the common region SD.

Since a partial surface of the common area SD faces a partial surface of the charge trapping material layer CL, the write voltage Vb transferred to the common area may contribute to an electric field formed in the charge trapping material layer CL. Since the first gate electrode GE1 is grounded, the write voltage Vb may be distributed to the gate insulating layer GO, the charge trapping layer M1 and the first gate electrode GE1 of the first transistor TR1 . The voltage division may be divided according to the voltage division law according to the resistance value of each layer. A write operation method of such a three-terminal weight element may be substantially the same as a write operation of a four-terminal weight element.

9 is a diagram illustrating an erase operation of the weight element of FIG. 7 .

Referring to FIG. 9 , the erase voltage Vw' may be applied to the first gate electrode GE1, the selection voltage Vw may be applied to the second gate electrode GE2, and the drain electrode DE may be grounded. The second channel region C2 is opened due to the selection voltage Vw, and the erase voltage Vw' is applied to the gate insulating layer GO, the charge trapping layer M1, and the first gate electrode GE1 of the first transistor TR1. can be distributed. The erase operation method of the three-terminal weight element may be substantially the same as the erase operation method of the above-described four-terminal weight element.

In addition, since the first gate electrode GE1 and the source electrode SE are electrically connected in the erasing operation of the three-terminal weight element, the erasing voltage Vw' may be transferred to the source region S1. The electric field formed by the erase voltage Vw' transmitted through the source region and the electric field formed by the erase voltage Vw' transferred to the charge trapping layer M1 may cancel each other out. The operation method of such a three-terminal weight device may be called intrinsic self-boosting.

Referring to FIG. 9 , the charge trapping material layer CL and the source region S1 may face each other with the gate insulating layer GO interposed therebetween. For example, the third lower surface 32 which is a partial region close to the first channel region C1 of the source region S1 and the third upper surface ( 31) can face each other. For example, the erasing voltage Vw' may be transmitted to the third upper surface 31, the erasing voltage Vw' may be transmitted to the third lower surface 31, and the respective erasing voltages Vw' may be offset from each other.

An electric field formed between the common region SD and the charge trapping layer M1 and an electric field that cancel each other in the source region S1 may be sufficiently spaced apart. Accordingly, the cancellation of the erase voltage Vw' transferred to the source region S1 and the erase voltage Vw' transferred to the first gate electrode GE1 may not affect the operation of the weight element. For example, the third upper surface 31 and the first upper surface 11 may be sufficiently spaced apart. For example, the third lower surface 32 and the first lower surface 12 may be sufficiently spaced apart. Referring to FIG. 9 , the electric field between the third upper surface 31 and the second lower surface 32 may not affect each other with the electric field between the first upper surface 11 and the second lower surface 12 .

The weight element of the internal self-boosting method does not require a separate boosting electrode (BE in FIG. 5), unlike the weight element of the global self-boosting method. Accordingly, the weight element of the internal self-boosting method may have a simpler structure than the weight element of the global self-boosting method.

The four-terminal type weight element may be operated by an internal self-boosting method only in an erase operation by connecting the source electrode SE and the first gate electrode GE1 by switching. In this case, it is possible to effectively prevent leakage of current to the source electrode SE without a separate leakage preventing region ( S2 in FIG. 6A ) like the weight element of FIG. 6 .

10A and 10B are diagrams illustrating an operation method for adjusting a weight of a weight element. A pulse signal may be applied to the weight element according to the present embodiment for weight control. A neural network, which will be described later, may include a plurality of weight elements, and may reflect weights to adjust a functional relationship between an input signal and an output signal.

The weight element according to the present embodiment is substantially the same as the weight element according to the embodiment described with reference to FIGS. 7 to 9 . Accordingly, a description of the overlapping configuration of the weight element will be omitted. In addition, although the weight element according to the present embodiment is a three-terminal weight element as an example, it is not limited thereto and may include the above-described four-terminal weight element.

Referring to FIG. 10A , a pulse voltage may be applied to the first gate electrode GE1 in order to increase the weight of the weight element. Except that the pulse voltage is applied to the first gate electrode GE1 , it is substantially the same as the above-described writing operation of the weight element, and thus the overlapping description will be omitted. The weight increase amount of the weight element may be proportional to the number of pulse voltages applied to the first gate electrode GE1 . The pulse voltage may have a magnitude greater than or equal to the above-described write voltage. The holding time per pulse of the pulse voltage may be determined differently depending on the characteristics of the weight element. For example, the holding time per pulse may be determined differently depending on the material of the switching layer SL, and specifically, one pulse may be long enough to change the resistance state of the switching layer SL.

Referring to FIG. 10B , a pulse voltage may be applied to the drain electrode DE in order to reduce the weight of the weight element. Except that the pulse voltage is applied to the drain electrode DE, it is substantially the same as the above-described erasing operation of the weight element, and thus the overlapping description will be omitted. The weight reduction amount of the weight element may be proportional to the number of pulse voltages applied to the drain electrode DE. The pulse voltage may have a magnitude greater than or equal to the above-described erase voltage. As described above, the holding time per pulse of the pulse voltage may be determined differently depending on the characteristics of the weight element.

11 is a cross-sectional view illustrating a weighting device according to another exemplary embodiment. Referring to FIG. 11 , the first channel region C1 and the second channel region C2 of the substrate SUB may have different conductivity. The structures of the first transistor TR1 and the second transistor TR2 except for the first channel region C1 and the second channel region C2 are the same as those of FIGS. 1 to 4 , and thus the same description will be omitted. do.

In the weight element according to the present embodiment, the first transistor TR1 is a PMOS transistor positioned on the first channel region C1 having n-type conductivity, and the second transistor TR2 is a first transistor having p-type conductivity. It may be an NMOS transistor positioned on the 2-channel region C2. For example, the first transistor TR1 is a PMOS formed on a well N-well formed with an n-type dopant, and the second transistor TR2 is formed on a substrate SUB doped with a p-type dopant. It may be NMOS.

For example, the source region S1 and the common region SD may be formed with a p-type dopant in an n-type well (N-well). Accordingly, since the source region S1 and the n-type well N-well surrounding the source region S1 have opposite conductivity, a PN diode structure can be formed. The weight element according to the present exemplary embodiment may prevent a reverse flow of current from the first channel region C1 to the source electrode SE. These embodiments are merely examples and are not limiting. For example, the first transistor TR1 may be an NMOS formed on a well formed with a p-type dopant, and the second transistor TR2 may be a PMOS formed on a substrate SUB doped with an n-type dopant. Alternatively, the first transistor TR1 may be formed on the substrate SUB, and the second transistor TR2 may be formed on the well.

12 is a cross-sectional view illustrating a weight element according to another embodiment. Since the weight element according to the present embodiment is substantially the same as the weight element of FIG. 11 except for the material of the switching layer SL, the overlapping description will be omitted below. Referring to FIG. 12 , the switching layer SL may include a nanofilamentary material in which a low resistance state is formed by the nanofilaments.

The nanofilamentary material may be a material in which conductive nanofilaments are formed when a voltage greater than or equal to a specific value inherent to the material is applied. The nanofilament may refer to a conductive path formed by a voltage. When a voltage less than a specific value is applied to the nanofilamentary material, since the nanofilament is not formed, it may be relatively difficult to flow a current.

The nanofilamentary material may include nanofilaments such as TiO _x . For example, when a voltage is applied to the nanofilamentary material, TiOx or the like inside may form nanofilaments to form a low resistance state. Depending on the voltage applied to the nanofilamentary material, the number or shape of the nanofilaments may appear differently for each material. Accordingly, the resistance behavior of the nanofilamentary material may be different. When the switching layer SL is formed of a nanofilamentary material, the resistance switching time may be very fast in nanosecond units.

13 is a cross-sectional view illustrating a weighting device according to another exemplary embodiment. 14 is a diagram illustrating a current curve versus applied voltage of the PN diode layer according to FIG. 13 .

Referring to FIG. 13 , the switching layer SL may include a PN diode layer including a P-type diode layer and an N-type diode layer. Since the weight element according to the present embodiment is substantially the same as the weight element of FIG. 11 except for the material of the switching layer SL, the overlapping description will be omitted below. The PN diode layer may be formed by combining the above-described threshold voltage conversion materials. The PN diode layer can facilitate charging of the charge of the charge trapping layer M1 and effectively prevent discharging. Compared to other embodiments of the above-described switching layer SL, the PN diode layer can apply a write voltage smaller than the erase voltage, thereby saving power.

14, in the PN diode layer applied voltage versus current curve, the positive bias voltage region A1 represents a low resistance region in which current can flow even when a weak voltage is applied, and the negative bias voltage region ( A2) indicates a high resistance region where no current flows even when a voltage is applied. In the breakdown voltage region (A3), the reverse bias voltage of the diode exceeds the limit value and the resistance value is lowered due to the breakdown of the resistance so that the current decreases. Represents a region of low resistance that can flow. The boundary voltage between the negative bias voltage region A2 and the breakdown voltage region A3 may be referred to as a breakdown voltage.

The operation of the PN diode layer of the weight element according to the present embodiment will be described with reference to FIG. 14 . The parts common to the operation method of the above-described weight element will be briefly described.

In the write operation of the weight element according to the present embodiment, the write voltage may be applied through the drain electrode DE to distribute a positive bias voltage to the PN diode layer. Since the PN diode layer is located in the positive bias voltage region A1 of FIG. 14 , the charge trapping material layer CL may trap charges.

In the erase operation of the weight element according to the present embodiment, the erase voltage may be applied through the first gate electrode GE1 to distribute a negative bias voltage to the PN diode layer. The PN diode layer may be located in the negative bias voltage region A2 or the breakdown voltage region A3 of FIG. 14B . When the voltage applied to the PN diode layer is equal to or greater than the breakdown voltage, the PN diode layer is located in the breakdown voltage region A3, so that the charge trapping material layer CL can discharge charges. When the voltage applied to the PN diode layer is less than the breakdown voltage, the PN diode layer is located in the negative bias voltage region A2, and the charge trapping material layer CL cannot discharge charges.

15A to 15D are cross-sectional views schematically illustrating another weight element and an operation method thereof. Referring to FIG. 15A , the weighting device according to the present embodiment may be a 6-terminal weighting device including 4 transistors TR3, TR4, TR5, and TR6.

The weight element according to the present embodiment includes a third transistor TR3 including a third gate electrode GE3, a first electrode E1, and a second electrode E2, and the third transistor TR3 and the A fourth transistor TR4 that shares the second electrode E2 and includes a fourth gate electrode GE4 and a third electrode E3 , and includes a fifth gate electrode GE5 and a fourth electrode E4 . ), and may include a sixth transistor TR6 including a sixth gate electrode GE6 and a fifth electrode E5 .

The names of the third transistor TR3 , the fourth transistor TR4 , the fifth transistor TR5 , and the sixth transistor TR6 are the first transistor ( TR1 in FIG. 1 ) and the second transistor ( FIG. 1 ) of the above-described embodiment. to distinguish it from TR2) of

The third transistor TR3 may use the first common area SD1 as a drain, and the fourth transistor TR4 may use the first common area SD1 as a source. The fifth transistor TR5 may use the second common area SD2 as a drain, and the sixth transistor TR6 may use the second common area SD2 as a source.

The weight element according to the present embodiment may include a charge trapping layer M2 electrically connected to the first electrode E1 and the third electrode E3 . The weight element according to the present embodiment may include an interconnect IC connecting the charge trapping layer M2 and the sixth gate electrode GE6. The terminals for controlling the operation of the weight element according to the present embodiment include the third gate electrode GE3, the second electrode E2, the fourth gate electrode GE4, the fourth electrode E4, and the fifth gate electrode ( GE5) and six of the fifth electrodes E5.

In the weight element according to the present embodiment, the charge trapping layer M2 may be disposed on the first electrode E1 and the third electrode E3 . In the weight element according to the above-described embodiment, the charge trapping layer (M1 in FIG. 1) was located on the first channel region (C1 in FIG. 1) of the transistor, and the cross-sectional area of the charge trapping layer (M1 in FIG. 1) is It could be limited by the area of the first channel region (C1 in FIG. 1 ). As described above, since the volume of the charge trapping layer M2 can determine the size of the multi-level, the cross-sectional area of the charge trapping layer M2 may need to be sufficiently wide in order for the weight element to have a large multi-level of several tens of levels or more. Accordingly, the charge trapping layer M2 may be disposed on the first electrode E1 and the third electrode E3 to have a sufficient cross-sectional area without limiting the area of the first channel region (C1 in FIG. 1 ).

A write operation of the weight element according to the present embodiment will be described with reference to FIG. 15B .

A write voltage Vb may be applied to the second electrode E2 , and a selection voltage Vw may be applied to either the third gate electrode GE3 or the fourth gate electrode GE4 . The fourth electrode E4 may be grounded, and a selection voltage Vw may be applied to the fifth gate electrode GE5 . As described above, the write voltage Vb may be divided into the switching layer SL and the charge trapping material layer CL through voltage distribution. For example, when the switching layer SL includes a PN diode layer, even when a small voltage is applied to the switching layer SL, the charge trapping material layer CL can capture the charge passing through the PN diode layer. have. For example, when the switching layer SL includes another material other than the PN diode layer, a voltage greater than or equal to the threshold voltage must be applied to change the resistance state of the switching layer SL, and the charge trapping material layer CL ) can trap charges.

An erase operation of the weight element according to the present embodiment will be described with reference to FIG. 15C. The second electrode E2 is grounded, and the selection voltage Vw may be applied to either the third gate electrode GE3 or the fourth gate electrode GE4 . An erase voltage Vw' may be applied to the fourth electrode E4 , and a selection voltage Vw may be applied to the fifth gate electrode GE5 . When the voltage applied to the switching layer SL exceeds the threshold voltage, charges trapped in the charge trapping material layer CL may escape to the first electrode E1 or the third electrode E3 . For example, when the switching layer SL includes a PN diode layer, a voltage greater than or equal to the breakdown voltage must be applied to the switching layer SL so that the charge trapping material layer CL can discharge charges. For example, when the switching layer SL includes another material other than the PN diode layer, a voltage greater than or equal to the threshold voltage must be applied to change the resistance state of the switching layer SL, and the charge trapping material layer CL ) can release this charge.

A read operation of the weight element according to the present embodiment will be described with reference to FIG. 15D.

A read voltage Vr may be applied to the fifth electrode E5 , and a selection voltage Vw may be applied to the fifth gate electrode GE5 . As described above, the weight value can be read by measuring the intensity of the current flowing through the fourth electrode E4. A separate voltage may not be applied to the third transistor ( TR3 in FIG. 15A ) and the fourth transistor ( TR4 in FIG. 15A ).

16 is a diagram schematically illustrating the principle of a neural network. The neural network may include at least one column of hidden layers between an input layer and an output layer. In the input layer, input information may be input as an electrical signal, and in the output layer, output information may be output as an electrical signal. The hidden layer may be a kind of black box that determines a correlation between input information and output information. The hidden layer can implement a non-linear functional relationship as well as a linear functional relationship. The hidden layer may include a plurality of the above-described weighting elements. The non-linear functional relationship implemented by the hidden layer may be determined by weight values of a plurality of weight elements included in the hidden layer.

A hidden layer can consist of a plurality of columns, and as the number of columns increases, complex nonlinear functional relationships can be implemented. A neural network including a plurality of hidden layers may be used for deep learning. Deep learning may refer to a learning method with high non-linearity.

The hidden layer may include a synapse and a perceptron. A synapse may mean a connection relationship between neurons shown as dots. The perceptron may be a configuration of a neural network that implements a functional relationship by adding weights to synapses and information transmitted through synapses. That is, the above-described weight element may correspond to a perceptron. Since the plurality of transistors included in the input layer correspond to the neurons of the actual neural network, they will be referred to as neuron transistors hereinafter.

17A to 17C are schematic diagrams illustrating a method of driving a weight element in a neural network. The neural network according to the present embodiment may have a schematic configuration including a perceptron composed of a neuron transistor and one weight element. The synapse may correspond to a connection relationship between the drain of the neuron transistor and the gate electrode of the weight element. For example, the neuron transistor may selectively switch the gate voltage applied to the weight element. In order for the neuron transistor and the weight element to exchange electrical signals, a synapse must be activated, which may correspond to activation of the channel region of the neuron transistor and the channel region of the weight element. 17A is a diagram illustrating a method of increasing a weight, FIG. 17B is a diagram illustrating a method of decreasing a weight, and FIG. 17C is a diagram illustrating a method of reading a weight.

17A and 17B , the synapse connecting the neuron transistor and the perceptron may be activated by applying the selection voltage Vw to the neuron and the weight element. Thereafter, the method of increasing or decreasing the weight value of the corresponding perceptron is substantially the same as the operation of the above-described weight element, and thus is omitted.

Referring to FIG. 17C , a weight value of the perceptron can be confirmed. Since the synapse connecting the neuron transistor and the perceptron does not need to be activated, the selection voltage Vw can be applied only to the weight element without applying the selection voltage to the neuron transistor.

18A to 18C are diagrams schematically illustrating the operation of a neural network composed of a plurality of rows of neuron transistors and a single row of perceptrons.

Referring to FIG. 18A , a plurality of neuron transistors may be two-dimensionally arranged as (a * b). In the two-dimensional array of (a * b), a may be a number representing a row, and b may be a number representing a column. For example, a transistor located at the top of the neural network is located in the first row, so a = 1, and a transistor located in a lower row may have a = 2. For example, since the leftmost transistor in the neural network is located in the first column, b = 1, and the transistor located in the right column may have b = 2. For example, the transistor located at (1 * 1) may mean a neuron transistor located in the first column of the first row with respect to the upper left corner of the neural network.

The neuron transistor according to the present embodiment may be arranged in (n * n) two-dimensionally. That is, n transistors may be arranged along a row and n transistors may be arranged along a column. This embodiment is for convenience of description and is not limited thereto.

The source electrodes of each neuron transistor located in the same row may be connected to each other to form an input line. Referring to FIG. 18A , in order to distinguish the input lines for each row, the input lines are W _D1 to W _Dn . can be expressed as An input signal may be applied to the input line.

The gate electrodes of each neuron transistor positioned in the same column may be connected to each other to form a selection line. Referring to FIG. 18A , in order to distinguish the selection lines for each column, the selection lines may be referred to as selection lines x ₁ to x _n . A selection voltage may be applied to the selection line. When a selection voltage is applied to a specific selection line, all of the transistors in the corresponding column may be selected. Selection may mean that a channel region of a transistor in a corresponding column is opened.

The perceptron may include a plurality of weighting elements according to the above-described embodiment.

Referring to FIG. 18A , when the neuron transistors are two-dimensionally arranged in (n * n), in the perceptron, n weight elements may be arranged one-dimensionally. For example, the drain electrode of each neuron transistor positioned in the same row may be electrically connected to the first gate electrode of the weight element positioned in the same row to form a synapse. As described above, the drain electrode of each weight element can adjust the weight of each weight element by applying a write voltage. The drain electrode of each weight element can be _dividedly represented by input lines W _C1 to WCN.

The second gate electrodes of the weight elements constituting the perceptron may be connected to each other to form a selection line. Referring to FIG. 18A , the selection line of the perceptron may be represented by y1. When the selection voltage Vw is applied to the selection line y1, all weight elements in the corresponding column may be selected. Selection of the weight element may mean that the second channel region C2 is in an open state. The details will be omitted as described above.

The neural network adjusts the voltages applied to the input lines W _D1 to W _{Dn , the} selection lines x ₁ to x _{n , the} input lines W _C1 to W _CN , and the selection line y1 to obtain the weights h1 to hn of each weight element included in the perceptron. can be adjusted

Referring to FIG. 18B , write and erase operations of the neural network will be described. For example, the selection voltage Vw may be applied to the selection line x2 and not applied to x1 and x3 to xn. Accordingly, the neuron transistors located in the second column can be selected. Since the selection voltage Vw is applied to the selection line y1 , the weight element connected to the selection line y1 may be activated. Accordingly, a synapse between the neuron transistor located on the selection line x2 and the weight element located on the selection line y1 may be activated. For example, an input line write voltage Vc1 may be applied to the input line W _C1 , and the input line W _D1 may be grounded. Charge flows in through a synapse between the neuron transistor located at (1 * 2) and the weight element located in the first row, so that the weight h1 may be increased. For example, the input line W _Cn is grounded and the input wire W _Dn An erase voltage V _Dn may be applied. The weight hn may be reduced because charges are leaked through the synapse between the neuron transistor located at (n * 2) and the weight element located at the nth row.

As described above, a pulse voltage may be applied as the write voltage and a pulse voltage may be applied as the erase voltage.

Referring to FIG. 18C , a read operation of the neural network will be described. For example, the read voltage V _R may be applied to the input line W _c1 . The weight h1 can be read by measuring the measurement current flowing through the weight element located in the first row. For example, the read voltage V _R may be applied to the input line W _cn , and as a result, the weight hn may be read. As described above, the weight value of the corresponding weight element may be read from the current value measured through the signal reader (S/A) or the ammeter (not shown). Since the reading of the weights h1 to hn may be independent of the synaptic activity with the neuron transistor, the selection voltage may not be applied to the selection lines x1 to xn.

In the neural network according to FIGS. 18A to 18C , the perceptron is composed of a singular column, but is not limited thereto. As described above, the neural network may include a perceptron composed of a plurality of columns, and such a neural network may be used for deep learning.

19 is a diagram related to learning using a neural network. Neural networks can be divided into continuous learning and discrete learning. The neural network using the above-described weight elements can be used for discrete learning in that it is a network using a limited number of weight elements.

A neural network including a non-volatile weighting element may be used for supervised learning and unsupervised learning. Control learning is a method of machine learning to infer a specific function from training data. Training data refers to predetermined input information and output information. In general, input information is included in a vector form, and output information determined for each input information vector is determined. Controlled learning refers to learning a neural network so that output information determined for such input information comes out, and in the present disclosure, the neural network can be trained by adjusting weights. Classification refers to determining what kind of value a given input vector is by using a learned neural network.

Referring to FIG. 20 , classification may be determined from the relationship between the input (x1) and the output (x2) in the controlled-learned neural network. For example, for classification, a controlled-trained neural network is prepared so that output B is generated for input A, input unknown input values C and D to this network, and check whether the result corresponds to output B. It can be judged from whether Referring to FIG. 20 , input values corresponding to output B values are indicated by circles, and input values not corresponding to output values B are indicated by cross marks. These circle and cross-mark values correspond to classifications according to whether the data correspond to the controlled-trained neural network.

Uncontrolled learning is a type of machine learning that is not given a target value of output information with respect to input information, unlike the aforementioned controlled learning. An example of uncontrolled learning is clustering. Clustering means statistically analyzing the output value of the input of the neural network acquired through uncontrolled learning and dividing it into groups.

Referring to FIG. 21 , a cluster may be determined by determining the relationship between the input (x1) and the output (x2) in the uncontrolled learned neural network. For example, by comparing output values according to input values input to the uncontrolled learned neural network, coordinates belonging to similar ranges can be grouped into one cluster. Referring to FIG. 21 , the coordinates of the input value and the output value are indicated by circles, and clusters are indicated by dotted lines depending on whether they are included in the similar range.

Up to now, exemplary embodiments of a weighting element, a neural network, and a method of operating a weighting element have been described and shown in the accompanying drawings in order to facilitate understanding of the present invention. However, it should be understood that these examples are merely illustrative of the present invention and not limiting thereof. And it should be understood that the present invention is not limited to the description shown and described. This is because various other modifications may occur to those skilled in the art.

SUB: Substrate GO: Gate Insulation Layer
C1: first channel region C2: second channel region
GE1: first gate electrode GE2: second gate electrode
CL: charge trapping material layer SL: switching layer
S1 : Source area S2 : Leakage prevention area
D1 : Drain area SD : Interface area
SE: source electrode DE: drain electrode
GE1: first gate electrode GE2: second gate electrode
M1: charge trapping layer

Claims (20)

Board;
On the substrate, a source region and a common region are spaced apart from each other, a source electrode electrically connected to the source region, a first channel region positioned between the source region and the common region, and on the first channel region A first gate insulating layer provided, a charge trapping material layer provided on the first gate insulating layer, a switching layer provided on the charge trapping material layer and capable of switching between a high resistance state and a low resistance state, and on the switching layer and a first gate electrode provided on a first transistor that blocks the movement of charges between the first gate electrode and the charge trapping material layer in the low resistance state and enables the movement of charges between the first gate electrode and the charge trapping material layer in the low resistance state; and
A drain region disposed on the substrate to be spaced apart from the common region, a drain electrode electrically connected to the drain region, a second channel region positioned between the common region and the drain region, and provided on the second channel region A weight element comprising: a second transistor including a second gate insulating layer, a second gate electrode provided on the second gate insulating layer, and using the common area as a source. The method of claim 1,
The first transistor is
a leak prevention region disposed on the substrate in contact with the source region and forming a PN diode structure with the source region;
The source electrode is a weight element in contact with the leakage prevention region. 3. The method of claim 2,
The leak prevention region is a weight element surrounded by the source region except for an area in contact with the source electrode. The method of claim 1,
The first channel region and the second channel region have opposite conductivity to each other. 5. The method of claim 4,
The first transistor is
and a well surrounding the source region, the first channel region, and the common region in the substrate and having a conductivity opposite to that of the second channel region. The method of claim 1,
and the first gate electrode and the source electrode are electrically connected to each other. The method of claim 1,
and a boosting electrode facing the charge trapping material layer with the first gate insulating layer and the substrate interposed therebetween. The method of claim 1,
The switching layer is a weight element including a nanofilamentary material capable of being switched to the low resistance state by forming conductive nanofilaments according to voltage application. The method of claim 1,
The switching layer is a weight element including a PN diode layer. The method of operating the weight element according to claim 1, comprising:
opening the second channel region by applying a selection voltage to the second gate electrode;
applying a write voltage to the drain electrode; and
grounding the first gate electrode;
A method of operating a weighting device in which electric charges are introduced into the charge trapping material layer through the first gate electrode by the write voltage to write information into the charge trapping material layer. The method of operating the weight element according to claim 1, comprising:
opening the second channel region by applying a selection voltage to the second gate electrode;
applying an erase voltage to the first gate electrode; and
Including; grounding the drain electrode;
A method of operating a weighting device for erasing information by removing charges trapped in the charge trapping material layer by the erasing voltage. The method of operating the weight element according to claim 1, comprising:
opening the second channel region by applying a selection voltage to the second gate electrode;
applying a read voltage to the source electrode; and
and reading the amount of charge trapped in the charge trapping material layer by measuring the measured current at the drain electrode. 11. The method of claim 10,
The step of applying the write voltage comprises:
Including; applying a pulse voltage to the drain electrode to reflect the weight;
The method of operating a weight element in which the reflection of the weight is controlled by the number of times the pulse voltage is applied. 12. The method of claim 11,
The step of applying the erase voltage comprises:
applying a pulse voltage to the first gate electrode to reflect the weight;
The method of operating a weight element in which the reflection of the weight is controlled by the number of times the pulse voltage is applied. a plurality of weight elements according to claim 1; and
and a plurality of neuron transistors selectively switching gate voltages applied to the plurality of weight elements. 16. The method of claim 15,
The plurality of neuron transistors are two-dimensionally arranged,
The drain electrodes of the plurality of neuron transistors are respectively connected to the first gate electrodes of the plurality of weight elements,
a selection line connected to a gate electrode of a neuron transistor positioned in the same column to apply a selection voltage; and
The neural network further comprising: an input line connected to a source electrode of a neuron transistor positioned in the same row to apply an input voltage. 16. The method of claim 15,
A neural network in which the plurality of weight elements are one-dimensionally or two-dimensionally arranged. The method of operating a neural network according to claim 15, comprising:
A method of operating a supervised learning neural network in which input information input through the plurality of neuron transistors and output information output through the plurality of weight elements are predetermined, and a weight value of the neural network corresponding thereto is determined. . The method of operating a neural network according to claim 15, comprising:
An operating method of an unsupervised learning neural network that allows the weight value of the neural network to be autonomously determined according to input information input through a neuron transistor. a third transistor having a third gate electrode, a first electrode, and a second electrode;
a fourth transistor sharing the third transistor and the second electrode and having a fourth gate electrode and a third electrode;
a fifth transistor having a fifth gate electrode and a fourth electrode and having a common area as a drain;
a sixth transistor having a sixth gate electrode and a fifth electrode and using the common area as a source;
a switching layer formed on the first electrode and the third electrode and capable of being switched between a high resistance state and a low resistance state;
a charge trapping material layer disposed on the switching layer and configured to trap or release charges according to a resistance state of the switching layer; and
and an interconnect connecting the charge trapping material layer and the sixth gate electrode.

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