KR102427975B1 - Conductance-based sequential matrix multiplication neural network by controlling weights with transistors - Google Patents

Abstract

A conductance-based sequential matrix multiplication neural network capable of adjusting a weight with a transistor according to an embodiment of the present invention includes a word line, an input line and a transistor connected to a diode, an output line, and a diode connected to the transistor, and an output line is connected to the selection transistor.

Description

CONDUCTANCE-BASED SEQUENTIAL MATRIX MULTIPLICATION NEURAL NETWORK BY CONTROLLING WEIGHTS WITH TRANSISTORS

The present invention relates to a neural network, and more particularly, to a conductance-based sequential matrix multiplication neural network capable of controlling a weight with a transistor.

The mobile neural processor performs learning by a server or computer, and stores the learning results in the mobile neural processor to perform inference. At this time, it is preferable that the value stored in the weight of the neural processor be multi-level, but there is a limit to the multi-level value. width) and then store the value as the mobile neural processor weight. This weight may be stored in a non-volatile memory or a volatile memory.

For servers, there is Google's Tensor Processing Unit (TPU), which stores weight values in DRAM, fetches them, and sends them to the matrix multiply unit (MMU). The output calculation result is sent back to the matrix multiplier input together with the new weight value stored in the DRAM, and circulated until the final output result is obtained.

When the weights are stored and used in the nonvolatile memory, the inference speed is fast, but there is a disadvantage in that the circuit overhead increases because all hidden layers must be manufactured. In the case of Google's TPU, weight information is stored outside the neural network, and the inference speed is reduced, but circuit overhead can be reduced because it is sequentially calculated while using the same neural network again.

The above description is only for helping the understanding of the background of the technical spirit of the present invention, and therefore it cannot be understood as the content corresponding to the prior art known to those skilled in the art.

In order to learn data with a neural network and perform inference and prediction using the learned result, weights need to be adjusted. Since there is a physical limit to manufacturing a weight element in multi-level, it cannot follow the weight bit-width used in software. For example, a 16-bit wide multilevel resistive memory material with 65,536 resistance levels is currently difficult to implement. Therefore, it is necessary to devise a structure and operation method of a matrix multiplier that can perform matrix multiplication while inputting weight values as flexibly as software.

As a method of changing the resistance value (or conductance value) to change the weight, there is a method of manufacturing resistors having various resistance values and selecting the necessary resistors, or there is a method of manufacturing resistors having the same fixed resistance value and selecting the resistors as a group. In this case, the circuit overhead increases because the circuit becomes more complex. In addition, manufacturing as many hidden layers as necessary is another problem that limits the size of a chip. Therefore, rather than using a memory material as a weight, it is preferable to devise a method for multileveling the channel conductance of a transistor or multileveling the current flowing through the transistor using a transistor.

In order to achieve the above object, in accordance with an embodiment of the present invention, a conductance-based sequential matrix multiplication neural network capable of adjusting a weight with a transistor includes: a transistor connected to a word line, an input line, and a diode; an output line, and a diode coupled to the transistor, the output line coupled to the selection transistor.

The voltage applied to the word line may be a pulse voltage.

The weight may be adjusted by controlling the pulse amplitude of the pulse voltage.

The weight may be adjusted by controlling the pulse width of the pulse voltage.

The word line and the output line may be positioned perpendicular to each other.

The input line may be connected to an input, and the selection transistor may be connected to an output.

A DC voltage may be applied to the input, and the output may be connected to a charge integrator.

A conductance-based sequential matrix multiplication neural network capable of adjusting a weight with a transistor according to an embodiment of the present invention includes a first word line, a first input, a first transistor connected to a first diode, and an output line connected to the a first weight cell comprising a first diode; a second weight cell comprising a second word line, a second input, a second transistor coupled to a second diode, and the second diode coupled to an output line, the output line comprising a first select transistor and Connected.

Voltages applied to the first word line and the second word line may be different pulse voltages.

The different pulse voltages may have different pulse amplitudes.

A weight output to the output line may be adjusted by controlling the pulse amplitudes of the different pulse voltages.

The different pulse voltages may have different pulse widths.

A weight output to the output line may be adjusted by controlling the pulse widths of the different pulse voltages.

The first word line and the second word line may be positioned parallel to each other, and the first word line, the second word line, and the output line may be positioned perpendicular to each other.

A conductance-based sequential matrix multiplication neural network capable of adjusting a weight with a transistor according to an embodiment of the present invention includes a first word line, a first input, a first transistor connected to a diode, and a first output line a first weight cell comprising a diode; a second weight cell comprising a second word line, a second input, a second transistor coupled to a diode, and the diode coupled to a first output line; a third weight cell comprising a third transistor coupled to a first word line, a first input, and a diode, and the diode coupled to a second output line; a fourth weight cell comprising a second word line, a second input, and a fourth transistor coupled to a diode, and the diode coupled to a second output line, wherein the first output line comprises a first select transistor and connected, and the second output line is connected to a second selection transistor.

Voltages applied to the first word line and the second word line may be different pulse voltages.

The different pulse voltages may have different pulse amplitudes or different pulse widths.

The weight may be adjusted by controlling the pulse amplitudes or pulse widths of the different pulse voltages.

By selectively applying a gate voltage to the first selection transistor and the second selection transistor, weights of weight cells output to the first output line and the second output line may be selectively adjusted.

By sequentially applying a gate voltage to the first selection transistor and the second selection transistor, weights of weight cells output to the first output line and the second output line may be sequentially adjusted.

Such a conductance-based sequential matrix multiplication neural network capable of adjusting weights with transistors according to an embodiment of the present invention can adjust weights flexibly, reduce circuit load, and achieve matrix multiplication unit chip size (matrix multiplication unit chip size). ) can also be minimized.

1 is a circuit diagram schematically illustrating a neural network according to an embodiment of the present invention.
2 is a circuit diagram schematically illustrating a weight cell of a neural network according to an embodiment of the present invention.
3 and 4 are circuit diagrams schematically illustrating an operating principle of a weight cell of a neural network according to an embodiment of the present invention.
5 is a circuit diagram illustrating a weight cell array of a neural network, word lines, bit lines, and selection transistors connected to the array, and respective inputs and outputs according to an embodiment of the present invention.
6 and 7 are circuit diagrams for explaining a sequential matrix multiplication operation of a neural network according to an embodiment of the present invention.

The contents described in the technical field of the background of the present invention are only for helping the understanding of the background of the technical idea of the present invention, and therefore it can be understood as content corresponding to the prior art known to those skilled in the art of the present invention. none.

In the following description, for purposes of explanation, numerous specific details are set forth to aid in understanding various embodiments. It will be evident, however, that various embodiments may be practiced without these specific details or in one or more equivalent manners. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments.

In the drawings, the size or relative size of layers, films, panels, regions, etc. may be exaggerated for clarity. Also, like reference numbers indicate like elements.

Throughout the specification, when a part is "connected" with another part, this includes not only the case of being "directly connected" but also the case of being "indirectly connected" with another element interposed therebetween. . However, if it is stated that a part is "directly connected" to another part, this will mean that there is no other element between the part and the other part. "At least one of X, Y, and Z" , and "at least any one selected from the group consisting of X, Y, and Z" means one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY , YZ, ZZ) Herein, "and/or" includes any combination of one or more of those elements.

Herein, although terms such as first, second, etc. may be used to describe various elements, elements, regions, layers, and/or sections, such elements, elements, regions, layers, and/or or sections are not limited to these terms. These terms are used to distinguish one element, element, region, layer, and/or section from another element, element, region, layer, and/or section. Accordingly, a first element, element, region, layer, and/or section in one embodiment may be referred to as a second element, element, region, layer, and/or section in another embodiment.

Spatially relative terms such as "below", "above", etc. may be used for descriptive purposes, thereby describing the relationship of one element or feature to another element(s) or feature(s) as shown in the drawings. do. This is only used to indicate the relationship of one component to another component in the drawing, and does not mean an absolute position. For example, if the device shown in the figures is turned over, elements depicted as being "below" other elements or features are positioned "above" the other elements or features. Thus, in one embodiment, the term "below" may include both up and down. In addition, the device may be otherwise oriented (eg, rotated 90 degrees or in other orientations), and such spatially relative terms used herein are interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and not for the purpose of limitation. Throughout the specification, when a part "includes" a certain element, it means that other elements may be further included, rather than excluding other elements, unless otherwise stated. Unless otherwise defined, terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

1 is a circuit diagram schematically illustrating a neural network according to an embodiment of the present invention.

Referring to FIG. 1 , a neural network according to an embodiment of the present invention includes an input neuron 10 , an output neuron 20 , and a weight cell 30 . The synapse 30 device is to be disposed at the intersection of a row line (R) extending horizontally from the input neuron 10 and a column line (C) extending vertically from the output neuron 20 can For convenience of explanation, four input neurons 10 and four output neurons 20 are illustrated in FIG. 1 , respectively, but the present invention is not limited thereto.

The input neuron 10 transmits electrical pulses to the weight cell 30 through the row line R in a learning mode, a reset mode, a correction or a reading mode. can

The output neuron 20 may receive an electrical pulse from the weight cell 30 through the column line C in the learning mode, the reset mode, or the correction or read mode.

2 is a circuit diagram schematically illustrating a weight cell of a neural network according to an embodiment of the present invention.

In order to flexibly apply the weight bit width according to the embodiment of the present invention, the weight is newly defined. Until now, G was multi-leveled by applying I = GV (current = conductance × voltage) in a weight based on conductance. At this time, if the Q=IΔt relationship is added and the Q=GΔtV relationship is applied, the weight can be adjusted by the conductance G and the current flowing time Δt, so the room for multileveling increases. Therefore, the weight is defined as GΔt.

Referring to FIG. 2 , a conductance-based sequential matrix multiplication neural network capable of adjusting a weight with a transistor according to an embodiment of the present invention includes a transistor and a diode. The transistor is connected to the word line WL, the input line BL, and the diode, the diode is connected to the output line and the transistor, and the output line is connected to the selection transistor ST.

According to an embodiment of the present invention, the voltage applied to the word line WL may be a pulse voltage. As an embodiment, the weight may be adjusted by controlling the pulse amplitude of the pulse voltage. As another embodiment, the weight may be adjusted by controlling the pulse width of the pulse voltage.

In an embodiment, the word line WL and the output line may be positioned to be orthogonal to each other. The input line may be connected to the input, and the selection transistor ST may be connected to the output. A DC voltage may be applied to the input, and the output may be connected to a charge integrator.

3 and 4 are circuit diagrams schematically illustrating an operating principle of a weight cell of a neural network according to an embodiment of the present invention.

Referring to FIG. 3 , a conductance-based sequential matrix multiplication neural network capable of adjusting weights with transistors according to an embodiment of the present invention includes a first weight cell including a first transistor and a first diode, a second transistor and a second and a second weight cell comprising a diode. The first transistor is coupled to the first word line, the first input, and the first diode, and the first diode is coupled to the first transistor and the output line. A second transistor is coupled to the second word line, the second input, and the second diode, and the second diode is coupled to the second transistor and the output line. The output line is connected to the first select transistor. As an embodiment, the first word line and the second word line may be positioned parallel to each other, and the first word line, the second word line, and the output line may be positioned perpendicular to each other. The first select transistor may be coupled to the output, and the output may be coupled to the charge integrator.

According to an embodiment of the present invention, voltages applied to the first word line and the second word line may be different pulse voltages. As an embodiment, different pulse voltages may have different pulse amplitudes. In addition, the weight output to the output line may be adjusted by controlling the pulse amplitudes of different pulse voltages. As another embodiment, different pulse voltages may have different pulse widths. In addition, the weight output to the output line may be adjusted by controlling the pulse widths of different pulse voltages.

According to an embodiment of the present invention, the amount of charge flowing for a predetermined time determined by the pulse width of the current determined by the channel conductance (or transconductance) of the weight cell is used as an output value. By way of example, the pulses applied to the word lines of the weight cells are voltage pulses of which the pulse amplitude and pulse width can be arbitrarily specified. As an embodiment, the pulse amplitude may be applied in a range capable of multi-leveling the transconductance of the transistor. In addition, the pulse width can be increased to the limit where reverse voltage does not occur in the charge integrator device when current flows with a given channel conductance (or transconductance) condition. Therefore, the maximum allowable charge flowing in the weight cell is determined by the product of the channel conductance and the pulse width. Accordingly, this maximum allowable charge corresponds to the weight bit-width of the weight cell.

3 and 4 , a column of weighted cells is selected by a selection transistor, an input voltage corresponding to an input signal is applied to a bit line of the transistor, and each voltage is applied to a word line for a predetermined time for each cell. Apply sequentially.

A selection transistor is disposed between the output line and the output, an arbitrary column is selected by applying a gate voltage to the gate of the selection transistor, and the sum of charges flowing through a weight connected to the column is output.

The amount of charge emitted from each weight cell of the neural network according to the embodiment of the present invention is Q=GΔtV. In this relationship, multiplication of GΔt corresponding to weight and voltage V becomes possible. G is the channel conductance or transconductance of the transistor determined by the gate voltage applied to the word line, and the gate voltage is applied in a range in which the conductance becomes multi-level linearly. In the linear channel conductance, the lowest channel conductance becomes the ground conductance GO. The pulse width Δt determines the basic unit pulse width ΔtO to increase linearly. Accordingly, weight bit-width and bit-resolution can be adjusted based on GO and ΔtO.

As an embodiment, in order to prevent the charge output from an arbitrary weight from flowing backward through the other weight cell in the same column due to the time difference of each pulse width, the difference in conductance of each weight, and the difference in input voltage, the output line and each weight cell A diode can be placed between the transistors of

As an embodiment, in order to randomly adjust the weight of each weight cell, multiplication may be performed by selecting each column by a selection transistor. As another embodiment, each column may be selected in order from the first column to the last column, or any column may be selected in any order. As another embodiment, each column may be selected once whenever sequential multiplication is performed on the weight cell array.

The outputs of each column are connected to a charge integrator that collects the output charges by connecting one output line.

5 is a circuit diagram illustrating a weight cell array of a neural network, word lines, bit lines, and selection transistors connected to the array, and respective inputs and outputs according to an embodiment of the present invention.

Referring to FIG. 5 , a conductance-based sequential matrix multiplication neural network capable of adjusting weights with a transistor according to an embodiment of the present invention includes a first weight cell, a second weight cell, a third weight cell, and a fourth weight cell do. The first weight cell includes a first transistor coupled with a first word line, a first input, and a diode, and a diode coupled with a first output line. The second weight cell includes a second transistor coupled to a second word line, a second input, and a diode, and a diode coupled to the first output line. The third weight cell includes a third transistor coupled to the first word line, the first input, and the diode, and the diode coupled to the second output line. The fourth weight cell includes a second word line, a second input, and a fourth transistor coupled to the diode, and a diode coupled to the second output line. The first output line is connected to the first select transistor, and the second output line is connected to the second select transistor.

According to an embodiment of the present invention, voltages applied to the first word line and the second word line may be different pulse voltages. Different pulse voltages may have different pulse amplitudes or different pulse widths. The weights can be adjusted by controlling the pulse amplitudes or pulse widths of different pulse voltages. In an embodiment, a weight of a weight cell output to the first output line and the second output line may be selectively adjusted by selectively applying a gate voltage to the first selection transistor and the second selection transistor. As another embodiment, the weights of the weight cells output to the first output line and the second output line may be sequentially adjusted by sequentially applying a gate voltage to the first selection transistor and the second selection transistor.

According to an embodiment of the present invention, a selection transistor ST is disposed between the output line and the charge integrator. As an embodiment, a column of weight cells of the neural network is selected by applying a gate voltage to the gate of the select transistor.

6 and 7 are circuit diagrams for explaining a sequential matrix multiplication operation of a neural network according to an embodiment of the present invention.

6 shows, for a first column of a neural network according to an embodiment of the present invention, applying a voltage to the gate of the first selection transistor and applying a voltage to the first column, respectively, and pulse voltages having arbitrary pulse amplitudes and pulse widths, respectively; It is a circuit diagram applied to the gates of weight cells.

7 shows that for the last column of a neural network according to an embodiment of the present invention, a voltage equal to the gate voltage of the first selection transistor is applied to the gate of the last selection transistor, and each and arbitrary pulse amplitudes and pulse widths are applied to the last column. It is a circuit diagram for applying a pulse voltage to the gates of each weight cell.

5, 6, and 7, in the neural network according to an embodiment of the present invention, weight cells are configured as an array, the weight cells are manufactured as a network layer, and then each column of the weight cell array is configured. A recurrent or iteration method is applied, which operates sequentially and uses the output value as input information for the next hidden layer.

6 and 7, the time for applying the gate voltage to each weight cell in a specific column of the neural network according to an embodiment of the present invention is adjusted by the width of the gate pulse applied to the word line connected to each weight cell in each column. . As an embodiment, matrix multiplication may be sequentially performed for each column by applying an arbitrary voltage to the word line for each column, and weight information and input information for each hidden layer may be stored in a storage medium external to the neural network. Weight information and input information for each layer are stored in an external storage medium and used for cyclic computing during inference.

Referring to FIGS. 6 and 7 , an embodiment in which the first column and the last column are sequentially selected among i columns can be seen, but the present invention is not limited thereto, and matrix multiplication can be performed by selecting several columns only once without ranking. .

According to the embodiments of the present invention as described above, the conductance-based sequential matrix multiplication neural network capable of adjusting the weights with the transistor according to the embodiment of the present invention can adjust the weights flexibly and reduce the circuit load, A matrix multiplication unit chip size can also be minimized.

As described above, the present invention has been described with specific matters such as specific components and limited embodiments and drawings, but these are only provided to help a more general understanding of the present invention, and the present invention is not limited to the above embodiments. , various modifications and variations are possible from these descriptions by those of ordinary skill in the art to which the present invention pertains.

Therefore, the spirit of the present invention should not be limited to the described embodiments, and not only the claims described below, but also all those with equivalent or equivalent modifications to the claims will be said to belong to the scope of the spirit of the present invention. .

10: input neuron 20: output neuron
30: weight cell

Claims (20)

a transistor having a word line connected to a gate, an input line connected to any one of a drain and a source, and a diode connected to the other one of the drain and the source; and
The output line is connected to the cathode and includes a diode to which the transistor and the anode are connected,
The output line is a transistor connected to any one of a drain and a source of a selection transistor, and a conductance-based neural network whose weight can be adjusted. The method of claim 1,
A conductance-based neural network in which the voltage applied to the word line is a pulse voltage and the weight of the transistor can be adjusted. 3. The method of claim 2,
A conductance-based neural network capable of adjusting a weight by a transistor that adjusts the weight by controlling the pulse amplitude of the pulse voltage. 3. The method of claim 2,
A conductance-based neural network capable of adjusting a weight by a transistor that adjusts the weight by controlling the pulse width of the pulse voltage. The method of claim 1,
A conductance-based neural network in which the word line and the output line are configured to be weighted by transistors positioned to be orthogonal to each other. The method of claim 1,
The input line is connected to the input, and the selection transistor is a transistor connected to the output, and the weight of the transistor can be adjusted. 7. The method of claim 6,
A conductance-based neural network in which a direct current voltage is applied to the input, and the output is a transistor connected to a charge integrator, and weight can be adjusted. a first transistor having a first word line connected to a gate, a first input connected to any one of a drain and a source, and a first diode connected to the other one of the drain and the source, the first transistor having an anode and an anode a first weight cell coupled and including the first diode having an output line coupled to a cathode; and
A second transistor having a second word line connected to a gate, a second input connected to one of a drain and a source of a second transistor, and a second diode connected to the other one of the drain and the source of the second transistor , a second weight cell comprising the second diode, wherein the second transistor is connected to the anode and the output line is connected to the cathode;
The output line is a transistor connected to any one of a drain and a source of the first selection transistor, and a weight of a conductance-based neural network can be adjusted. 9. The method of claim 8,
Voltages applied to the first word line and the second word line are pulse voltages different from each other, and a weight of a transistor may be used to adjust a weight. 10. The method of claim 9,
A conductance-based neural network in which the different pulse voltages are weighted by transistors having different pulse amplitudes. 10. The method of claim 9,
A conductance-based neural network capable of adjusting a weight by a transistor that adjusts the weight output to the output line by controlling the pulse amplitudes of the different pulse voltages. 10. The method of claim 9,
A conductance-based neural network in which the different pulse voltages are weighted by transistors having different pulse widths. 10. The method of claim 9,
A conductance-based neural network capable of adjusting a weight by a transistor that adjusts the weight output to the output line by controlling the pulse widths of the different pulse voltages. 9. The method of claim 8,
The first word line and the second word line are positioned parallel to each other, and the first word line, the second word line, and the output line are positioned orthogonally to each other. a first transistor having a first word line connected to a gate, a first input connected to any one of a drain and a source, and a diode connected to the other one of a drain and a source, the first transistor being connected to an anode, a first weight cell comprising the diode having one output line coupled to a cathode;
a second transistor having a second word line connected to a gate, a second input connected to any one of a drain and a source of a second transistor, and a diode connected to a diode and the other one of the drain and the source of the second transistor; a second weight cell comprising the diode having a second transistor coupled to the anode and a first output line coupled to the cathode;
a third transistor having a first word line connected to a gate, a first input connected to any one of a drain and a source of a third transistor, and a diode connected to a diode and the other one of the drain and the source of the third transistor; a third weight cell comprising the diode having a third transistor coupled to the anode and a second output line coupled to the cathode; and
a fourth transistor having a second word line connected to a gate, a second input connected to any one of a drain and a source of a fourth transistor, and a diode connected to a diode and the other one of the drain and the source of the fourth transistor; a fourth weight cell comprising the diode having a fourth transistor coupled to the anode and a second output line coupled to the cathode;
The first output line is connected to any one of a drain and a source of a first selection transistor, and the second output line is a transistor connected to any one of a drain and a source of the second selection transistor. A conductance-based transistor whose weight can be adjusted. neural network. 16. The method of claim 15,
Voltages applied to the first word line and the second word line are pulse voltages different from each other, and a weight of a transistor may be used to adjust a weight. 17. The method of claim 16,
A conductance-based neural network in which the different pulse voltages are weighted by transistors having different pulse amplitudes or different pulse widths. 17. The method of claim 16,
A conductance-based neural network capable of adjusting a weight by a transistor that adjusts the weight by controlling the pulse amplitude or pulse width of the different pulse voltages. 16. The method of claim 15,
A transistor that selectively adjusts weights of weight cells output to the first output line and the second output line by selectively applying a gate voltage to the first selection transistor and the second selection transistor. A conductance capable of controlling a weight. based neural networks. 16. The method of claim 15,
A transistor that sequentially adjusts weights of weight cells output to the first output line and the second output line by sequentially applying a gate voltage to the first selection transistor and the second selection transistor. based neural networks.

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