CN114121089B - Memristor array-based data processing method and device - Google Patents
Memristor array-based data processing method and device Download PDFInfo
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Abstract
A data processing method and a data processing device based on a memristor array are used for a linear operation algorithm. The data processing method comprises the following steps: acquiring algorithm parameters; determining a mapping conductance value of a corresponding memristor in the memristor array by algorithm parameters; determining a mapped conductance interval based on the mapped conductance value; writing the mapping conductance value into a corresponding memristor in the memristor array, and enabling the corresponding memristor to fall into the mapping conductance interval to obtain the mapped memristor array. The data processing method can solve the problem that the quantization mapping scheme introduces quantization errors and is not suitable for a linear operation algorithm, so that the accuracy of memristor conductance mapping can be improved, and the operation accuracy of a memristor memory-calculation integrated system can be improved.
Description
Technical Field
The embodiment of the disclosure relates to a data processing method and a data processing device based on a memristor array.
Background
Memristors are novel micro-nano electronic devices for information storage and processing, and the resistance states of the memristors can be adjusted through external voltage excitation. The memristor-based memory-computing integrated architecture breaks through the bottleneck of the von neumann architecture of a classical computing system, can eliminate the time and energy cost required by data handling, brings about explosive growth of hardware computing power and energy efficiency, and is one of the next generation hardware chip technologies with the highest potential. Meanwhile, the memristor has the advantages of low operation voltage, small energy consumption, small area, high speed and the like. Thus, memristor array-based computational integration systems are a recent research hotspot.
Disclosure of Invention
At least one embodiment of the present disclosure provides a data processing method based on a memristor array, for a linear operation algorithm, the data processing method including: acquiring algorithm parameters; determining a mapping conductance value of a corresponding memristor in the memristor array by algorithm parameters; determining a mapped conductance interval based on the mapped conductance value; writing the mapping conductance value into a corresponding memristor in the memristor array, and enabling the corresponding memristor to fall into the mapping conductance interval to obtain the mapped memristor array.
For example, in a data processing method provided in at least one embodiment of the present disclosure, making a corresponding memristor fall within a mapped conductance interval includes: after the mapping conductance value is written into the corresponding memristor in the memristor array, reading the conductance value of the corresponding memristor; determining whether the conductance value of the corresponding memristor falls within the mapped conductance interval, and determining that the write operation is successful in the case that the conductance value of the corresponding memristor falls within the mapped conductance interval, or, in the case that the conductance value of the corresponding memristor does not fall within the mapped conductance interval, writing the mapped conductance value into the corresponding memristor in the memristor array again and causing the corresponding memristor to fall within the mapped conductance interval.
For example, in a data processing method provided by at least one embodiment of the present disclosure, an algorithm parameter includes a plurality of parameters mapped into a plurality of memristors, respectively, and determining a mapped conductance interval based on a mapped conductance value includes: for a plurality of parameters, a corresponding plurality of mapped conductance intervals are independently determined.
For example, in a data processing method provided by at least one embodiment of the present disclosure, at least two of a plurality of mapped conductance intervals are allowed to overlap each other.
For example, in a data processing method provided in at least one embodiment of the present disclosure, before writing the mapped conductance value into a corresponding memristor in the memristor array and causing the corresponding memristor to fall within the mapped conductance interval, the data processing method further includes: and carrying out an initial activation operation on the memristor array.
For example, in the data processing method provided in at least one embodiment of the present disclosure, after obtaining the mapped memristor array, the data processing method further includes: and performing read operation on the mapped memristor array.
For example, in the data processing method provided in at least one embodiment of the present disclosure, a first analog-to-digital converter is used to write a mapped conductance value into a corresponding memristor in a memristor array, a second analog-to-digital converter is used to perform an initialization activation operation on the memristor array and a read operation on the mapped memristor array, and the accuracy of the first analog-to-digital converter is higher than that of the second analog-to-digital converter.
At least one embodiment of the present disclosure provides a data processing apparatus for a linear operation algorithm, the data processing apparatus including: a memristor array including a plurality of memristors; the controller is configured to acquire algorithm parameters, determine mapping conductance values of the corresponding memristors in the memristor array according to the algorithm parameters, and determine mapping conductance intervals based on the mapping conductance values; and the operation circuit is configured to write the mapping conductance value into a corresponding memristor in the memristor array, and enable the corresponding memristor to fall into the mapping conductance interval to obtain the mapped memristor array.
For example, in a data processing apparatus provided in at least one embodiment of the present disclosure, the operation circuit is further configured to: after the mapping conductance value is written into the corresponding memristor in the memristor array, reading the conductance value of the corresponding memristor; the controller is further configured to: determining whether the conductance value of the corresponding memristor falls within the mapped conductance interval, and determining that the writing operation is successful in the case that the conductance value of the corresponding memristor falls within the mapped conductance interval, or writing the mapped conductance value into the corresponding memristor in the memristor array again in the case that the conductance value of the corresponding memristor does not fall within the mapped conductance interval, and enabling the corresponding memristor to fall within the mapped conductance interval.
For example, in a data processing apparatus provided by at least one embodiment of the present disclosure, the algorithm parameters include a plurality of parameters mapped into a plurality of memristors, respectively, the controller is further configured to: for a plurality of parameters, a corresponding plurality of mapped conductance intervals are independently determined.
For example, in a data processing apparatus provided in at least one embodiment of the present disclosure, the controller is further configured to allow at least two of the plurality of mapped conductance intervals to overlap each other.
For example, in a data processing apparatus provided in at least one embodiment of the present disclosure, an operation circuit includes: the first analog-to-digital converter is configured to map algorithm parameters into conductance values in the memristor array to obtain a mapped memristor array; and a second analog-to-digital converter configured to perform an initializing activation operation on the memristor array and/or a reading operation on the mapped memristor array, wherein the accuracy of the first analog-to-digital converter is higher than that of the second analog-to-digital converter.
For example, in a data processing apparatus provided in at least one embodiment of the present disclosure, the memristor has a 1T1R structure or a 2T2R structure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.
FIG. 1 shows a schematic diagram of a memristor array;
FIG. 2 shows a schematic diagram of a memristor cell with a 1T1R structure;
FIG. 3 shows a schematic diagram of a memristor cell with a 2T2R structure;
FIG. 4 illustrates an exemplary schematic diagram of a quantized mapping scheme;
FIG. 5 illustrates a schematic flow diagram of a data processing method based on a memristor array provided in accordance with at least one embodiment of the present disclosure;
FIG. 6 illustrates an exemplary schematic diagram of a data processing method provided by at least one embodiment of the present disclosure;
FIG. 7 illustrates a schematic flow diagram of another memristor array-based data processing method provided by at least one embodiment of the present disclosure;
FIG. 8 illustrates a schematic block diagram of a data processing apparatus provided in accordance with at least one embodiment of the present disclosure;
fig. 9 is a schematic diagram of a data processing apparatus according to at least one embodiment of the present disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
Memristors (e.g., resistive random access memories, phase change memories, conductive bridge memories, etc.) are nonvolatile devices whose conductance state can be adjusted by application of an external stimulus. Memristors, which are two-terminal devices, have the characteristics of adjustable resistance and non-volatility, and are therefore widely used in memory and computing. According to kirchhoff's current law and ohm's law, an array of memristors can perform multiply-accumulate calculations in parallel, and both storage and calculation occur in each device of the array. Based on the computing architecture, a computationally-intensive computation that does not require a large amount of data movement can be implemented.
FIG. 1 shows a schematic diagram of a memristor array structure. As shown in FIG. 1, the memristor array is composed of a plurality of memristor units, wherein the plurality of memristor units form an array of M rows and N columns, and M and N are positive integers. Each memristor cell includes a switching element and one or more memristors. In fig. 1, WL <1>, WL <2> … … WL < M > represent the word lines of the first and second rows … …, respectively, and the control electrode (e.g., gate of transistor) of the switching element in the memristor cell circuit of each row is connected to the word line corresponding to that row; BL <1>, BL <2> … … BL < N > represent the bit lines of the N-th column of the first column and the second column … … respectively, and the memristors in the memristor unit circuits of each column are connected with the bit lines corresponding to the column; SL <1>, SL <2> … … SL < M > represent the source lines of the Mth row of the first row and the second row … …, respectively, and the sources of the transistors in the memristor cell circuits of each row are connected to the source line corresponding to that row.
The memristor cells in the memristor array of fig. 1 may be, for example, a 1T1R structure or a 2T2R structure, where the memristor cells of the 1T1R structure include one switching transistor and one memristor, and the memristor cells of the 2T2R structure include two switching transistors and two memristors. The present disclosure is not limited with respect to the type, structure, etc. of memristor devices.
It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors (e.g., MOS field effect transistors) or other switching devices with the same characteristics. The source and drain of the transistor used herein may be symmetrical in structure, so that the source and drain may be indistinguishable in structure. Embodiments of the present disclosure are not limited in the type of transistor employed.
FIG. 2 shows a schematic diagram of a memristor cell with a 1T1R structure. As shown in fig. 2, the memristor cell of the 1T1R structure includes one transistor M1 and one memristor R1.
For example, when the transistor M1 adopts an N-type transistor, the gate thereof is connected to the word line terminal WL, for example, the transistor M1 is turned on when the word line terminal WL inputs a high level; the first pole of the transistor M1 may be a source and configured to be connected to the source terminal SL, e.g., the transistor M1 may receive a reset voltage through the source terminal SL; the second pole of the transistor M1 may be a drain and configured to be connected to a second pole (e.g., a negative pole) of the memristor R1, the first pole (e.g., a positive pole) of the memristor R1 being connected to the bit line terminal BL, the memristor R1 receiving a set voltage through the bit line terminal BL, for example. For example, when the transistor M1 adopts a P-type transistor, the gate thereof is connected to the word line terminal WL, for example, the transistor M1 is turned on when the word line terminal WL inputs a low level; the first pole of the transistor M1 may be a drain and configured to be connected to the source terminal SL, e.g., the transistor M1 may receive a reset voltage through the source terminal SL; the second pole of the transistor M1 may be a source and configured to be connected to a second pole (e.g., a negative pole) of the memristor R1, the first pole (e.g., a positive pole) of the memristor R1 being connected to the bit line terminal BL, the memristor R1 receiving a set voltage through the bit line terminal BL, for example. It should be noted that the resistive random access memory structure may also be implemented as other structures, for example, a structure in which the second pole of the memristor R1 is connected to the source terminal SL, which is not limited by the embodiments of the present disclosure.
The following embodiments will take the N-type transistor as an example of the transistor M1.
The word line terminal WL functions to apply a corresponding voltage to the gate of the transistor M1, thereby controlling the transistor M1 to be turned on or off. In the operation of the memristor R1, for example, the set operation or the reset operation, the transistor M1 needs to be turned on first, that is, an on voltage needs to be applied to the gate of the transistor M1 through the word line end WL. After transistor M1 is turned on, the resistance state of memristor R1 may be changed, for example, by applying voltages to memristor R1 at source terminal SL and bit terminal BL. For example, a set voltage may be applied through the bit line terminal BL to place the memristor R1 in a low resistance state; for another example, a reset voltage may be applied through the source terminal SL to place the memristor R1 in a high resistance state. For example, the resistance value in the high resistance state is 100 times or more, for example 1000 times or more, that in the low resistance state.
It should be noted that, in the embodiment of the present disclosure, for example, by applying voltages to the word line terminal WL and the bit line terminal BL at the same time, the resistance value of the memristor R1 may be made smaller and smaller, that is, the memristor R1 changes from the high-resistance state to the low-resistance state, and the operation of changing the memristor R1 from the high-resistance state to the low-resistance state is referred to as a set operation; by applying voltages to the word line terminal WL and the source line terminal SL at the same time, the resistance value of the memristor R1 is increased, that is, the memristor R1 changes from a low resistance state to a high resistance state, and the operation of changing the memristor R1 from the low resistance state to the high resistance state is referred to as a reset operation. For example, the memristor R1 has a threshold voltage that does not change the resistance value (or conductance value) of the memristor R1 when the input voltage magnitude is less than the threshold voltage of the memristor R1. In this case, calculation may be performed using the resistance value (or conductance value) of the memristor R1 by inputting a voltage smaller than the threshold voltage; the resistance value (or conductance value) of memristor R1 may be changed by inputting a voltage greater than the threshold voltage.
FIG. 3 shows a schematic diagram of a memristor cell with a 2T2R structure. As shown in fig. 3, the memristor cell of the 2T2R structure includes two transistors M1 and M2 and two memristors R1 and R2. The following description will take an example in which the transistors M1 and M2 are both N-type transistors.
The gate of the transistor M1 is connected to the word line terminal WL1, for example, the transistor M1 is turned on when the word line terminal WL1 of M1 inputs a high level, the gate of the transistor M2 is connected to the word line terminal WL2, for example, the transistor M2 is turned on when the word line terminal WL2 of M2 inputs a high level; the first pole of the transistor M1 may be a source and configured to be connected to the source line terminal SL, e.g. the transistor M1 may receive a reset voltage through the source line terminal SL, the first pole of the transistor M2 may be a source and configured to be connected to the source line terminal SL, e.g. the transistor M2 may receive a reset voltage through the source line terminal SL, the first pole of the transistor M1 is connected to the first pole of the transistor M2 and together to the source line terminal SL. The second pole of the transistor M1 may be a drain and configured to be connected to a second pole (e.g., a negative pole) of the memristor R1, the first pole (e.g., a positive pole) of the memristor R1 being connected to the bit line terminal BL1, e.g., the memristor R1 may receive a set voltage through the bit line terminal BL 1; the second pole of transistor M2 may be a drain and configured to be connected to a second pole (e.g., a negative pole) of memristor R2, a first pole (e.g., a positive pole) of memristor R2 being connected to bit line terminal BL2, for example, memristor R2 may receive a set voltage through bit line terminal BL 2.
It should be noted that, the transistors M1 and M2 in the memristor unit with the 2T2R structure may also be P-type transistors, which is not described herein again.
Many efforts have demonstrated the superiority of neural network algorithms such as single-layer perceptrons, multi-layer perceptrons, convolutional neural networks, etc. to implementation on memristor array-based memory-computing integrated systems. These works commonly employ quantization mapping (Quantized Mapping, QM) to map algorithm parameters into memristor arrays.
Fig. 4 shows an exemplary schematic diagram of a quantization mapping scheme.
As shown in fig. 4, the left side of the figure is an algorithmic model of a neural network whose algorithmic parameters are first quantized before being mapped to a memristor array. Currently, algorithm parameters are quantized rather than directly mapped to memristors, because: memristors are beginning to be used as memories, representing a plurality of bits in a plurality of different electrical conduction states, and strict requirement is made that the plurality of electrical conduction states are equidistant from each other (so that the distance can be guaranteed to be maximized at the same time) so as to avoid overlapping between the electrical conduction states, which leads to destruction of the information stored in the memristors. The algorithm parameters respectively fall into a plurality of quantization intervals, the solid line represents the actual algorithm parameters falling into the plurality of quantization intervals, the dotted line represents the range boundary of the quantization intervals, and the plurality of quantization intervals are connected end to end and do not overlap each other. For example, one algorithm parameter falls within the first quantization interval, and the intermediate value of the first quantization interval (instead of the actual value of the algorithm parameter) is mapped into the memristor array on the right as the new quantized parameter. The memristor array comprises a plurality of memristors arranged in an array, and a dotted arrow in the figure indicates that a certain quantized new parameter is mapped to a corresponding memristor, and the quantized new parameter is stored in the memristor as a conductance value of the corresponding memristor.
For example, N algorithm parameters of the neural network (algorithm parameters are w i Represented) is in the range of 0 to 16, i.e. w i ∈[0,16]I=1, 2,3, …, N, i is a positive integer. Setting the number of quantization intervals to be 16, and quantizing the N algorithm parameters to 16 intervals, wherein the 16 intervals are respectively [0,1 ], [1,2 ], [2, 3), … …, [14, 15), and [15,16]The median value of each quantization interval is 0.5, 1.5, 2.5, … …, 14, respectivelyAnd 5, 15.5. If an algorithm parameter is 2.9, the algorithm parameter will fall within the quantization interval of [2,3 ], but in the quantization mapping scheme described above, the algorithm parameter will be mapped with the intermediate value 2.5 of interval [2,3 ] as the new quantized parameter. The rest of the algorithm parameters are mapped sequentially according to the same method.
The number of sections is not limited to a fixed number, and may be 4, 6, 32, or the like, and the number of sections may be determined according to the actual situation, and is not limited. The specific range of each quantization interval is determined according to the range of all algorithm parameters in the neural network and the preset number of quantization intervals. In the QM scheme, the respective quantization intervals do not overlap with each other.
The QM scheme is widely applied to a neural network algorithm, and on one hand, because the memristor still has larger read noise and write bias, the distinguishing property of adjacent conductivity values is ensured by virtue of quantization operation; on the other hand, since the neural network algorithm is a nonlinear algorithm that focuses on the final classification accuracy, and does not require that every algorithm parameter have extremely high accuracy, there is no need to obtain a memristor conductance value (i.e., the parameter value of the neural network algorithm) with high accuracy.
However, QM schemes are not suitable for linear operation algorithms (e.g., signal processing algorithms, including, for example, discrete fourier transform algorithms, discrete cosine transform algorithms, finite impulse response filter algorithms, infinite impulse response filter algorithms, etc.). On the one hand, the linear operation algorithm has high requirements on the precision of the calculation result, and on the other hand, the number of parameters of some algorithms (such as a signal processing algorithm) in the linear operation algorithm is huge and the values are different, the number of required conductance values is extremely large (for example, 1463 different conductance values are required for 1024-point discrete Fourier transform for the signal processing algorithm), and if the parameters of the algorithm are forcedly quantized, serious calculation precision loss is caused.
At least one embodiment of the present disclosure provides a data processing method for a linear operation algorithm, the data processing method including: acquiring algorithm parameters; determining a mapping conductance value of a corresponding memristor in the memristor array by algorithm parameters; determining a mapped conductance interval based on the mapped conductance value; writing the mapping conductance value into a corresponding memristor in the memristor array, and enabling the corresponding memristor to fall into the mapping conductance interval to obtain the mapped memristor array.
The data processing method provided by the embodiment of the disclosure can solve the problem that the QM scheme introduces quantization errors (the concept of the quantization errors can be seen in fig. 6) and is not suitable for a linear operation algorithm, so that the accuracy of memristor conductance mapping can be improved, and the operation accuracy of a memristor memory-calculation integrated system can be improved.
At least one embodiment of the present disclosure further provides a data processing apparatus corresponding to the above data processing method.
Embodiments of the present disclosure will be described in detail below with reference to the attached drawings, but the present disclosure is not limited to these specific embodiments.
FIG. 5 illustrates a schematic flow diagram of a data processing method based on a memristor array provided in at least one embodiment of the present disclosure. For example, the data processing method is used for a linear operation algorithm, such as a signal processing algorithm.
As shown in fig. 5, the data processing method includes the following steps S501 to S504.
Step S501: and acquiring algorithm parameters.
For example, the algorithm parameters include a plurality of parameters that are mapped into a plurality of memristors, respectively.
Step S502: the mapped conductance values of the corresponding memristors in the memristor array are determined by the algorithm parameters.
For example, in this embodiment, the algorithm parameter is not quantized, so the mapped conductance value of the memristor corresponding to the algorithm parameter represents the actual value of the algorithm parameter.
Step S503: a mapped conductance interval is determined based on the mapped conductance value.
For example, in some embodiments of the present disclosure, one example of step S503 may include: for a plurality of parameters, a corresponding plurality of mapped conductance intervals are independently determined.
For example, if the positive and negative 0.1 μs are preset as acceptable mapping deviation and the mapping conductance value of one algorithm parameter is 5 μs, the mapping conductance interval corresponding to the algorithm parameter is 4.9 μs to 5.1 μs. For example, the mapped conductance value of another algorithm parameter is 4.9 μS, and the mapped conductance interval corresponding to the algorithm parameter is 4.8 μS to 5.0 μS.
For example, at least two of the plurality of mapped conductance intervals are allowed to overlap each other.
For example, the map conductance interval 4.9. Mu.S to 5.1. Mu.S and the map conductance interval 4.8. Mu.S to 5.0. Mu.S overlap each other.
Step S504: writing the mapping conductance value into a corresponding memristor in the memristor array, and enabling the corresponding memristor to fall into the mapping conductance interval to obtain the mapped memristor array.
For example, in some embodiments of the present disclosure, causing the corresponding memristor to fall within the mapped conductance interval in step S504 may include: after the mapping conductance value is written into the corresponding memristor in the memristor array, reading the conductance value of the corresponding memristor; determining whether the conductance value of the corresponding memristor falls within the mapped conductance interval, and determining that the write operation is successful in the case that the conductance value of the corresponding memristor falls within the mapped conductance interval, or, in the case that the conductance value of the corresponding memristor does not fall within the mapped conductance interval, writing the mapped conductance value into the corresponding memristor in the memristor array again and causing the corresponding memristor to fall within the mapped conductance interval.
Due to the existence of memristor write bias, a certain bias exists between the mapped conductance value and the actual conductance value of the corresponding memristor, which are determined by algorithm parameters. For example, the mapped conductance value is 5. Mu.S and the mapped conductance interval is 4.9. Mu.S to 5.1. Mu.S. After writing the mapped conductance values into the corresponding memristors in the memristor array, reading the conductance values of the corresponding memristors. If the read conductance value is within the mapped conductance interval of 4.9 μs to 5.1 μs, then the write operation is considered successful, and if the read conductance value is not within the mapped conductance interval of 4.9 μs to 5.1 μs, then the mapped conductance value is rewritten into the corresponding memristor in the memristor array until the read conductance value is within the mapped conductance interval.
It should be noted that if the map conductance interval is set narrower, the mapping result is more accurate, but this requires more mapping, takes more time, consumes more energy, and requires a higher-precision analog-to-digital converter. In practice, the mapping error will be set to a moderate value (e.g., plus or minus 0.5 μs) so that the mapped conductance interval is in the proper range.
For example, in some embodiments of the present disclosure, before writing the mapped conductance values into the corresponding memristors in the memristor array and causing the corresponding memristors to fall within the mapped conductance interval, the data processing method further includes: an activation operation (Forming) is initiated on the memristor array.
The initialized activation operation refers to: the memristor just prepared is in an initial resistance state, generally a high resistance state, and has no resistance change characteristic, so that a relatively large voltage pulse needs to be applied to two ends of the memristor in order to enable the memristor to work normally, and the process is called an activation process. After the activation operation, the memristor has normal resistance change characteristics.
For example, in some embodiments of the present disclosure, after obtaining the mapped memristor array, the data processing method further includes: and performing read operation on the mapped memristor array.
For example, in some embodiments of the present disclosure, a mapped conductance value is written into a corresponding memristor in a memristor array using a first analog-to-digital converter, an initialized activation operation is performed on the memristor array using a second analog-to-digital converter, and a read operation is performed on the mapped memristor array, where, for example, the accuracy of the first analog-to-digital converter is higher than the accuracy of the second analog-to-digital converter.
In the read operation of the memristor array, a very high-Precision analog-to-digital converter (ADC) is not required due to the existence of read noise, and only a Low-Precision ADC (LP-ADC) is required to save power consumption and increase the operation speed. In writing the mapped conductance values into the memristor array, a High-Precision analog-to-digital converter (HP-ADC) needs to be employed (i.e., precision is higher than LP-ADC) in order to achieve higher Precision. In embodiments of the present disclosure, there is no limitation on the specific implementation of the analog-to-digital converter (ADC).
In this embodiment, during the activation operation of initializing the memristor array and the read operation of the mapped memristor array, the second analog-to-digital converter is invoked, and during writing of the mapped conductance value into the corresponding memristor in the memristor array, the first analog-to-digital converter is invoked, where the accuracy of the first analog-to-digital converter is higher than that of the second analog-to-digital converter.
The accuracy of the analog-to-digital converter is divided by the full scale input of the converter by 2 N N is the ideal number of bits for the converter. For example, assume a 12-bit analog-to-digital converter that can represent any signal applied to the input of the converter at 4096 numbers at the output. These representation information do have a limited amount of error. Thus, if the input full scale (VFS) of a 12-bit analog-to-digital converter is 10VP-P, the accuracy is + -1.22 mV.
In practice, the required analog-to-digital converter accuracy varies according to the kind of algorithm, or the application scenario, or the device characteristics. For example, for a Discrete Fourier Transform (DFT) algorithm, in writing mapped conductance values into a memristor array, 10bit and higher precision analog-to-digital converters may be selected, and in reading a mapped memristor array, 6bit or lower precision analog-to-digital converters may be selected.
Since in at least one embodiment of the present disclosure, the operation matrix of the algorithm is often given and fixed, the operation of mapping the conductance values into the memristor array need only be performed once before the algorithm operates, and no overwriting of the conductance values in the memristor array is required during the operation. Therefore, in the data processing method provided by the embodiment of the disclosure, it is necessary and desirable to invoke the energy and time consumption of the high-precision analog-to-digital converter in exchange for more accurate operation results.
An exemplary schematic of the data processing method depicted in fig. 5 is shown in fig. 6.
The difference in mapping results obtained using the quantized mapping scheme and the data processing method of the present disclosure can be seen from fig. 6. In the left box of fig. 6 is a mapping result using a quantization mapping scheme, and in the right box of fig. 6 is a mapping result using the data processing method of the embodiment of the present disclosure. And the mapping conductance values of the corresponding memristors in the memristor array, which are determined by the algorithm parameters, are T1-T5. In the quantization mapping scheme, the mapped conductance intervals L1 to L5 do not overlap each other (the mapped conductance intervals are shown by solid lines in the left frame), whereas in the data processing method of at least one embodiment of the present disclosure, for example, the mapped conductance intervals L3 and L4 overlap, and the mapped conductance intervals L4 and L5 overlap (the mapped conductance intervals are shown by solid lines in the right frame). If the quantization mapping scheme is adopted, the actually mapped conductance values of the mapped conductance values T1 to T5 are respectively intermediate values (as indicated by the dashed lines in the left-hand frame) of the mapped conductance intervals L1 to L5, and if the data processing method of the present disclosure is adopted, the actually mapped conductance values of the mapped conductance values T1 to T5 are indicated by the dashed lines in the right-hand frame. Since the mapped conductance values are directly mapped to the conductance values of the memristor array without performing the step of parameter quantization in the case of the data processing method of at least one embodiment of the present disclosure, quantization errors (as indicated by the arrow in the left-hand box) under the quantization mapping scheme, which refer to the difference between the mapped conductance values and the actually mapped conductance values, are not introduced.
The data processing method provided by at least one embodiment of the present disclosure allows mapping conductance intervals to overlap each other, so as to overcome quantization errors introduced by a quantization mapping scheme, so that algorithm parameters with small phase differences can still be distinguished after mapping, and therefore high-precision conductance mapping can be realized.
At least one embodiment of the present disclosure provides a memristor array-based data processing method including three parts, namely, a first part is an activation operation, a second part is a mapping operation, and a third part is a read operation, and a schematic flowchart of the data processing method is shown in fig. 7.
As shown in fig. 7, first, the data processing method starts to be executed.
Next, as shown in FIG. 7, an initial activation operation is performed on the memristor array.
For example, the LP-ADC is invoked for an activation operation.
Next, as shown in fig. 7, a mapping operation is performed to obtain a mapped memristor array.
For example, performing the mapping operation includes the steps of: after the algorithm parameters are preliminarily mapped into the corresponding memristors in the memristor array, invoking the HP-ADC to read the conductance values of the corresponding memristors, if the read conductance values fall into the mapping conductance interval, considering that the mapping operation is successful, and if the read conductance values do not fall into the mapping conductance interval, remapping the algorithm parameters into the corresponding memristors in the memristor array until the read conductance values are located in the mapping conductance interval.
Next, as shown in fig. 7, a read operation is performed on the mapped memristor array.
For example, the LP-ADC is called for a read operation.
For example, the dashed arrow in FIG. 7 leading from the read operation to the map operation indicates that after multiple read operations have been performed, it may be necessary to adjust the conductance values of the memristor array, and then return to the map operation step to remap the memristor array.
Finally, as shown in fig. 7, the data processing method ends.
For the data processing method shown in fig. 7, memristors of the memristor array may be implemented using appropriate types of devices (e.g., phase change memory, magnetic random access memory, etc.), appropriate types of memristor array structures (1T 1R structures, 2T2R structures, etc.), appropriate types of pulse operation schemes (pulse number coding scheme, pulse amplitude coding scheme, etc.).
Fig. 8 illustrates a schematic block diagram of a data processing apparatus 800 for linear operation, which may be used to perform the data processing method illustrated in fig. 5, in accordance with at least one embodiment of the present disclosure.
As shown in fig. 8, the data processing apparatus 800 includes a memristor array 801, a controller 802, and an operating circuit 803, the operating circuit 803 including a first analog-to-digital converter 804 and a second analog-to-digital converter 805.
For example, the memristor array 801 includes a plurality of memristors.
For example, in some embodiments of the present disclosure, the memristor structure is a 1T1R structure as shown in fig. 2 or a 2T2R structure as shown in fig. 3.
The controller 802 is configured to obtain an algorithm parameter, determine a mapped conductance value of a corresponding memristor in the memristor array 801 from the algorithm parameter, and determine a mapped conductance interval based on the mapped conductance value.
The operation circuit 803 is configured to write the mapped conductance values into the corresponding memristors in the memristor array 801 and cause the corresponding memristors to fall within the mapped conductance interval, resulting in a mapped memristor array 801.
The first analog-to-digital converter 804 is configured to map the algorithm parameters to conductance values in the memristor array 801, resulting in a mapped memristor array 801.
The second analog-to-digital converter 805 is configured to perform an initialization activation operation of the memristor array 801 and/or to perform a read operation of the mapped memristor array 801.
For example, the accuracy of the first analog-to-digital converter 804 is higher than the accuracy of the second analog-to-digital converter 805.
For example, in at least one embodiment, the operational circuitry 803 is further configured to read the conductance values of the corresponding memristors in the memristor array 801 after writing the mapped conductance values into the corresponding memristors.
For example, in at least one embodiment, the controller 802 is further configured to determine whether the conductance value of the corresponding memristor falls within the mapped conductance interval, determine that the write operation was successful in the case where the conductance value of the corresponding memristor falls within the mapped conductance interval, or, in the case where the conductance value of the corresponding memristor does not fall within the mapped conductance interval, again write the mapped conductance value into the corresponding memristor in the memristor array 801 and cause the corresponding memristor to fall within the mapped conductance interval.
For example, in at least one embodiment, the algorithm parameters include a plurality of parameters that are mapped into a plurality of memristors, respectively, and the controller 802 is further configured to independently determine a corresponding plurality of mapped conductance intervals for the plurality of parameters.
For example, in at least one embodiment, the controller 802 is further configured to allow at least two of the plurality of mapped conductance intervals to overlap each other.
For example, data processing apparatus 800 may be implemented in hardware, software, firmware, and any feasible combination thereof, which is not limiting in this disclosure.
The technical effects of the data processing apparatus 800 are the same as those of the data processing method shown in fig. 5, and can be used to improve the operation accuracy of the memristor memory integrated system, which is not described herein again.
Fig. 9 shows a schematic diagram of a data processing apparatus according to at least one embodiment of the present disclosure.
As shown in fig. 9, the data processing apparatus is used to implement a data processing method according to at least one embodiment of the present disclosure. The data processing apparatus includes a memristor array, and peripheral circuitry including a digital-to-analog converter (DAC), a low-precision analog-to-digital converter (LP-ADC), a high-precision analog-to-digital converter (HP-ADC), a transimpedance amplifier (TIA), and a Multiplexer (MUX).
The memristor array includes M rows and N columns of memristors. The memristor array further includes M word lines (WL [1:M ]), M source lines (SL [1:M ]), and N bit lines (BL [1:N ]), wherein the M word lines and the M source lines respectively correspond to M rows, and the N bit lines respectively correspond to N columns. Each word line, each source line and each bit line are respectively connected with corresponding multiplexers, and the multiplexers of M word lines, M source lines and N column lines are respectively controlled by signals WL_sw [1:M ], SL_sw [1:M ] and BL_sw [1:N ]. One input terminal of M multiplexers connected to M word lines is connected to Ground (GND), and the other input terminal is connected to a voltage signal V_WL 1:M. For example, when a voltage signal v_wl [1:M ] is applied to a word line WL [1:M ] through a multiplexer, the memristor corresponding to the word line to which the voltage signal is applied is turned on, and when a voltage signal 0 (at this time, a connection ground line) is applied to a word line WL [1:M ] through a multiplexer, the memristor corresponding to the word line to which the voltage signal 0 is applied is turned off. One input end of the N multiplexers connected with the N bit lines is connected with a Ground (GND), the other input end of the N multiplexers is connected with a DAC, the DAC converts digital signals into analog voltage signals, and the analog voltage signals are applied to the bit lines BL [1:N ] through the multiplexers. The source line voltage V_SL [1:M ] is applied to the source line SL [1:M ] through the multiplexer.
An embodiment of a data processing method according to at least one embodiment of the present disclosure is briefly described below with reference to the data processing apparatus shown in fig. 9, and specific reference may be made to the foregoing description.
A controller (not shown) obtains algorithm parameters, determines mapped conductance values for corresponding memristors in the memristor array from the algorithm parameters, and determines mapped conductance intervals based on the mapped conductance values. Before writing the mapped conductance values to the memristor array, an initialization activation operation is performed on the memristor array with the LP-ADC. And then, writing the mapped conductance value into a corresponding memristor in the memristor array by using the HP-ADC to obtain the mapped memristor array. For example, the gate of the memristor is applied with a voltage via the word line WL [1:M ], and after the memristor is turned on, the memristor can be changed in its conductance state by applying a voltage to the memristor at the source line SL [1:M ] and the bit line BL [1:N ]. After writing the mapped conductance values into the corresponding memristors in the memristor array, reading the conductance values of the corresponding memristors using the HP-ADC, and determining whether the conductance values of the corresponding memristors fall within the mapped conductance interval. For example, by applying voltage signals to the word line end, the bit line end and the source line end of one memristor at the same time, a source line current flowing through the memristor can be obtained, the source line current is converted into a voltage signal through a transimpedance amplifier, the voltage signal is converted into a digital signal through an HP-ADC, a conductance value stored in the memristor can be obtained through the size of the digital signal, and whether mapping is successful or not is determined by comparing the conductance value with a mapping conductance interval.
For the purposes of this disclosure, the following points are also noted:
(1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.
(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.
The foregoing is merely a specific embodiment of the disclosure, but the scope of the disclosure is not limited thereto and should be determined by the scope of the claims.
Claims (13)
1. A data processing method based on a memristor array, for a linear operation algorithm, the data processing method comprising:
acquiring algorithm parameters;
determining a mapping conductance value of a corresponding memristor in the memristor array by the algorithm parameter under the condition that the algorithm parameter does not perform quantization operation;
determining a mapped conductance interval based on the mapped conductance value;
writing the mapped conductance value into a corresponding memristor in the memristor array, and enabling the conductance value of the corresponding memristor to fall into the mapped conductance interval to obtain a mapped memristor array.
2. The data processing method of claim 1, wherein causing the conductance value of the corresponding memristor to fall within the mapped conductance interval comprises:
after writing the mapping conductance value into a corresponding memristor in the memristor array, reading the conductance value of the corresponding memristor;
determining whether the conductance value of the corresponding memristor falls within the mapped conductance interval, and
and determining that a write operation is successful in the case that the conductance value of the corresponding memristor falls within the mapped conductance interval, or, in the case that the conductance value of the corresponding memristor does not fall within the mapped conductance interval, writing the mapped conductance value again into a corresponding memristor in the memristor array and causing the conductance value of the corresponding memristor to fall within the mapped conductance interval.
3. The data processing method of claim 1 or 2, wherein the algorithm parameters include a plurality of parameters mapped into a plurality of memristors, respectively, the mapping conductance interval being determined based on the mapping conductance value, comprising:
for the plurality of parameters, a corresponding plurality of mapped conductance intervals is independently determined.
4. A data processing method according to claim 3, wherein at least two of the plurality of mapped conductance intervals are allowed to overlap each other.
5. The data processing method of claim 1 or 2, wherein prior to writing the mapped conductance value into a corresponding memristor in the memristor array and causing the conductance value of the corresponding memristor to fall within the mapped conductance interval, the data processing method further comprises:
and initializing the memristor array to perform activation operation.
6. The data processing method of claim 1, wherein after obtaining the mapped memristor array, the data processing method further comprises:
and performing a read operation on the mapped memristor array.
7. The data processing method of claim 6, wherein the mapped conductance values are written into corresponding ones of the memristor arrays using a first analog-to-digital converter, the memristor arrays are initialized with an activation operation using a second analog-to-digital converter and the mapped memristor arrays are read,
the accuracy of the first analog-to-digital converter is higher than the accuracy of the second analog-to-digital converter.
8. A data processing apparatus for a linear operation algorithm, comprising:
a memristor array including a plurality of memristors;
the controller is configured to acquire algorithm parameters, determine mapping conductance values of corresponding memristors in the memristor array according to the algorithm parameters under the condition that the algorithm parameters do not perform quantization operation, and determine mapping conductance intervals based on the mapping conductance values; and
and the operation circuit is configured to write the mapping conductance value into a corresponding memristor in the memristor array, and enable the conductance value of the corresponding memristor to fall into the mapping conductance interval to obtain a mapped memristor array.
9. The data processing apparatus of claim 8, wherein,
the operating circuit is further configured to: after writing the mapping conductance value into a corresponding memristor in the memristor array, reading the conductance value of the corresponding memristor; and
the controller is further configured to: determining whether the conductance value of the corresponding memristor falls within the mapped conductance interval, determining that a write operation is successful in a case where the conductance value of the corresponding memristor falls within the mapped conductance interval, or, in a case where the conductance value of the corresponding memristor does not fall within the mapped conductance interval, writing the mapped conductance value again into a corresponding memristor in the memristor array and causing the conductance value of the corresponding memristor to fall within the mapped conductance interval.
10. The data processing apparatus of claim 8, wherein the algorithm parameters comprise a plurality of parameters mapped into a plurality of memristors, respectively, the controller further configured to: for the plurality of parameters, a corresponding plurality of mapped conductance intervals is independently determined.
11. The data processing apparatus of claim 10, wherein,
the controller is further configured to allow at least two of the plurality of mapped conductance intervals to overlap each other.
12. The data processing apparatus of claim 8, wherein the operating circuit comprises:
the first analog-to-digital converter is configured to map the algorithm parameters into conductance values in the memristor array to obtain the mapped memristor array; and
a second analog-to-digital converter configured to perform an initialization activation operation on the memristor array and/or a read operation on the mapped memristor array,
wherein the accuracy of the first analog-to-digital converter is higher than the accuracy of the second analog-to-digital converter.
13. The data processing apparatus of any of claims 8-12, wherein the memristor structure is a 1T1R structure or a 2T2R structure.
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