CN114121089A - Data processing method and device based on memristor array - Google Patents
Data processing method and device based on memristor array Download PDFInfo
- Publication number
- CN114121089A CN114121089A CN202111404527.7A CN202111404527A CN114121089A CN 114121089 A CN114121089 A CN 114121089A CN 202111404527 A CN202111404527 A CN 202111404527A CN 114121089 A CN114121089 A CN 114121089A
- Authority
- CN
- China
- Prior art keywords
- mapped
- conductance
- memristor
- data processing
- memristors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
A data processing method and a data processing device based on a memristor array are used for a linear operation algorithm. The data processing method comprises the following steps: acquiring algorithm parameters; determining mapped conductance values of corresponding memristors in the memristor array from the algorithm parameters; determining a mapped conductance interval based on the mapped conductance value; and writing the mapping conductance values into corresponding memristors in the memristor array, and enabling the corresponding memristors to fall into the mapping conductance intervals to obtain the mapped memristor array. The data processing method can solve the problem that a quantization error is introduced into a quantization mapping scheme and is not suitable for a linear operation algorithm, so that the memristor conductance mapping precision can be improved, and the operation precision of a memristor storage-calculation integrated system can be improved.
Description
Technical Field
The embodiment of the disclosure relates to a data processing method and a data processing device based on a memristor array.
Background
The memristor is a novel micro-nano electronic device for information storage and processing, and the resistance state of the memristor can be adjusted through external voltage excitation. The memristor-based storage-computation integrated architecture breaks through the Von Neumann architecture bottleneck of a classic computing system, can eliminate the time and energy expenditure required by data transportation, brings about explosive growth of hardware computational power and energy efficiency, and is one of the most potential next-generation hardware chip technologies. Meanwhile, the memristor has the advantages of low operating voltage, low energy consumption, small area, high speed and the like. Therefore, a memory-integrated system based on memristor arrays is a research hotspot in recent years.
Disclosure of Invention
At least one embodiment of the present disclosure provides a data processing method based on a memristor array, which is used for a linear operation algorithm, and the data processing method includes: acquiring algorithm parameters; determining mapped conductance values of corresponding memristors in the memristor array from the algorithm parameters; determining a mapped conductance interval based on the mapped conductance value; and writing the mapping conductance values into corresponding memristors in the memristor array, and enabling the corresponding memristors to fall into the mapping conductance intervals to obtain the mapped memristor array.
For example, in a data processing method provided in at least one embodiment of the present disclosure, making a corresponding memristor fall within a mapped conductance interval includes: after the mapped conductance values are written into corresponding memristors in the memristor array, the conductance values of the corresponding memristors are read; determining whether the conductance value of the corresponding memristor falls within the mapped conductance interval, and determining that the writing operation is successful in the case that the conductance value of the corresponding memristor falls within the mapped conductance interval, or writing the mapped conductance value into the corresponding memristor in the memristor array again and making the corresponding memristor fall within the mapped conductance interval in the case that the conductance value of the corresponding memristor does not fall within the mapped conductance interval.
For example, in a data processing method provided in at least one embodiment of the present disclosure, the algorithm parameter includes a plurality of parameters, the plurality of parameters are respectively mapped into a plurality of memristors, and the determining the mapped conductance interval based on the mapped conductance value includes: a corresponding plurality of mapped conductance intervals is independently determined for the plurality of parameters.
For example, in a data processing method provided in at least one embodiment of the present disclosure, at least two of the plurality of mapped conductance intervals are allowed to overlap with each other.
For example, in a data processing method provided by at least one embodiment of the present disclosure, before writing the mapped conductance values into corresponding memristors in the memristor array and making the corresponding memristors fall within the mapped conductance intervals, the data processing method further includes: an activation operation is initiated on the memristor array.
For example, in a data processing method provided in at least one embodiment of the present disclosure, after obtaining the mapped memristor array, the data processing method further includes: and performing read operation on the mapped memristor array.
For example, in the data processing method provided by at least one embodiment of the present disclosure, the mapped conductance values are written into corresponding memristors in the memristor array using a first analog-to-digital converter, an activation operation for initializing the memristor array is performed using a second analog-to-digital converter, and a read operation is performed on the mapped memristor array, where the accuracy of the first analog-to-digital converter is higher than that of the second analog-to-digital converter.
At least one embodiment of the present disclosure provides a data processing apparatus for a linear operation algorithm, the data processing apparatus including: a memristor array comprising a plurality of memristors; the controller is configured to acquire algorithm parameters, determine mapping conductance values of corresponding memristors in the memristor array according to the algorithm parameters, and determine mapping conductance intervals based on the mapping conductance values; and the operation circuit is configured to write the mapping conductance values into corresponding memristors in the memristor array, and enable the corresponding memristors to fall into the mapping conductance intervals, so that the mapped memristor array is obtained.
For example, in a data processing apparatus provided in at least one embodiment of the present disclosure, the operation circuit is further configured to: after the mapped conductance values are written into corresponding memristors in the memristor array, the conductance values of the corresponding memristors are read; and the controller is further configured to: determining whether the conductance value of the corresponding memristor falls within the mapping conductance interval, and determining that the writing operation is successful in the case that the conductance value of the corresponding memristor falls within the mapping conductance interval, or writing the mapping conductance value into the corresponding memristor in the memristor array again and enabling the corresponding memristor to fall within the mapping conductance interval in the case that the conductance value of the corresponding memristor does not fall within the mapping conductance interval.
For example, in a data processing apparatus provided in at least one embodiment of the present disclosure, the algorithm parameter includes a plurality of parameters, the plurality of parameters are respectively mapped into a plurality of memristors, and the controller is further configured to: a corresponding plurality of mapped conductance intervals is independently determined for the plurality of parameters.
For example, in a data processing apparatus provided in at least one embodiment of the present disclosure, the controller is further configured to allow at least two of the plurality of mapped conductance intervals to overlap with each other.
For example, in a data processing apparatus provided in at least one embodiment of the present disclosure, the operation circuit includes: the first analog-to-digital converter is configured to map the algorithm parameters to conductance values in the memristor array to obtain the mapped memristor array; and a second analog-to-digital converter configured to perform an initialized activation operation on the memristor array and/or perform a read operation on the mapped memristor array, wherein an accuracy of the first analog-to-digital converter is higher than an accuracy of the second analog-to-digital converter.
For example, in the data processing device provided by at least one embodiment of the present disclosure, the structure of the memristor is a 1T1R structure or a 2T2R structure.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.
FIG. 1 shows a structural schematic of a memristor array;
FIG. 2 shows a schematic diagram of a memristor cell having a 1T1R structure;
FIG. 3 shows a schematic diagram of a memristor cell having a 2T2R structure;
FIG. 4 shows an exemplary diagram of a quantization mapping scheme;
FIG. 5 illustrates a schematic flow chart of a memristor array-based data processing method provided by at least one embodiment of the present disclosure;
fig. 6 illustrates an exemplary diagram of a data processing method provided by at least one embodiment of the present disclosure;
FIG. 7 illustrates a schematic flow chart of another memristor array-based data processing method provided by at least one embodiment of the present disclosure;
fig. 8 shows a schematic block diagram of a data processing apparatus provided in at least one embodiment of the present disclosure;
fig. 9 shows a schematic diagram of a data processing apparatus according to at least one embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
Memristors (e.g., resistive random access memories, phase change memories, conductive bridge memories, etc.) are non-volatile devices whose conduction state can be adjusted by applying an external stimulus. The memristor is a two-terminal device, has the characteristics of adjustable resistance and non-volatilization, and is widely applied to the integration of memory and computation. According to kirchhoff's current law and ohm's law, an array formed by memristors can complete multiplication and accumulation calculation in parallel, and storage and calculation both occur in each device of the array. Based on the computing architecture, the storage and computation integrated computing without a large amount of data movement can be realized.
FIG. 1 shows a schematic diagram of a memristor array structure. As shown in fig. 1, the memristor array is made up of a plurality of memristor cells that make up an array of M rows and N columns, with M and N being positive integers. Each memristor cell includes a switching element and one or more memristors. In fig. 1, WL <1>, WL <2> … … WL < M > respectively represent word lines of the first row, the second row … …, and the mth row, and the control electrodes (e.g., the gates of the transistors) of the switching elements in the memristor cell circuits of each row are connected to the word line corresponding to the row; BL <1>, BL <2> … … BL < N > respectively represent bit lines of a first column and a second column … … and an Nth column, and a memristor in the memristor unit circuit of each column is connected with the corresponding bit line of the column; SL <1>, SL <2> … … and SL < M > respectively represent source lines of a first row and a second row … … and an mth row, and the source of the transistor in the memristor unit circuit of each row is connected with the source line corresponding to the row.
The memristor cells in the memristor array of fig. 1 may be, for example, a 1T1R structure or a 2T2R structure, where the memristor cells of the 1T1R structure include one switching transistor and one memristor, and the memristor cells of the 2T2R structure include two switching transistors and two memristors. The present disclosure has no limitations on the type, structure, etc. of the memristor devices.
It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors (e.g., MOS field effect transistors) or other switching devices with the same characteristics. The source and drain of the transistor used herein may be symmetrical in structure, so that there may be no difference in structure between the source and drain. Embodiments of the present disclosure do not limit the type of transistors employed.
FIG. 2 shows a schematic diagram of a memristor cell having a 1T1R structure. As shown in fig. 2, the memristor cell of the 1T1R structure includes one transistor M1 and one memristor R1.
For example, when the transistor M1 is an N-type transistor, its gate is connected to the word line terminal WL, for example, the transistor M1 is turned on when the word line terminal WL is inputted with a high level; the first pole of the transistor M1 may be a source and configured to be connected to a source line terminal SL, e.g., the transistor M1 may receive a reset voltage through the source line terminal SL; the second pole of the transistor M1 may be a drain and configured to be connected to a second pole (e.g., a cathode) of the memristor R1, a first pole (e.g., an anode) of the memristor R1 is connected to the bit line terminal BL, e.g., the memristor R1 may receive a set voltage through the bit line terminal BL. For example, when the transistor M1 is a P-type transistor, its gate is connected to the word line terminal WL, for example, the transistor M1 is turned on when the word line terminal WL is low; the first pole of the transistor M1 may be a drain and configured to be connected to a source line terminal SL, e.g., the transistor M1 may receive a reset voltage through the source line terminal SL; the second pole of the transistor M1 may be a source and configured to be connected to a second pole (e.g., a cathode) of the memristor R1, a first pole (e.g., an anode) of the memristor R1 being connected to the bit line terminal BL, e.g., the memristor R1 may receive a set voltage through the bit line terminal BL. It should be noted that the resistive random access memory structure may also be implemented as another structure, for example, a structure in which the second pole of the memristor R1 is connected to the source line terminal SL, and the embodiment of the present disclosure is not limited thereto.
In the following embodiments, the transistor M1 is exemplified by an N-type transistor.
The word line terminal WL is used to apply a corresponding voltage to the gate of the transistor M1, thereby controlling the transistor M1 to be turned on or off. When the memristor R1 is operated, for example, a set operation or a reset operation, the transistor M1 needs to be turned on first, that is, a turn-on voltage needs to be applied to the gate of the transistor M1 through the word line terminal WL. After the transistor M1 is turned on, for example, a voltage may be applied to the memristor R1 by applying voltages to the memristor R1 at the source line terminal SL and the bit line terminal BL to change the resistance state of the memristor R1. For example, a set voltage may be applied through the bit line terminal BL to cause the memristor R1 to be in a low resistance state; for another example, a reset voltage may be applied across the source terminal SL to place the memristor R1 in a high resistance state. For example, the resistance value in the high resistance state is 100 times or more, for example 1000 times or more, the resistance value in the low resistance state.
It should be noted that, in the embodiment of the present disclosure, for example, by applying voltages to the word line terminal WL and the bit line terminal BL at the same time, the resistance value of the memristor R1 may be made smaller and smaller, that is, the memristor R1 changes from the high resistance state to the low resistance state, and the operation of changing the memristor R1 from the high resistance state to the low resistance state is referred to as a set operation; by applying voltages to the word line terminal WL and the source line terminal SL simultaneously, the resistance value of the memristor R1 can be made larger and larger, that is, the memristor R1 changes from the low resistance state to the high resistance state, and the operation of changing the memristor R1 from the low resistance state to the high resistance state is called a reset operation. For example, the memristor R1 has a threshold voltage that does not change the resistance value (or conductance value) of the memristor R1 when the input voltage magnitude is less than the threshold voltage of the memristor R1. In this case, a calculation may be made with the resistance value (or conductance value) of the memristor R1 by inputting a voltage less than the threshold voltage; the resistance value (or conductance value) of the memristor R1 may be changed by inputting a voltage greater than a threshold voltage.
FIG. 3 shows a schematic diagram of a memristor cell having a 2T2R structure. As shown in fig. 3, a memristor cell of a 2T2R structure includes two transistors M1 and M2 and two memristors R1 and R2. In the following, the transistors M1 and M2 are both N-type transistors as an example.
The gate of the transistor M1 is connected to the word line terminal WL1, for example, when the word line terminal WL1 of M1 inputs a high level, the transistor M1 is turned on, the gate of the transistor M2 is connected to the word line terminal WL2, for example, when the word line terminal WL2 of M2 inputs a high level, the transistor M2 is turned on; the first pole of the transistor M1 may be a source and configured to be connected to a source line terminal SL, for example, the transistor M1 may receive a reset voltage through the source line terminal SL, the first pole of the transistor M2 may be a source and configured to be connected to the source line terminal SL, for example, the transistor M2 may receive a reset voltage through the source line terminal SL, and the first pole of the transistor M1 is connected to the first pole of the transistor M2 and is connected together to the source line terminal SL. The second pole of the transistor M1 may be a drain and configured to be connected to a second pole (e.g., a cathode) of the memristor R1, a first pole (e.g., an anode) of the memristor R1 is connected to the bit line terminal BL1, e.g., the memristor R1 may receive a set voltage through the bit line terminal BL 1; the second pole of the transistor M2 may be a drain and configured to be connected to a second pole (e.g., a cathode) of the memristor R2, a first pole (e.g., an anode) of the memristor R2 is connected to the bit line terminal BL2, e.g., the memristor R2 may receive a set voltage through the bit line terminal BL 2.
It should be noted that, the transistors M1 and M2 in the memristor unit with the 2T2R structure may also both adopt P-type transistors, and details are not described here.
Many works have proved the superiority of neural network algorithms such as single-layer perceptron, multi-layer perceptron, convolutional neural network and the like on the realization of a memory-computation integrated system based on a memristor array. These works commonly employ Quantized Mapping (QM) to map algorithm parameters into memristor arrays.
Fig. 4 shows an exemplary schematic diagram of a quantization mapping scheme.
As shown in fig. 4, the left side of the graph is an algorithmic model of a neural network whose algorithmic parameters are first quantified before being mapped to the memristor array. Currently, algorithm parameters are quantized without directly mapping them to memristors, because: memristors have begun to be used as memories, where multiple bits are represented by multiple different electrical conduction states, and the multiple electrical conduction states are strictly required to be equally spaced from each other (so that the spacing can be simultaneously guaranteed to be maximized) to avoid overlapping between the electrical conduction states, which may result in damage to the information stored by the memristor. The algorithm parameters respectively fall into a plurality of quantization intervals, the solid line represents the actual algorithm parameters falling into the quantization intervals, the dotted line represents the range boundary of the quantization intervals, and the quantization intervals are connected end to end and do not overlap with each other. For example, one algorithm parameter falls into the first quantization interval, and the middle value of the first quantization interval (instead of the actual value of the algorithm parameter) is mapped as a new quantized parameter into the memristor array on the right. The memristor array comprises a plurality of memristors arranged in an array, a dotted arrow in the figure represents that a certain quantized new parameter is mapped to the corresponding memristor, and the quantized new parameter is stored in the memristor as a conductance value of the corresponding memristor.
For example, N algorithm parameters (w for algorithm parameters) of the neural networkiIs represented by) is in the range of 0 to 16, i.e., wi∈[0,16]I is 1,2,3, …, and N, i is a positive integer. Setting the number of quantization intervals to be 16, and quantizing the N algorithm parameters to 16 intervals, wherein the 16 intervals are [0,1 ], [1,2 ], [2,3), [ … …, [14,15 ], [15,16 ] respectively]The median values of each quantization interval are 0.5, 1.5, 2.5, … …, 14.5, 15.5, respectively. If an algorithm parameter is 2.9, the algorithm parameter will fall within the quantization interval of [2,3), but in the above quantization mapping scheme, the algorithm parameter will be mapped with the middle value of 2.5 of the interval [2,3) as a new parameter after quantization. The remaining algorithm parameters will perform the mapping operations in turn in the same manner.
The number of sections is not limited, and may be 4, 6, 32, or the like, and the number of sections may be determined in accordance with actual circumstances and is not limited. The specific range of each quantization interval is determined according to the range of all algorithm parameters in the neural network and the number of preset quantization intervals. In the QM scheme, there is no overlap of the respective quantization intervals with each other.
The QM scheme is widely applied to a neural network algorithm, on one hand, because a memristor still has larger read noise and write deviation, the differentiability of adjacent conductance values needs to be ensured by means of quantization operation; on the other hand, since the neural network algorithm is a nonlinear algorithm, the final classification accuracy is emphasized, and each algorithm parameter is not required to have extremely high precision, so that the memristor conductance value (namely, the parameter value of the neural network algorithm) with high precision does not need to be obtained.
However, the QM scheme is not applicable to linear operation algorithms (e.g., signal processing algorithms including, for example, discrete fourier transform algorithms, discrete cosine transform algorithms, finite impulse response filter algorithms, infinite impulse response filter algorithms, etc.). On one hand, linear operation algorithms have high requirements on the accuracy of the calculation results, and on the other hand, some algorithms (for example, signal processing algorithms) in the linear operation algorithms have huge parameter numbers and different values, the number of required conductance values is extremely large (for example, 1463 different conductance values are required for 1024-point discrete fourier transform of the signal processing algorithms), and if each parameter of the algorithms is forcibly quantized, serious calculation accuracy loss is caused.
At least one embodiment of the present disclosure provides a data processing method for a linear operation algorithm, including: acquiring algorithm parameters; determining mapped conductance values of corresponding memristors in the memristor array from the algorithm parameters; determining a mapped conductance interval based on the mapped conductance value; and writing the mapping conductance values into corresponding memristors in the memristor array, and enabling the corresponding memristors to fall into the mapping conductance intervals to obtain the mapped memristor array.
The data processing method provided by the above embodiment of the disclosure can solve the problem that the QM scheme introduces quantization errors (the concept of quantization errors can be seen in fig. 6) and is not suitable for a linear operation algorithm, so that the precision of memristor conductance mapping can be improved, and the operation precision of a memristor memory-computation integrated system can be improved.
At least one embodiment of the present disclosure further provides a data processing apparatus corresponding to the data processing method.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.
Fig. 5 shows a schematic flow chart of a data processing method based on a memristor array, provided by at least one embodiment of the present disclosure. For example, the data processing method is used for a linear operation algorithm, such as a signal processing algorithm.
As shown in fig. 5, the data processing method includes steps S501 to S504 as follows.
Step S501: and acquiring algorithm parameters.
For example, the algorithm parameters include a plurality of parameters that are respectively mapped into a plurality of memristors.
Step S502: mapped conductance values for corresponding memristors in the memristor array are determined by the algorithm parameters.
For example, in this embodiment, the algorithm parameters are not quantized, and therefore the mapped conductance values of the memristors corresponding to the algorithm parameters represent the actual values of the algorithm parameters.
Step S503: a mapped conductance interval is determined based on the mapped conductance value.
For example, in some embodiments of the present disclosure, one example of step S503 may include: a corresponding plurality of mapped conductance intervals is independently determined for the plurality of parameters.
For example, if plus or minus 0.1 μ S is preset as an acceptable mapping deviation, and the mapping conductance value of one algorithm parameter is 5 μ S, the mapping conductance interval corresponding to the algorithm parameter is 4.9 μ S to 5.1 μ S. For example, the mapped conductance value of another algorithm parameter is 4.9 μ S, and the mapped conductance interval corresponding to the algorithm parameter is 4.8 μ S-5.0 μ S.
For example, at least two of the plurality of mapped conductance intervals are allowed to overlap each other.
For example, the mapped conductance interval 4.9. mu.S to 5.1. mu.S and the mapped conductance interval 4.8. mu.S to 5.0. mu.S overlap each other.
Step S504: and writing the mapping conductance values into corresponding memristors in the memristor array, and enabling the corresponding memristors to fall into the mapping conductance intervals to obtain the mapped memristor array.
For example, in some embodiments of the present disclosure, causing the corresponding memristor to fall within the mapped conductance interval in step S504 may include: after the mapped conductance values are written into corresponding memristors in the memristor array, the conductance values of the corresponding memristors are read; determining whether the conductance value of the corresponding memristor falls within the mapped conductance interval, and determining that the writing operation is successful in the case that the conductance value of the corresponding memristor falls within the mapped conductance interval, or writing the mapped conductance value into the corresponding memristor in the memristor array again and making the corresponding memristor fall within the mapped conductance interval in the case that the conductance value of the corresponding memristor does not fall within the mapped conductance interval.
Due to the existence of memristor writing deviation, a certain deviation exists between the mapping conductance value and the actual conductance value of the corresponding memristor determined by the algorithm parameters. For example, the mapped conductance value is 5 μ S, and the mapped conductance interval is 4.9 μ S to 5.1 μ S. After writing the mapped conductance values into corresponding memristors in the memristor array, the conductance values of the corresponding memristors are read. And if the read conductance value is within the mapping conductance interval of 4.9-5.1 muS, the writing operation is considered to be successful, and if the read conductance value is not within the mapping conductance interval of 4.9-5.1 muS, the mapping conductance value is rewritten into the corresponding memristor in the memristor array until the read conductance value is within the mapping conductance interval.
It should be noted that if the mapping conductance interval is set to be narrower, the mapping result is more accurate, but this requires more mappings, takes more time, consumes more energy, and requires a higher accuracy analog-to-digital converter. In practice, the mapping error may be set to a moderate value (e.g., plus or minus 0.5 μ S) so that the mapping conductance interval is in the proper range.
For example, in some embodiments of the present disclosure, prior to writing the mapped conductance values into corresponding memristors in the memristor array and causing the corresponding memristors to fall within the mapped conductance intervals, the data processing method further comprises: an initialization activation operation (Forming) is performed on the memristor array.
The initialized activation operation refers to: the prepared memristor is in an initial resistance state, generally a high resistance state, and has no resistance change characteristic, in order to enable the memristor to work normally, a relatively large voltage pulse needs to be applied to two ends of the memristor, and the process is called an activation process. After the activation operation, the memristor has normal resistance change characteristics.
For example, in some embodiments of the present disclosure, after obtaining the mapped memristor array, the data processing method further comprises: and performing read operation on the mapped memristor array.
For example, in some embodiments of the present disclosure, a mapped conductance value is written into a corresponding memristor in the memristor array using a first analog-to-digital converter, an activation operation is initiated on the memristor array using a second analog-to-digital converter, and a read operation is performed on the mapped memristor array, where, for example, the accuracy of the first analog-to-digital converter is higher than the accuracy of the second analog-to-digital converter.
In the reading operation of the memristor array, a very high-Precision analog-to-digital converter (ADC) is not needed due to the existence of reading noise, and only a Low-Precision ADC (LP-ADC) is needed in order to save energy consumption and improve the operation speed. In order to achieve higher accuracy in writing the mapped conductance values into the memristor array, a High-Precision analog-to-digital converter (HP-ADC) needs to be employed (i.e., with higher accuracy than the LP-ADC). In the embodiments of the present disclosure, the specific implementation manner of the analog-to-digital converter (ADC) is not limited.
In this embodiment, the second analog-to-digital converter is invoked during an activation operation to initialize the memristor array and a read operation to the mapped memristor array, and the first analog-to-digital converter is invoked during writing of the mapped conductance values into the corresponding memristors in the memristor array, the accuracy of the first analog-to-digital converter being higher than that of the second analog-to-digital converter.
It should be noted that the accuracy of the analog-to-digital converter is divided by the converter full-scale input by 2NN is the ideal number of bits for the converter. For example, assume a 12-bit analog-to-digital converter that can represent any signal applied to the input of the converter at 4096 digital representations at the output. These representations do have a limited amount of error. Thus, if the input full-scale (VFS) of the 12-bit analog-to-digital converter is 10VP-P, the accuracy is + -1.22 mV.
In fact, the required analog-to-digital converter precision is different according to different algorithm types, different application scenes or different device characteristics. For example, for a Discrete Fourier Transform (DFT) algorithm, 10bit and higher precision analog-to-digital converters may be selected in writing mapped conductance values into the memristor array, and 6bit or lower precision analog-to-digital converters may be selected in reading the mapped memristor array.
Since in at least one embodiment of the present disclosure, the operation matrix of the algorithm is often given and fixed, the operation of writing the mapped conductance values into the memristor array only needs to be performed once before the operation of the algorithm, and the conductance values in the memristor array do not need to be rewritten during the operation process. Therefore, in the data processing method provided by the embodiments of the present disclosure, it is necessary and desirable to invoke the energy and time consumption of the high-precision adc in exchange for more accurate operation results.
An exemplary schematic of the data processing method depicted in fig. 5 is shown in fig. 6.
The difference in the mapping results obtained with the quantization mapping scheme and the data processing method of the present disclosure can be seen from fig. 6. In the left box of fig. 6 is the mapping result using the quantization mapping scheme, and in the right box of fig. 6 is the mapping result using the data processing method of the embodiment of the present disclosure. The mapping conductance values of the corresponding memristors in the memristor array determined by the algorithm parameters are T1-T5. In the quantitative mapping scheme, the mapped conductance intervals L1-L5 do not overlap each other (the mapped conductance intervals are shown by solid lines in the left-hand box), whereas in the data processing method of at least one embodiment of the present disclosure, for example, the mapped conductance intervals L3 and L4 overlap, and the mapped conductance intervals L4 and L5 overlap (the mapped conductance intervals are shown by solid lines in the right-hand box). If the quantitative mapping scheme is adopted, the actually mapped conductance values of the mapped conductance values T1-T5 are respectively the middle values of the mapped conductance intervals L1-L5 (as shown by the dashed lines in the left-side box), and if the data processing method of the present disclosure is adopted, the actually mapped conductance values of the mapped conductance values T1-T5 are shown by the dashed lines in the right-side box. Since the mapped conductance values are directly mapped to the conductance values of the memristor array without a parameter quantization step in the case of adopting the data processing method of at least one embodiment of the present disclosure, no quantization error under a quantization mapping scheme (as indicated by an arrow in the left-side box) is introduced, which is a difference between the mapped conductance values and the actually mapped conductance values.
The data processing method provided by at least one embodiment of the disclosure allows the mapping conductance intervals to overlap with each other, so that quantization errors introduced by a quantization mapping scheme are overcome, algorithm parameters with small phase differences can still be distinguished after mapping, and thus high-precision conductance mapping can be realized.
At least one embodiment of the present disclosure provides a memristor array-based data processing method including three parts, namely, a first part is an activation operation, a second part is a mapping operation, and a third part is a read operation, and a schematic flowchart of the data processing method is shown in fig. 7.
As shown in fig. 7, first, the data processing method is started.
Next, as shown in fig. 7, an activation operation is initiated on the memristor array.
For example, the LP-ADC is invoked for an activation operation.
Next, as shown in fig. 7, a mapping operation is performed to obtain a mapped memristor array.
For example, performing the mapping operation includes the steps of: after the algorithm parameters are mapped to the corresponding memristors in the memristor array preliminarily, the HP-ADC is called to read the conductance values of the corresponding memristors, if the read conductance values fall into the mapping conductance interval, the mapping operation is considered to be successful, and if the read conductance values do not fall into the mapping conductance interval, the algorithm parameters are mapped to the corresponding memristors in the memristor array again until the read conductance values are located in the mapping conductance interval.
Next, as shown in fig. 7, a read operation is performed on the mapped memristor array.
For example, the LP-ADC is called for a read operation.
For example, the dashed arrow in fig. 7 pointing from a read operation to a map operation indicates that after multiple read operations have been performed, adjustments may still be needed to the conductance values of the memristor array, and then a return is made to the map operation step to remap the memristor array.
Finally, as shown in fig. 7, the data processing method is ended.
For the data processing method shown in fig. 7, the memristors of the memristor array may be implemented using appropriate types of devices (e.g., phase change memory, magnetic random access memory, etc.), appropriate types of memristor array structures (1T1R structures, 2T2R structures, etc.), appropriate types of pulse operation schemes (pulse number encoding schemes, pulse amplitude encoding schemes, etc.).
Fig. 8 shows a schematic block diagram of a data processing apparatus 800, which is provided by at least one embodiment of the present disclosure and is used for linear operation, and which can be used for executing the data processing method shown in fig. 5.
As shown in fig. 8, the data processing apparatus 800 includes a memristor array 801, a controller 802, and an operational circuit 803, the operational circuit 803 including a first analog-to-digital converter 804 and a second analog-to-digital converter 805.
For example, the memristor array 801 includes a plurality of memristors.
For example, in some embodiments of the present disclosure, the structure of the memristor is the 1T1R structure shown in fig. 2 or the 2T2R structure shown in fig. 3.
The controller 802 is configured to obtain algorithm parameters from which mapped conductance values for corresponding memristors in the memristor array 801 are determined, and determine mapped conductance intervals based on the mapped conductance values.
The operational circuitry 803 is configured to write the mapped conductance values into corresponding memristors in the memristor array 801 and cause the corresponding memristors to fall within the mapped conductance intervals, resulting in the mapped memristor array 801.
The first analog-to-digital converter 804 is configured to map the algorithm parameters to conductance values in the memristor array 801, resulting in a mapped memristor array 801.
The second analog-to-digital converter 805 is configured to perform an initialized activation operation on the memristor array 801 and/or to perform a read operation on the mapped memristor array 801.
For example, the accuracy of the first analog-to-digital converter 804 is higher than the accuracy of the second analog-to-digital converter 805.
For example, in at least one embodiment, the operational circuitry 803 is further configured to read the conductance values of the corresponding memristors in the memristor array 801 after writing the mapped conductance values into the corresponding memristors.
For example, in at least one embodiment, the controller 802 is further configured to determine whether the conductance value of the corresponding memristor falls within the mapped conductance interval, to determine that the write operation was successful in the case that the conductance value of the corresponding memristor falls within the mapped conductance interval, or to write the mapped conductance value again into the corresponding memristor in the memristor array 801 and cause the corresponding memristor to fall within the mapped conductance interval in the case that the conductance value of the corresponding memristor does not fall within the mapped conductance interval.
For example, in at least one embodiment, the algorithm parameters include a plurality of parameters that are respectively mapped into a plurality of memristors, the controller 802 being further configured to independently determine a corresponding plurality of mapped conductance intervals for the plurality of parameters.
For example, in at least one embodiment, controller 802 is further configured to allow at least two of the plurality of mapped conductance intervals to overlap one another.
For example, the data processing apparatus 800 may be implemented in hardware, software, firmware, or any feasible combination thereof, and the present disclosure is not limited thereto.
The technical effect of the data processing apparatus 800 is the same as that of the data processing method shown in fig. 5, and both can be used to improve the operation accuracy of the memristor memory-computation integrated system, which is not described herein again.
Fig. 9 shows a schematic diagram of a data processing apparatus according to at least one embodiment of the present disclosure.
As shown in fig. 9, the data processing apparatus is used to implement a data processing method according to at least one embodiment of the present disclosure. The data processing device comprises a memristor array and peripheral circuit devices, wherein the peripheral circuit devices comprise a digital-to-analog converter (DAC), a low-precision analog-to-digital converter (LP-ADC), a high-precision analog-to-digital converter (HP-ADC), a trans-impedance amplifier (TIA) and a Multiplexer (MUX).
The memristor array includes M rows and N columns of memristors. The memristor array further comprises M word lines (WL [1: M ]), M source lines (SL [1: M ]), and N bit lines (BL [1: N ]), wherein the M word lines and the M source lines respectively correspond to M rows, and the N bit lines respectively correspond to N columns. Each word line, each source line and each bit line are respectively connected with a corresponding multiplexer, and the multiplexers of the M word lines, the M source lines and the N column lines are respectively controlled by signals WL _ sw [1: M ], SL _ sw [1: M ] and BL _ sw [1: N ]. One input end of M multiplexers connected with M word lines is connected with Ground (GND), and the other input end is connected with voltage signal V _ WL [1: M ]. For example, when a voltage signal V _ WL [1: M ] is applied to word lines WL [1: M ] through the multiplexer, the memristor corresponding to the word line to which the voltage signal is applied is turned on, and when a voltage signal 0 (connected to ground at this time) is applied to word lines WL [1: M ] through the multiplexer, the memristor corresponding to the word line to which the voltage signal 0 is applied is turned off. One input terminal of N multiplexers connected to the N bit lines is connected to a Ground (GND), the other input terminal is connected to a DAC, the DAC converts a digital signal into an analog voltage signal, and the analog voltage signal is applied to the bit lines BL [1: N ] through the multiplexers. Source line voltages V _ SL [1: M ] are applied to the source lines SL [1: M ] through a multiplexer.
In the following, an embodiment of a data processing method provided by at least one embodiment of the present disclosure is briefly described with reference to the data processing apparatus shown in fig. 9, and specifically, reference may be made to the foregoing description.
A controller (not shown in the figures) obtains algorithm parameters, determines mapped conductance values for corresponding memristors in the memristor array from the algorithm parameters, and determines mapped conductance intervals based on the mapped conductance values. Before writing the mapped conductance values to the memristor array, an activation operation is initiated on the memristor array using the LP-ADC. And then, writing the mapping conductance values into corresponding memristors in the memristor array by using the HP-ADC, so as to obtain the mapped memristor array. For example, a voltage is applied to the gate of the memristor through the word line WL [1: M ], and after the memristor is turned on, the electrical conductivity of the memristor can be changed by applying the voltage to the memristor through the source line SL [1: M ] and the bit line BL [1: N ]. After writing the mapped conductance values into the corresponding memristors in the memristor array, the conductance values of the corresponding memristors are read using the HP-ADC and it is determined whether the conductance values of the corresponding memristors fall within the mapped conductance intervals. For example, voltage signals are applied to a word line terminal, a bit line terminal and a source line terminal of a memristor at the same time, source line current flowing through the memristor can be acquired, the source line current is converted into a voltage signal through a trans-resistance amplifier, the voltage signal is converted into a digital signal through an HP-ADC, a conductance value stored in the memristor can be obtained according to the magnitude of the digital signal, and the conductance value is compared with a mapping conductance interval to determine whether mapping is successful.
For the present disclosure, there are also the following points to be explained:
(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.
(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.
Claims (13)
1. A data processing method based on a memristor array is used for a linear arithmetic algorithm, and comprises the following steps:
acquiring algorithm parameters;
determining, by the algorithm parameters, mapped conductance values for corresponding memristors in the memristor array;
determining a mapped conductance interval based on the mapped conductance value;
and writing the mapping conductance values into corresponding memristors in the memristor array, and enabling the corresponding memristors to fall into the mapping conductance intervals to obtain the mapped memristor array.
2. The data processing method of claim 1, wherein causing the corresponding memristor to fall within the mapped conductance interval comprises:
reading the conductance values of the corresponding memristors after writing the mapped conductance values into the corresponding memristors in the memristor array;
determining whether the conductance value of the corresponding memristor falls within the mapped conductance interval, an
Determining that a write operation is successful if the conductance value of the corresponding memristor falls within the mapped conductance interval, or, if the conductance value of the corresponding memristor does not fall within the mapped conductance interval, writing the mapped conductance value into the corresponding memristor in the memristor array again and making the corresponding memristor fall within the mapped conductance interval.
3. The data processing method of claim 1 or 2, wherein the algorithm parameters include a plurality of parameters that are respectively mapped into a plurality of memristors, the determining the mapped conductance interval based on the mapped conductance values comprising:
for the plurality of parameters, a corresponding plurality of mapped conductance intervals is independently determined.
4. The data processing method of claim 3, wherein at least two of the plurality of mapped conductance intervals are allowed to overlap each other.
5. The data processing method of claim 1 or 2, wherein prior to writing the mapped conductance values into corresponding memristors in the memristor array and causing the corresponding memristors to fall within the mapped conductance intervals, the data processing method further comprises:
an activation operation that initializes the memristor array.
6. The data processing method of claim 1, wherein after obtaining the mapped memristor array, the data processing method further comprises:
and performing a read operation on the mapped memristor array.
7. The data processing method of claim 6, wherein the mapped conductance values are written into corresponding memristors in the memristor array using a first analog-to-digital converter, an activation operation to initialize the memristor array using a second analog-to-digital converter, and a read operation to the mapped memristor array,
the accuracy of the first analog-to-digital converter is higher than the accuracy of the second analog-to-digital converter.
8. A data processing apparatus for a linear arithmetic algorithm, comprising:
a memristor array comprising a plurality of memristors;
a controller configured to obtain algorithm parameters from which mapped conductance values of corresponding memristors in the memristor array are determined, a mapped conductance interval being determined based on the mapped conductance values; and
the operation circuit is configured to write the mapped conductance values into corresponding memristors in the memristor array and enable the corresponding memristors to fall into the mapped conductance intervals, so that the mapped memristor array is obtained.
9. The data processing apparatus of claim 8,
the operational circuitry is further configured to: reading the conductance values of the corresponding memristors after writing the mapped conductance values into the corresponding memristors in the memristor array; and
the controller is further configured to: determining whether the conductance value of the corresponding memristor falls within the mapped conductance interval, determining that a write operation is successful in the case that the conductance value of the corresponding memristor falls within the mapped conductance interval, or, in the case that the conductance value of the corresponding memristor does not fall within the mapped conductance interval, writing the mapped conductance value again into the corresponding memristor in the memristor array and causing the corresponding memristor to fall within the mapped conductance interval.
10. The data processing apparatus of claim 8, wherein the algorithm parameters comprise a plurality of parameters that are respectively mapped into a plurality of memristors, the controller further configured to: for the plurality of parameters, a corresponding plurality of mapped conductance intervals is independently determined.
11. The data processing apparatus of claim 10,
the controller is further configured to allow at least two of the plurality of mapped conductance intervals to overlap one another.
12. The data processing apparatus of claim 8, wherein the operational circuitry comprises:
a first analog-to-digital converter configured to map the algorithm parameter to a conductance value in the memristor array, resulting in the mapped memristor array; and
a second analog-to-digital converter configured to perform an activation operation to initialize the memristor array and/or to perform a read operation on the mapped memristor array,
wherein the accuracy of the first analog-to-digital converter is higher than the accuracy of the second analog-to-digital converter.
13. The data processing apparatus of any of claims 8-12, wherein the structure of the memristor is a 1T1R structure or a 2T2R structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111404527.7A CN114121089B (en) | 2021-11-24 | 2021-11-24 | Memristor array-based data processing method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111404527.7A CN114121089B (en) | 2021-11-24 | 2021-11-24 | Memristor array-based data processing method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114121089A true CN114121089A (en) | 2022-03-01 |
| CN114121089B CN114121089B (en) | 2023-05-09 |
Family
ID=80371982
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111404527.7A Active CN114121089B (en) | 2021-11-24 | 2021-11-24 | Memristor array-based data processing method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114121089B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20200327406A1 (en) * | 2019-04-10 | 2020-10-15 | International Business Machines Corporation | Training of artificial neural networks |
| US20200410333A1 (en) * | 2019-06-25 | 2020-12-31 | Arm Limited | Non-volatile memory-based compact mixed-signal multiply-accumulate engine |
| CN112215331A (en) * | 2019-07-10 | 2021-01-12 | 华为技术有限公司 | Data processing method for neural network system and neural network system |
| WO2021082325A1 (en) * | 2019-11-01 | 2021-05-06 | 清华大学 | Memristor-based neural network training method and training apparatus thereof |
| CN113077829A (en) * | 2021-04-20 | 2021-07-06 | 清华大学 | Memristor array-based data processing method and electronic device |
| CN113643175A (en) * | 2021-08-16 | 2021-11-12 | 清华大学 | Data processing method and electronic device |
-
2021
- 2021-11-24 CN CN202111404527.7A patent/CN114121089B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20200327406A1 (en) * | 2019-04-10 | 2020-10-15 | International Business Machines Corporation | Training of artificial neural networks |
| US20200410333A1 (en) * | 2019-06-25 | 2020-12-31 | Arm Limited | Non-volatile memory-based compact mixed-signal multiply-accumulate engine |
| CN112215331A (en) * | 2019-07-10 | 2021-01-12 | 华为技术有限公司 | Data processing method for neural network system and neural network system |
| WO2021082325A1 (en) * | 2019-11-01 | 2021-05-06 | 清华大学 | Memristor-based neural network training method and training apparatus thereof |
| CN113077829A (en) * | 2021-04-20 | 2021-07-06 | 清华大学 | Memristor array-based data processing method and electronic device |
| CN113643175A (en) * | 2021-08-16 | 2021-11-12 | 清华大学 | Data processing method and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114121089B (en) | 2023-05-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10534840B1 (en) | Multiplication using non-volatile memory cells | |
| US10552510B2 (en) | Vector-by-matrix multiplier modules based on non-volatile 2D and 3D memory arrays | |
| US10528643B1 (en) | Vector-matrix multiplication using non-volatile memory cells | |
| CN109214510B (en) | Nerve morphology multi-bit digital weight unit | |
| CN107533858B (en) | Crossbar array, image processor and method for programming memory cell | |
| US10497440B2 (en) | Crossbar arrays for calculating matrix multiplication | |
| CN111406265A (en) | Neural network circuit with non-volatile synapse array | |
| Hu et al. | Dot-product engine as computing memory to accelerate machine learning algorithms | |
| US11521658B2 (en) | Binary weighted voltage encoding scheme for supporting multi-bit input precision | |
| CN114400031B (en) | Complement mapping RRAM (resistive random access memory) storage and calculation integrated chip and electronic equipment | |
| US20210117500A1 (en) | Methods to tolerate programming and retention errors of crossbar memory arrays | |
| CN115862708A (en) | Operation method of memristor array and data processing device | |
| US20220301613A1 (en) | Device and method for performing matrix operation | |
| TWI778674B (en) | Signal preserve in mram during reading | |
| US20200410334A1 (en) | Binary weighted voltage encoding scheme for supporting multi-bit input precision | |
| CN111859261B (en) | Computing circuit and operating method thereof | |
| US9330738B2 (en) | Data storage using analog coding | |
| CN114121089B (en) | Memristor array-based data processing method and device | |
| TWI773393B (en) | Signal amplification in mram during reading | |
| CN115458005A (en) | Data processing method, integrated storage and calculation device and electronic equipment | |
| CN117157636A (en) | Integrated deposit and calculation device, system and operation method thereof | |
| CN111130544A (en) | Defect mitigation in crossbar-based computing environments | |
| CN110797067B (en) | Storage array module and control method, device and module thereof | |
| CN114143412B (en) | Image processing method and image processing apparatus | |
| US20230097363A1 (en) | Data processing system, operating method thereof, and computing system using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |