CN114400031B - Complement mapping RRAM (resistive random access memory) storage and calculation integrated chip and electronic equipment - Google Patents
Complement mapping RRAM (resistive random access memory) storage and calculation integrated chip and electronic equipment Download PDFInfo
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- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
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- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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Abstract
The invention discloses a complement mapping RRAM (resistive random access memory) storage and calculation integrated chip and electronic equipment, wherein the chip comprises a control gating module, an RRAM array module and a complement quantization module, wherein the control gating module receives an input signal, is connected to a bit line, a source line and a word line in the RRAM array module and performs gating and read-write control on the RRAM array module; the complement quantization module is connected to an output line in the RRAM array module, a digital input signal is input to the RRAM array module through the control gating module through a bit line BL, and after the digital input signal is multiplied and added by the RRAM array module and a weight value stored in a complement form, an analog signal is output to the complement quantization module; and the complement quantization module completes quantization of the analog signal in a complement form and outputs a digital signal result. Compared with the traditional mode, the invention realizes the complement quantization of the 2T1R RRAM array multiplication and addition operation, can save nearly half of RRAM array resources, reduces the chip area and reduces the power consumption.
Description
Technical Field
The invention relates to the technical field of an integrated storage and calculation chip, in particular to an RRAM integrated storage and calculation chip with complementary code mapping and electronic equipment.
Background
Due to the separation of storage and computing modules, traditional von neumann computing architectures face a storage wall bottleneck, also known as von neumann bottleneck. The RRAM is taken as a representative memory computing technology to combine the storage and the computation of data, so that the computing speed and the parallelism can be improved, the power consumption is reduced, and the von Neumann bottleneck is broken through. The method is particularly suitable for the field of artificial intelligence depending on array multiplication and addition operation. In the existing artificial intelligence algorithm, for a neural network weighted value represented by a signed number, one positive memristor array and one negative memristor array are used for mapping, so that excessive memristor resources are occupied, and the minimum negative value in a numerical range is lost.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention provides a complement mapping RRAM (resistive random access memory) integrated chip and electronic equipment, wherein the chip adopts a complement mapping and reading mode, weight data are stored on a 2T1R RRAM array in a complement mode, and the result reading of multiply-add operation is completed in the complement mode, and the specific technical scheme is as follows:
a complement mapping RRAM (resistive random access memory) storage and calculation integrated chip comprises a control gating module, an RRAM array module and a complement quantization module, wherein the control gating module receives an input signal, is connected to a bit line BL, a source line SL and a word line WL in the RRAM array module, and performs gating and read-write control on the RRAM array module; the complement quantization module is connected to an output line RBL in the RRAM array module, a digital input signal is input to the RRAM array module through a control gating module through a bit line BL, and after the digital input signal is multiplied and added by the RRAM array module and a weight value stored in a complement form, an analog signal is output to the complement quantization module; and the complement quantization module completes quantization of the analog signal in a complement mode and outputs a digital signal result.
Further, the control gating module comprises: the decoding gating unit receives an input signal, determines a unit in the RRAM array module needing gating according to the input signal, and outputs the input signal to the RRAM array module after the level of the input signal is translated by adopting the level shifting unit.
Furthermore, the RRAM array module consists of three sub-arrays, the three sub-arrays are three 2T1R RRAM arrays, each sub-array comprises n rows and m columns of 2T1R units, each 2T1R unit comprises a resistance change resistor, a gate tube and an output tube, and each 2T1R unit can represent 1/0 two states according to the difference of the high and low resistance states of the resistance change resistor and represents 1bit data; for every N2T 1R cells, a weight data is stored, every N columns are grouped into a group, wherein the first column is a sign bit column and the 2 nd to N th columns are numerical bit columns.
Further, for the 2T1R RRAM array n bit weighted value, once multiply-add operation will gate the n column 2T1R RRAM array, thereby generating n output currents, output to the complement quantization module, specifically, the word line WL of the 2T1R RRAM array plays a gating role, when the corresponding weighted value is selected, the corresponding n word line WL of the group is connected with the power supply voltage, otherwise, the grounding voltage, for the gated cell, when the input signal is 1, the bit line BL is connected with the read voltage Vread, and the storage value is 1, namely, when the resistance change resistance is in the low resistance state, the multiplication result is 1, the output current I is generated for the corresponding output line RBL, when the input signal is 0, the multiplication result is 0, and the output current is also 0; the same column of units share the same output line RBL, so the output currents of the units are mutually superposed, which is equivalent to the superposition of multiplication results.
Furthermore, for the cells with the coordinate [ n, m ] in the 2T1R RRAM array, when writing operation is carried out, a high voltage is connected to the word line WL [ n ] to open a gate tube, a writing voltage Vset is applied between the two ends of the bit line BL and the source line SL, the resistance change resistance can be set to be in a low resistance state, and conversely, a reverse voltage Vreset is applied between the two ends of the bit line BL and the source line SL, the resistance change resistance can be set to be in a high resistance state; when reading, the word line WL [ n ] is connected with high voltage to open the gate tube, meanwhile, the gate tube and the resistance changing resistor form a voltage dividing structure, if the input signal is 1, a forward reading voltage is applied between the bit line BL [ m ] and the source line SL [ m ], if the resistance changing resistor is in a low resistance state at the moment, namely, when 1 is stored, the grid end voltage of the output tube is close to the reading voltage of the bit line BL, the output tube is in a weak sub-threshold area, output current is generated on the output line RBL [ m ], a logic 1 is output, otherwise, no current is output on the output line RBL [ m ], and a logic 0 is output.
Furthermore, there are 8 complementary quantization modules, and each complementary quantization module includes: 8 current-voltage conversion circuits, 1 complement quantization analog-to-digital converter and 1 12-channel-to-1 multi-channel selection circuit, wherein the output of the RRAM array module is gated through the 12-channel-to-1 multi-channel selection circuit, a current signal is output to the current-voltage conversion circuit, the complement quantization analog-to-digital converter which is converted into a voltage signal and passes through complements quantization, and a digital signal result is output.
Further, the 12-channel 1-selection multi-channel selection circuit is a multi-channel gate tube composed of 12 NMOS tubes.
Further, the current-voltage conversion circuit includes: an operational amplifier A1, a transistor PM1, a transistor PM2, a transistor PM3, a transistor PM4 and a switch tube NM 1; the grid electrode of the transistor PM1 is connected with the grid electrode of the PM2 and then connected to the output end of the operational amplifier A1, the source electrode of the transistor PM1 is connected with the source electrode of the transistor PM2, the drain electrode of the transistor PM1 is connected with the source electrode of the transistor PM3, the grid electrode of the transistor PM3 is connected with the grid electrode of the transistor PM4 and then connected to the output line RBL, the drain electrode of the PM3 is connected to the output line RBL, the source electrode of the PM4 is connected to the drain electrode of the PM2, and the drain electrode of the PM4 is connected to the drain electrode of the switching tube; wherein, the operational amplifier A1 and the transistor PM1 form a negative feedback loop to clamp the RBL potential of the output line at VRBLThe same as the potential of the non-inverting input terminal of the operational amplifier a1, the transistor PM2 mirrors the current on the transistor PM1 in proportion, NM1 is a switching tube with a width-length ratio larger than that of PM2, SAMN is the inverse of the sampling clock SAM of the complement quantization analog-to-digital converter, when SAM =0, the sampling switch SH of the complement quantization analog-to-digital converter is turned on, NM1 is turned on, and the node B between the transistor NM1 and the transistor PM4 is pulled to the ground potential; when SAM =1, the sampling switch SH is closed, NM1 is turned off, and the current on RBL charges the capacitor Ctot in the complement quantization analog-to-digital converter through the transistor PM2, completing the conversion of the current to the voltage.
Furthermore, the complement quantization analog-to-digital converter quantizes the voltage signal output by the current-voltage conversion circuit into a digital complement result at one time according to the weight.
An electronic device comprises a shell and the complementary code mapped RRAM integrated chip, wherein the RRAM integrated chip is arranged on the shell.
The invention has the beneficial effects that:
compared with the traditional mode, the invention realizes the complement quantization of the 2T1R RRAM array multiplication and addition operation, can save nearly half of RRAM array resources, reduces the chip area and reduces the power consumption.
Drawings
FIG. 1 is a schematic diagram of an RRAM integrated chip module of the present invention;
FIG. 2 is a schematic diagram of a 2T1R RRAM array circuit employed by the present invention;
FIG. 3 is a schematic diagram of a complementary quantization module of the present invention;
FIG. 4 is a schematic diagram of a current-to-voltage conversion circuit according to the present invention.
Detailed Description
In order to make the objects, technical solutions and technical effects of the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and examples.
As shown in fig. 1, the complement mapped RRAM memory integrated chip of the present invention includes a control gating module, an RRAM array module, and a complement quantization module, where the control gating module receives an input signal, is connected to a bit line BL, a source line SL, and a word line WL in the RRAM array module, and is responsible for gating and read-write control of the RRAM array module; the complement quantization module is connected to an output line RBL in the RRAM array, a digital input signal is input to the RRAM array module through a control gating module via a bit line BL, and is multiplied by a weight value stored by the RRAM array module, the RRAM array module is used as a complement mapping target and stores the weight value in a complement form, namely, a complement mapping mode is adopted in multiplication and addition operation; the complement quantization module completes quantization on the result of the multiplication and addition analog signal of the input signal and the weighted value in a complement mode to generate a quantization result and output a digital signal result; the whole process is calculated in complementary form.
The control gating module comprises a decoding gating unit and a level shift unit and is used for receiving input signals, determining an array unit required to be gated and operations to be taken, wherein the input signals comprise gating signals and voltages applied to lines where the gating signals are located.
The RRAM array module consists of three sub-arrays, each sub-array comprises n rows and m columns of 2T1R units, and each 2T1R unit can represent 1/0 two states according to the difference of the high and low resistance states of the resistance change resistor, and represents 1bit data. An N-bit complement weight data in which the sign bit is represented by one cell and the value bit is represented by N-1 cells. Therefore, in the whole array, every N units store one weight datum, every N columns are divided into a group, wherein the first column is a sign bit column, and the 2 nd to N th columns are numerical bit columns, and the weight is decreased according to a binary system.
In the 2T1R RRAM array, a word line WL plays a role of gating, when a corresponding weight value is selected, n word lines WL corresponding to the group are connected to a power supply voltage, otherwise, a ground voltage is applied, a signal is input to the gated cell through a bit line BL row, when an input signal is 1, the bit line BL is connected to a read voltage Vread, and a value of 1 is stored, namely, when a resistance change resistor is in a low resistance state, a multiplication result is 1, 100nA output current is generated for a corresponding output line RBL, when the input signal is 0, the ground voltage is applied to the bit line BL, the multiplication result is 0, and the output current is also 0. The same output line RBL is shared by the same row of units, so that the output currents are mutually superposed and equivalent to the superposition of multiplication results; therefore, the n bit weighted value once multiply-add operation gates the n column 2T1R RRAM array, thereby generating n output currents, which are output to the complement quantization module. For an n-bit weight value, the 2T1R RRAM array is grouped every n columns, and n cells in the same row are used for storing weights, wherein the first cell stores a sign bit, and the 2 nd to the n th cells store numerical bits.
Specifically, in the embodiment of the present invention, the three sub-arrays are three 2T1R RRAM arrays, each sub-array is composed of 64 × 256 2T1R units, as shown in fig. 2, each 2T1R unit includes a resistance change resistor, a gate tube, and an output tube; when the resistance change resistance is in a high resistance state, the resistance change resistance represents 0, and when the resistance change resistance is in a low resistance state, the resistance change resistance represents 1; for a cell with the coordinate [ n, m ] in a 2T1R RRAM array, n represents the nth row in a 2T1R RRAM array, m represents the mth column in a 2T1R RRAM array, when a write operation is required, a high voltage is connected to a word line WL [ n ] to open a gate tube, a write voltage Vset of 1.5-2V is applied between two ends of a bit line BL and a source line SL, so that the resistance change resistance can be set to be in a low resistance state, and conversely, a reverse voltage Vreset is applied between two ends of the bit line BL and the source line SL, so that the resistance change resistance can be set to be in a high resistance state. When reading operation is needed, the word line WL [ n ] is connected with high voltage to open a gate tube, meanwhile, the gate tube and a resistance change resistor form a voltage division structure, if an input signal is 1, a forward 0.5V reading voltage is applied between a bit line BL [ m ] and a source line SL [ m ], if the resistance change resistor is in a low resistance state at the moment, namely 1 is stored, the grid end voltage of the output tube is close to the reading voltage of the bit line BL, an output tube is in a weak sub-threshold region, weak output current is generated on the output line RBL [ m ], a logic 1 is output, otherwise, no current is output on the output line RBL [ m ], and a logic 0 is output.
In the embodiment of the invention, 8-bit weight is adopted, each 8 columns of each 2T1R RRAM array are divided into one group, 8 units in the same row are adopted in each group to store the weight value in a complementary code mode, wherein the 1 st unit stores a sign bit, and the 2 nd to 8 th units represent digital bits. After passing through the control gating module, the digital input signals are input into the 2T1R RRAM array from the bit line BL, and output currents are generated on the array output lines RBL, and each group generates eight output currents Io [0-7], and then the output currents are input into the complement quantization module.
As shown in fig. 3, which is a schematic circuit diagram of the complementary quantization module of the present invention, the whole chip includes 8 complementary quantization modules, and each complementary quantization module includes: 8 current-voltage conversion circuits, 1 complement quantization analog-to-digital converter and 1 12-channel-to-1 multi-channel selection circuit, wherein the output of the RRAM array module is gated through the 12-channel-to-1 multi-channel selection circuit, a current signal is output to the current-voltage conversion circuit, the complement quantization analog-to-digital converter which is converted into a voltage signal and passes through complements quantization, and a digital signal result is output. Wherein, the 12-channel 1-selection multi-channel selection circuit is a multi-channel gate tube consisting of 12 NMOS tubes.
Fig. 4 is a schematic diagram of a current-voltage conversion circuit. The complement quantization analog-to-digital converter cannot directly quantize the output current generated by the RRAM array module, and needs to be linearly converted into a voltage signal through a current-voltage conversion circuit, namely, a group of N rows of output currents Io [0-N-1] generated by the RRAM array module are linearly converted into a voltage Vo [0-N-1 ].
The current-voltage conversion circuit includes: an operational amplifier A1, a transistor PM1, a transistor PM2, a transistor PM3, a transistor PM4 and a switch tube NM 1; the gate of the transistor PM1 is connected with the gate of the PM2 and then connected to the output end of the operational amplifier A1, the source of the transistor PM1 is connected with the source of the transistor PM2, the drain of the transistor PM1 is connected with the source of the transistor PM3, the gate of the transistor PM3 is connected with the gate of the transistor PM4 and then connected to the output line RBL, the drain of the transistor PM3 is connected with the output line RBL, the source of the transistor PM4 is connected with the drain of the transistor PM2, and the drain of the transistor PM4 is connected with the drain of the switching tube.
The drain ends of output tubes of 2T1R RRAM units in the same column in the RRAM array module are connected in parallel with an output line RBL, NM2 is a multi-way gate tube, EN is a gate signal, an operational amplifier A1 and a transistor PM1 form a negative feedback loop, and the potential of the output line RBL is clamped at VRBLTo ensure the output current is stable, the transistor PM2 mirrors the current on the transistor PM1 proportionally, NM1 is a switching tube with a width-to-length ratio much larger than that of PM2, and SAMN is the inverse of the sampling clock SAM of the analog-to-digital converter. When SAM =0, sampling switch SH is open, NM1 is conductive, and node B is pulled to ground; when SAM =1, the sampling switch SH is closed, NM1 is turned off, and the current on RBL charges the capacitor Ctot in the complement quantization analog-to-digital converter through the transistor PM2, completing the conversion of the current to the voltage. By adjusting the width-to-length ratio of PM1/PM2, the converted voltage can be adjusted to be in a range suitable for quantization of the complement quantization analog-to-digital converter.
Since the n-bit weight values are stored in a complementary form, the first column of sign bit weight values is
The 2 nd to n th columns are numerical digits, and the weight values are sequentially
、
…
Therefore, the output currents generated by the columns have different weights. To quantize the whole of the circuit in a complementary form, n output currents are linearly converted into n voltage signals. The traditional method is to quantize n voltage signals once by using n analog-to-digital converters or n times by using one analog-to-digital converter to obtain n quantization results, then re-weight the quantization results according to weights of the quantization results, and finally obtain a complementary code result. The invention introduces a complement quantization analog-to-digital converter, quantizes the voltage signal output by the current-voltage conversion circuit into a digital complement result at one time according to the weight, and can realize n bit complement quantization in one-time quantization by only one analog-to-digital converter, thereby greatly reducing the number of the analog-to-digital converters and not needing to carry out weighted calculation again.
In the embodiment of the invention, for 8 current output signals generated by 8bit weight values of the array, 8 current-voltage conversion circuits are adopted to convert the 8 current output signals into 8 voltage signals Vo [0-7]]Wherein Vo [0 ]]Represents a sign bit with a weight of
，Vo[1-7]Is a numerical digit whose weight is sequentially
、
…
. The complementary code quantization analog-to-digital converter adopted by the invention converts Vo 0-7]The signals are quantized into a digital complement result at one time according to the weight value, and the signals are not traditionally quantized into a digital domain by 8 voltage signals and then are weighted and combined into a complement result again.
The chip of the invention can be used for realizing the brain-like neural algorithm, can realize the applications such as image recognition, edge calculation and the like with high energy efficiency, and is applied to electronic equipment such as mobile phones, cameras and the like, more specifically: a voice recognition system in the mobile phone and an image recognition system in the camera.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Although the foregoing has described the practice of the present invention in detail, it will be apparent to those skilled in the art that modifications may be made to the practice of the invention as described in the foregoing examples, or that certain features may be substituted in the practice of the invention. All changes, equivalents and modifications which come within the spirit and scope of the invention are desired to be protected.
Claims (9)
1. A complement mapping RRAM (resistive random access memory) storage integrated chip comprises a control gating module, an RRAM array module and a complement quantization module, and is characterized in that the control gating module receives an input signal, is connected to a bit line BL, a source line SL and a word line WL in the RRAM array module, and performs gating and read-write control on the RRAM array module; the complement quantization module is connected to an output line RBL in the RRAM array module, a digital input signal is input to the RRAM array module through a control gating module through a bit line BL, and after the digital input signal is multiplied and added by the RRAM array module and a weight value stored in a complement form, an analog signal is output to the complement quantization module; the complement quantization module completes quantization of the analog signal in a complement form and outputs a digital signal result;
the control gating module comprises: the decoding gating unit receives an input signal, determines a unit in the RRAM array module needing gating according to the input signal, and outputs the input signal to the RRAM array module after the level of the input signal is translated by adopting the level shifting unit.
2. The complement mapped RRAM memory chip of claim 1, wherein the RRAM array module is composed of three sub-arrays, the three sub-arrays are three 2T1R RRAM arrays, each sub-array comprises n rows and m columns of 2T1R units, each 2T1R unit comprises a resistance change resistor, a gate tube and an output tube, each 2T1R unit represents 1/0 two states according to the difference of the high and low resistance states of the resistance change resistor, and represents 1bit data; for every N2T 1R cells, a weight data is stored, every N columns are grouped into a group, wherein the first column is a sign bit column and the 2 nd to N th columns are numerical bit columns.
3. The chip of claim 2, wherein for a 2T1R RRAM array, n bit weighted value one multiply-add operation will gate n column 2T1R RRAM array, thereby generating n output currents, which are output to the complement quantization module, specifically, word line WL of 2T1R RRAM array plays a role of gating, when the corresponding weighted value is selected, the corresponding n word line WL of the group is connected to the power voltage, otherwise, the ground voltage, for the gated cell, when the input signal is 1, the bit line BL is connected to the read voltage Vread, and the storage value is 1, i.e. the resistance change resistance is in low resistance state, the multiplication result is 1, for the corresponding output line RBL generates the output current I, when the input signal is 0, the ground voltage is connected to the bit line BL, the multiplication result is 0, and the output current is also 0; the same output line RBL is shared by the units in the same column, so that the output currents of the units are mutually superposed, which is equivalent to the superposition of multiplication results of the units.
4. A complement mapped RRAM memory integrated chip as claimed in claim 3, wherein for cells with coordinates [ n, m ] in 2T1R RRAM array, when performing write operation, a high voltage is connected to word line WL [ n ] to open the gate, a write voltage Vset is applied between bit line BL and both ends of source line SL to set the resistance change resistance to a low resistance state, and conversely, a reverse voltage Vreset is applied between bit line BL and both ends of source line SL to set the resistance change resistance to a high resistance state; when reading, the word line WL [ n ] is connected with high voltage to open the gate tube, meanwhile, the gate tube and the resistance changing resistor form a voltage dividing structure, if the input signal is 1, a forward reading voltage is applied between the bit line BL [ m ] and the source line SL [ m ], if the resistance changing resistor is in a low resistance state at the moment, namely, when 1 is stored, the grid end voltage of the output tube is close to the reading voltage of the bit line BL, the output tube is in a weak sub-threshold area, output current is generated on the output line RBL [ m ], a logic 1 is output, otherwise, no current is output on the output line RBL [ m ], and a logic 0 is output.
5. The complement mapped RRAM memory integrated chip of claim 1, wherein there are 8 complement quantization modules, each complement quantization module comprising: 8 current-voltage conversion circuits, 1 complement quantization analog-to-digital converter and 1 12-channel-to-1 multi-channel selection circuit, wherein the output of the RRAM array module is gated through the 12-channel-to-1 multi-channel selection circuit, a current signal is output to the current-voltage conversion circuit, the complement quantization analog-to-digital converter which is converted into a voltage signal and passes through complements quantization, and a digital signal result is output.
6. The complement mapped RRAM memory integrated chip of claim 5, wherein said 12-way 1-out multiplexing circuit is a multiplexing gate consisting of 12 NMOS transistors.
7. The complement mapped RRAM memory integrated chip of claim 5, wherein the current-to-voltage conversion circuit comprises: an operational amplifier A1, a transistor PM1, a transistor PM2, a transistor PM3, a transistor PM4 and a switch tube NM 1; the grid electrode of the transistor PM1 is connected with the grid electrode of the PM2 and then connected to the output end of the operational amplifier A1, the source electrode of the transistor PM1 is connected with the source electrode of the transistor PM2, the drain electrode of the transistor PM1 is connected with the source electrode of the transistor PM3, the grid electrode of the transistor PM3 is connected with the grid electrode of the transistor PM4 and then connected to the output line RBL, the drain electrode of the PM3 is connected to the output line RBL, the source electrode of the PM4 is connected to the drain electrode of the PM2, and the drain electrode of the PM4 is connected to the drain electrode of the switching tube; wherein, the operational amplifier A1 and the transistor PM1 form a negative feedback loop to clamp the RBL potential of the output line at VRBLThe same as the potential of the non-inverting input terminal of the operational amplifier a1, the transistor PM2 mirrors the current on the transistor PM1 in proportion, NM1 is a switching tube with a width-length ratio larger than that of PM2, SAMN is the inverse of the sampling clock SAM of the complement quantization analog-to-digital converter, when SAM =0, the sampling switch SH of the complement quantization analog-to-digital converter is turned on, NM1 is turned on, and the node B between the transistor NM1 and the transistor PM4 is pulled to the ground potential; when SAM =1, the sampling switch SH is closed, NM1 is turned off, and the current on RBL charges the capacitor Ctot in the complement quantization analog-to-digital converter through the transistor PM2, completing the conversion of the current to the voltage.
8. The complement mapped RRAM memory integrated chip of claim 5, wherein the complement quantization adc quantizes the voltage signal output by the current-to-voltage conversion circuit into a digital complement result in one time according to weighting.
9. An electronic device comprising a housing and the complement mapped RRAM-save-all chip of any one of claims 1 to 8, wherein the RRAM-save-all chip is disposed on the housing.
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| US8773887B1 (en) * | 2011-05-25 | 2014-07-08 | Peter K. Naji | Resistive memory devices and related methods |
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| WO2021248643A1 (en) * | 2020-06-08 | 2021-12-16 | 中国科学院微电子研究所 | Storage and calculation integrated circuit |
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| US10381071B1 (en) * | 2018-07-30 | 2019-08-13 | National Tsing Hua University | Multi-bit computing circuit for computing-in-memory applications and computing method thereof |
| CN110209375B (en) * | 2019-05-30 | 2021-03-26 | 浙江大学 | Multiply-accumulate circuit based on radix-4 coding and differential weight storage |
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| US8773887B1 (en) * | 2011-05-25 | 2014-07-08 | Peter K. Naji | Resistive memory devices and related methods |
| WO2019114217A1 (en) * | 2017-12-17 | 2019-06-20 | 华中科技大学 | Computing array based on 1t1r device, operation circuit, and operating method |
| WO2021248643A1 (en) * | 2020-06-08 | 2021-12-16 | 中国科学院微电子研究所 | Storage and calculation integrated circuit |
| CN113988279A (en) * | 2021-10-21 | 2022-01-28 | 江南大学 | Output current reading method and system of storage array supporting negative value excitation |
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