CN116524977A

CN116524977A - Memory system and method of operating memory array

Info

Publication number: CN116524977A
Application number: CN202310204420.0A
Authority: CN
Inventors: 柯文昇; 吴秉骏; 李东颖; 张孟凡
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-04-05
Filing date: 2023-03-06
Publication date: 2023-08-01

Abstract

Memory systems and methods of operation of memory arrays are provided. A memory system for performing in-memory Computing (CiM) operations includes a memory array and processing circuitry. The memory array includes a plurality of memory cells. The processing circuitry is coupled to the memory array and includes programming circuitry and control circuitry. The programming circuit is coupled to the memory array and is configured to perform a write operation for programming the electrical characteristics of the memory cells. The control circuit is coupled to the programming circuit and configured to: receiving a plurality of weight data corresponding to a plurality of weight values; and controlling the write operation performed by the programming circuit to program the electrical characteristics of the memory cells in a sequential order of the weight values.

Description

Memory system and method of operating memory array

Technical Field

Embodiments of the present application relate to memory systems and methods of operation of memory arrays.

Background

Implementing High Performance Computing (HPC), such as Artificial Intelligence (AI), deep Learning (DL), machine Learning (ML), reinforcement learning, etc., typically involves a large number of matrix multiplications, the speed of which is limited by the memory access speed, also known as von neumann bottleneck. In view of this speed limitation, the in-memory Computing (CiM) architecture has attracted attention because it is likely to break through the von neumann bottleneck in current computing architectures.

Disclosure of Invention

According to one aspect of an embodiment of the present application, there is provided a memory system for performing memory Computing (CiM) operations, the memory system including a memory array and processing circuitry. The memory array includes a plurality of memory cells. The processing circuitry is coupled to the memory array. The processing circuit includes a programming circuit and a control circuit. The programming circuit is coupled to the memory array and is configured to perform a write operation for programming the electrical characteristics of the memory cells. The control circuit is coupled to the programming circuit and configured to: receiving a plurality of weight data corresponding to a plurality of weight values; and controlling the write operation performed by the programming circuit to program the electrical characteristics of the memory cells in a sequential order of the weight values.

According to another aspect of an embodiment of the present application, there is provided a memory system for performing memory Computing (CiM) operations, the memory system including a memory array and processing circuitry. The memory array comprises a plurality of memory units, and the plurality of memory units respectively store a plurality of weight data corresponding to a plurality of weight values. The plurality of weight data are signed numbers. The memory cells are coupled to bit lines and are controlled by a plurality of word lines, respectively. The processing circuitry is coupled to the memory array. The processing circuit includes a control circuit, a readout circuit, and a shift converter. The control circuit is coupled to the programming circuit and configured to: receiving a plurality of input data corresponding to a plurality of input values; and controlling voltages on the word lines according to the plurality of input data, respectively, thereby controlling each memory cell to be enabled or disabled. The sense circuit is coupled to the bit line and is configured to perform a read operation to read an electrical characteristic of the enabled memory cell and generate a first summation result, wherein the first summation result is based on unsigned data. The shift converter is coupled to the readout circuit and configured to generate a signed summation result by encoding the first summation result using a two's complement representation.

According to one aspect of embodiments of the present application, an operating method for operating a memory array is provided. The memory array includes a plurality of memory cells that respectively store a plurality of weight data corresponding to a plurality of weight values, the memory cells being coupled to bit lines and respectively controlled by a plurality of word lines. The operation method comprises the following steps: controlling voltages on the word lines according to the plurality of input data, respectively, thereby controlling each memory cell to be enabled or disabled; performing a read operation to read an electrical characteristic of the enabled memory cell and generate a first summed result, wherein the first summed result is unsigned data; and generating a signed summation result by encoding the first summation result using a two's complement representation.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates a schematic block diagram of a memory system, according to some embodiments.

Fig. 2A illustrates a table of programming operations for a multi-level cell (MLC) when weight data is unsigned and signed numbers, respectively, according to some embodiments.

FIG. 2B illustrates a table of programming operations for third order cells (TLCs) when the weight data is unsigned and signed numbers, respectively, according to some embodiments.

Fig. 3A illustrates a table of read operations performed on MLCs when weight data is unsigned and signed numbers, respectively, according to some embodiments.

Fig. 3B illustrates data conversion performed by a readout circuit when performing a read operation on an MLC storing weight data for a symbol number, according to some embodiments.

Fig. 3C illustrates a table for performing a read operation on TLC when weight data is an unsigned number and a signed number, respectively, according to some embodiments.

Fig. 3D illustrates data conversion performed by a readout circuit when performing a read operation on TLC of weight data stored with sign numbers, according to some embodiments.

FIG. 4A illustrates a memory system according to some embodiments.

Fig. 4B illustrates a read operation performed by a readout circuit when the weight data is signed numbers, in accordance with some embodiments.

Fig. 5A illustrates a flow chart of a method of operation according to some embodiments.

Fig. 5B illustrates a flow chart of a further method of operation according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations shown in the drawings, the term spaced apart relationship is intended to include different orientations of the device in use or operation. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spaced apart relationship descriptors used herein interpreted accordingly.

Fig. 1 shows a schematic block diagram of a memory system 1 according to some embodiments. The memory system 1 may be used to perform in-memory Computing (CiM) operations. The memory system 1 includes a memory array 10 and a processing circuit (also referred to as a controller) 12 coupled to the memory array 10. The processing circuitry 12 is configured to control operations in the memory array 10. The processing circuitry 12 is configured to perform at least one write operation (also referred to as a program operation) or read operation on the memory array 10. In some embodiments, the memory system 1 is integrated and arranged on a single chip in a system on a chip (SOC) manner. In some embodiments, memory system 1 is part of a larger IC device that includes circuitry for other functions than the memory system. In some embodiments, the memory system 1 is provided on at least one chip.

In the exemplary configuration of the memory system 1 in fig. 1, although not shown, the memory array 10 includes a plurality of memory cells arranged in columns and rows. The memory cell may include at least one memory element. The electrical characteristics (e.g., resistance or threshold voltage or other suitable electrical characteristics) of each memory element may be programmed at different levels. Thus, the memory cell can store data by programming the electrical characteristics of the memory element at the corresponding level. In some embodiments, each memory cell in the memory array 10 is a multi-level cell (MLC), a third-level cell (TLC), a fourth-level cell (QLC), or the like. In some embodiments, the memory system 1 comprising a plurality of memory cells is configured as one of MLC, TLC, or QLC memory for storing data. In one or more embodiments, the MLC, TLC, or QLC memory is further configured to perform CiM operations. In at least one embodiment, one or more advantages may be realized including, but not limited to, a larger memory window (margin for reading data from memory), better computing performance, and the like.

The memory array 10 also includes a plurality of word lines, a plurality of source lines, and at least one bit line. Each memory cell is coupled to processing circuitry 12 by a corresponding bit line and a corresponding word line. The word line is configured to transmit addresses of memory cells or memory elements, etc. among memory cells to be read and/or to be written. Word lines are sometimes referred to as "address lines". At least one bit line and/or source line is configured to transmit data or the like to be written to and/or read from a memory cell or memory element in the memory cells, the data being indicated by an address on the respective word line. At least one bit line and/or source line is sometimes referred to as a "data line". Various numbers of word lines, bit lines, and/or source lines in the memory array 10 are within the scope of the various embodiments.

Examples of programmable memory elements, in order to have different values of electrical characteristics, include, but are not limited to, resistive random access memory (ReRAM or RRAM), magnetic RAM (MRAM), phase Change Memory (PCM), flash memory containing a charge storage material or floating gate, and the like. In one or more embodiments, both NOR and NAND gate flash memory are suitable for implementing memory elements of the memory cells. The RRAM, MRAM, or PCM memory element includes an access transistor electrically coupled in series with a memory layer. The memory layer is programmable to have two or more states corresponding to two or more resistance values of the memory element. The gates of the access transistors of the RRAM, MRAM, or PCM memory elements correspond to the control terminals of the memory elements and are electrically coupled to corresponding word lines. Flash memory elements include transistors with floating gates or charge storage layers. The floating gate or charge storage layer is programmable to store charges of two or more orders corresponding to two or more resistance values of the memory element. The gates of the transistors of the flash memory elements correspond to the control terminals of the memory elements and are electrically coupled to corresponding word lines. Other types or configurations of memory elements are also within the scope of the various embodiments.

The processing circuit 12 includes a programming circuit 120, a control circuit 122, and a readout circuit 124. In at least one embodiment, the processing circuitry 12 further includes one or more clock generators for providing clock signals to various components of the memory system 1, one or more input/output (I/O) circuits for exchanging data with external devices, and/or one or more controllers for controlling various operations in the memory system 1.

Programming circuitry 120 is coupled to memory cells of memory array 10 by at least one bit line and source line to perform a write operation to at least one memory cell in memory array 10. In at least one embodiment, the processing circuitry 12 also includes a word line driver (also referred to as a "word line decoder") coupled to the memory array 10 via word lines. The word line driver is configured to decode a row address of a selected memory cell selected to be accessed in a read operation or a write operation. In at least one embodiment, a write operation is performed on a selected memory cell by programming circuit 120 by controlling the voltage on the corresponding source line, such that the electrical characteristics of the selected memory cell can be adjusted to a level corresponding to the applied voltage.

The sense circuit 124 is coupled to the memory cells of the memory array 10 by at least one bit line to perform a read operation on at least one memory cell of the memory array 10. In at least one embodiment, the sense loop 124 also includes a sense amplifier coupled to the memory array 10 via at least one bit line. The sense amplifier is configured to read an electrical characteristic of the memory cell from the at least one bit line in a read operation.

Control circuitry 122 is coupled to programming circuitry 120 and sensing circuitry 124 to control write operations and/or read operations performed on memory array 10. In at least one embodiment, control circuitry 122 is configured to receive a plurality of weight data corresponding to a plurality of weight values and control programming circuitry 120 to perform a write operation on the memory cells such that the electrical characteristics of the memory cells can be programmed in the order of the weight values. In at least one embodiment, the electrical characteristics of the respective memory cells are programmed in a sequential order of the weight values. As the weight value increases or decreases, the electrical characteristics of each memory cell continue to increase or decrease. Examples of control circuitry 122 include, but are not limited to, a Central Processing Unit (CPU), a memory controller, a Microprocessor Control Unit (MCU), an Application Specific Integrated Circuit (ASIC), a circuit implementation of a Field Programmable Gate Array (FPGA), or a circuit implementation according to a hardware description language (e.g., verilog, VHDL), etc. Other types or configurations of control circuitry 122 are also within the scope of the various embodiments.

For example, in a write operation, the selected memory cell is configured to be supplied with a write voltage through the corresponding word line. In addition, a low voltage is also provided to the selected memory cell by programming circuit 120 through the corresponding bit line and/or the corresponding source line. Thus, a sufficiently large voltage difference is provided to the selected memory cell to perform the write operation. For unselected memory cells, a high voltage is provided to the corresponding bit line of the unselected memory cells. Thus, insufficient voltage is provided to those unselected memory cells.

More specifically, the order of the weight data is different with respect to the weight value for signed numbers and unsigned numbers. Table 1 below shows examples of weight data and weight values for two-bit signed and unsigned numbers arranged in bit order. For example, the following sequence is followed: 00. 01, 10, 11, the bit order of the weight data increases with increasing binary values of the weight data. As shown in table 1, the weight data for signed and unsigned numbers are listed in bit order. For unsigned numbers, the weight value monotonically increases in the bit order of the weight data. However, for signed numbers, the weight value does not monotonically increase or monotonically decrease as the bit order of the weight data increases. When the sign bit of the signed digit is unchanged, the weight value of the signed digit will increase with the bit order of the weight data. However, when the sign bit of the signed number changes (e.g., weight data from 01 to 10), the weight value of the signed number decreases, but the bit order of the weight data increases. In other words, the bit order of the weight data of the unsigned number and the sequence order of the weight values are the same, but the order of the signed numbers is different. This difference between the bit order of the weight data and the sequential order of the weight values results in the control circuit 122 requiring additional conversion when performing a signed digital write operation, so that the electrical characteristics of the memory cells can be programmed in the sequential order of the corresponding weight values. In other words, the electrical characteristics of the memory cells are programmed in the order of the weight values rather than in the order of the bits of the weight data received by the control circuit 122. In this example, while the weight values are each encoded as weight data in a two's complement representation, it should be noted that other suitable encoding mechanisms for signed numbers (such as a one's complement) are within the scope of the various embodiments.

TABLE 1

In at least one embodiment, processing circuitry 12 also includes registers coupled to control circuitry 122. The register is configured to store a table that records programming parameters corresponding to all weight data for signed and unsigned numbers. The programming parameters may be, for example, but are not limited to, a write voltage to be applied on the corresponding source line and/or the corresponding bit line. Accordingly, the control circuit 122 can identify whether the received weight data is a signed number or an unsigned number to obtain appropriate programming parameters from the stored table based on the identification and the received weight data, and can program the electrical characteristics of the selected memory cells in the sequential order of the corresponding weight values.

Optionally, processing circuitry 12 may include conversion logic coupled to control circuitry 122 for data conversion in addition to including registers. For example, the conversion logic may be configured to perform data conversion on signed digital weight data. When the weight data is determined to be an unsigned number, the conversion logic may be disabled, so that the unsigned number weight data may be provided directly to the programming circuit 120 during a write operation. When it is determined that the weight data is a signed number, the conversion logic may be enabled to convert the weight data to a weight value, thus enabling the programming circuit 120 to program the electrical characteristics of the memory cells in the sequential order of the weight values during the write operation.

Fig. 2A illustrates tables 200a, 200b of programming operations on MLCs when weight data is unsigned and signed numbers, according to some embodiments. Table 200a shows the weight data of the unsigned numbers to be programmed, the weight values corresponding to the weight data, and the electrical characteristics (including cell resistance and conductivity) used to program the MLC. In table 200a, the weight values are arranged in a sequence order in a second column, the corresponding weight data to be programmed is located in the first column, and the corresponding electrical characteristics of the MLC are located in the third and fourth columns. It can be observed that the cell resistance and conductivity of the MLC decrease and increase, respectively, as the weight value of the unsigned number increases. In addition, the bit order of the weight data coincides with the sequence order of the weight values.

Table 200b shows the weight data of the signed numbers to be programmed, the weight values corresponding to the weight data, and the electrical characteristics (including cell resistance and conductivity) used to program the MLC. In table 200b, the weight values are arranged in a sequence order in a second column, the corresponding weight data to be programmed is located in the first column, and the corresponding electrical characteristics of the MLC are located in the third and fourth columns. Similarly, as the weight value increases, the cell resistance of the MLC decreases and the conductivity of the memory cell increases. Thus, in tables 200a, 200b, the order of the electrical characteristics (whether cell resistance or conductivity) is programmed in the order of the sequence of weight values, and therefore when programmed with signed and unsigned numbers, the order of the electrical characteristics is the same relative to the sequence of weight values.

Fig. 2B illustrates tables 200c, 200d of programming operations for TLC when weight data is unsigned and signed numbers, according to some embodiments. Table 200c shows the weight data of the unsigned numbers to be programmed, the weight values corresponding to the weight data, and the electrical characteristics (including cell resistance and conductivity) for programming TLC. In table 200c, the weight values are arranged in a sequence order in the second column, the corresponding weight data to be programmed is in the first column, and the corresponding electrical characteristics of TLC are programmed in the third and fourth columns. It can be observed that as the weight value of the unsigned number increases, the cell resistance and conductivity of TLC decrease and increase, respectively. In addition, the bit order of the weight data coincides with the sequence order of the weight values.

Table 200d shows the weight data of the signed numbers to be programmed, the weight values corresponding to the weight data, and the electrical characteristics (including cell resistance and conductivity) used to program TLC. In table 200d, the weight values are arranged in a sequence order in the second column, the corresponding weight data to be programmed is located in the first column, and the corresponding electrical characteristics of TLC are located in the third and fourth columns. Similarly, as the weight value increases, the cell resistance of TLC decreases and the conductivity of the memory cell increases. Thus, in tables 200c, 200d, the order of the electrical characteristics (whether cell resistance or conductivity) is programmed in the order of the sequence of weight values, and therefore when programmed with signed and unsigned numbers, the order of the electrical characteristics is the same relative to the sequence of weight values.

Further, for an electrical characteristic of an unsigned number (whether two or three bits), the cell resistance is inversely proportional to the weight value and the conductivity is proportional to the weight value. More specifically, the programmed conductivity is linearly related to the weight value, which further facilitates CiM operation of the MLC. The CiM operation will be described in detail below.

For example, in a read operation, the selected memory cell is configured to be supplied with a read voltage through a corresponding word line to sufficiently enable the selected memory cell. In addition, a sense current is provided to the selected memory cell through the corresponding source line. Thus, the selected memory cell is enabled to perform a read operation, and the current flowing through the memory cell is determined by the electrical characteristics of the memory storage element within the memory cell (which is programmed at the level corresponding to the weight data) and provided to the corresponding bit line. The sense amplifier is configured to receive the current and compare it to at least one current threshold to determine a level of the received current. Thus, the data stored in the selected memory cell can be obtained by the comparison result generated by the sense amplifier.

Fig. 3A illustrates tables 300a, 300b of read operations performed on MLCs when weight data is unsigned and signed numbers, according to some embodiments. Table 300a shows stored unsigned digital weight data, weight values corresponding to the weight data, and electrical characteristics (including cell resistance and conductivity) of the MLC to be read. In table 300a, the sequence order of the weight values is the same as the bit order of the weight data, so the order of the electrical characteristics (especially the conductivity) read from the MLC also follows the bit order of the weight data.

Table 300b shows stored signed digit weight data, weight values corresponding to the weight data, and electrical characteristics (including cell resistance and conductivity) of the MLC to be read. In table 300b, the sequence order of the weight values and the bit order of the weight data are different, which makes the order of the electrical characteristics (especially the electrical conductivity) read from the MLC inconsistent with the bit order of the weight data.

In at least one embodiment, a read operation is performed by sensing the level of current flowing through the memory cell by sense circuit 124. One advantage of programming the electrical characteristics to follow the sequential order of the weight values is that when a read operation is performed on an MLC storing unsigned digital weight data, the sequential order of the electrical characteristics specified by the sense circuit 124 can be readily used as unsigned digital weight data because the order of the electrical characteristics (resistance or conductivity) read from the MLC coincides with the bit order of the weight data. Therefore, when a read operation is performed on an MLC storing weight data of an unsigned number, simple data conversion or no data conversion is required. In at least one embodiment, when performing a read operation on an MLC storing weight data of a sign number, the readout circuit 124 requires additional data conversion because the comparison result from the sense amplifier designates the electrical characteristics of the MLC as an unsigned number.

Fig. 3B illustrates data conversion performed by the readout circuitry 124 when performing a read operation on an MLC storing weight data for a symbol number, according to some embodiments. Two lines L1 and L2 are shown in fig. 3B, the lines L1 and L2 corresponding to the relationship between the conductivity and the weight values of the unsigned number and the signed number, respectively. In at least one embodiment, the sense circuit 124 reads conductivity from the MLC and generates first sensed data that is unsigned data. The first readout data corresponds to the data listed in the second column of table 300B shown in fig. 3A, and also covers the weight value range from 0 to 3 shown by line L1 in fig. 3B. To convert the first sensed data from unsigned to signed, the line L1 needs to be shifted left by 2 ^n-1 To line L2, where n is the number of bits carried by each weight data, i.e., 2 in this embodiment. Sometimes, n is also referred to as the number of bits of weight data. Shift line L1 to the left by 2 ^n-1 The operation of (2) corresponds to subtracting 2 from the first read data ^n-1 Is a data conversion of (a). For example, referring to the first row in table 300b, where the first sensed data is 11, the value corresponding to binary value 2 is subtracted ^2-1 The signed read data 01 corresponding to the weight data for programming the MLC is calculated. Thus, during a read operation in which signed weight data is read from the MLC, a value of 2 can be subtracted from the comparison result generated from the sense amplifier ^2-1 To obtain signed digital weight data.

Fig. 3C illustrates tables 300C, 300d for performing read operations on TLCs when weight data is unsigned and signed number, respectively, according to some embodiments. Table 300c shows stored unsigned numerical weight data, weight values corresponding to the weight data, and electrical characteristics (including cell resistance and conductivity) for programming TLC. Table 300d shows stored signed number weight data, weight values corresponding to the weight data, and electrical characteristics (including cell resistance and conductivity) for programming TLC. Similar to tables 300a, 300b discussed above, table 300c shows that the sequence order of the weight values and the bit order of the weight data are the same, so the order of the electrical characteristics (especially conductivity) read from TLC also follows the bit order of the weight data. Table 300d shows that the sequence order of the weight values and the bit order of the weight data are different, which makes the order of the electrical characteristics (especially the conductivity) read from TLC inconsistent with the bit order of the weight data.

Fig. 3D illustrates data conversion performed by readout circuitry 124 when performing a read operation on TLC of weight data stored with sign numbers, according to some embodiments. Two lines L3 and L4 are shown in fig. 3D, the lines L3 and L4 corresponding to the relationship between the conductivity and the weight values of the unsigned and signed numbers, respectively. In at least one embodiment, sense circuit 124 reads the conductivity of the TLC and generates first sensed data that is unsigned data. The first readout data corresponds to the data listed in the second column of table 300D shown in fig. 3C, and also covers the weight value range from 0 to 7 shown by line L3 in fig. 3D. To convert the first read data from unsigned to signed, line L3 needs to be shifted left by 2 ^n-1 To line L4, where n is the number of bits carried by each weight data, i.e. 3 in this embodiment. Shift line L3 left by 2 ^n-1 The operation of (2) corresponds to subtracting 2 from the first read data ^n-1 Is a data conversion of (a). For example, referring to the fifth row in table 300d, where the read data is 011, the value corresponding to binary value 2 is subtracted ^3-1 Signed read data 111 corresponding to weight data programmed for TLC is calculated. Thus, during a read operation to read signed weight data from TLC, a value of 2 can be subtracted from the comparison result generated from the sense amplifier ^3-1 To obtain signed digital weight data.

Fig. 4A illustrates a memory system 4 according to some embodiments. Memory system 4 may be used to perform in-memory Computing (CiM) operations. Memory system 4 includes a memory array 40 and a processing circuit 42 coupled to memory array 40. The processing circuitry 42 is configured to control the operation of the memory array 40. The processing circuitry 42 is configured to perform at least one of a write operation and/or a read operation on the memory array 40.

The memory array 40 includes a plurality of memory cells MC1MCn coupled to word lines WL1-WLn, respectively. Each memory cell MC1-MCn has one terminal coupled to source line SL and the other terminal coupled to bit line BL, and the control terminal of each memory cell is controlled by one of the corresponding word lines. In at least one embodiment, each memory cell includes a memory element and a selector coupled in series between a source line SL and a bit line BL. The control terminals of the selectors are coupled to a corresponding one of the word lines, so that the memory cells are controlled by the voltages provided on the word lines to be enabled or disabled. The electrical characteristics (e.g., resistance or threshold voltage or other suitable electrical characteristics) of each memory element may be programmed at different levels. Thus, the memory cell is capable of storing data by programming the electrical characteristics of the memory element at the corresponding level. Although only one source line and one bit line are shown in fig. 4A, various word lines and/or bit lines and/or numbers of source lines in memory array 40 are within the scope of the various embodiments.

The processing circuit 42 includes a programming circuit 420, a control circuit 422, a readout circuit 424, and a shift converter 426. In at least one embodiment, processing circuitry 42 also includes one or more clock generators for providing clock signals to various components of memory system 4, one or more input/output (I/O) circuits for exchanging data with external devices, and/or one or more controllers for controlling various operations of memory system 4.

The programming circuit 420 is coupled to the memory cells MC1-MCn of the memory array 40 through the bit line BL and the source line SL to perform a write operation to the memory cells MC1-MCn in the memory array 40. In at least one embodiment, the processing circuitry 42 also includes a word line driver (also referred to as a "word line decoder") coupled to the memory array 40 via word lines. The word line driver is configured to decode a row address of a selected memory cell selected to be accessed in a read operation or a write operation. Further, the detailed information of the write operation described above with reference to fig. 2A, 2B is not repeated here.

Sense circuit 424 is coupled to memory cells MC1-MCn of memory array 40 through bit line BL to perform a read operation on at least one memory cell in memory array 40. In at least one embodiment, the sense circuit 424 also includes sense amplifiers that are coupled to the memory array 40 via bit lines. The sense amplifier is configured to read the level of the equivalent electrical characteristic of the enabled memory cells MC1-MCn from the bit line BL in a read operation. Further, the sense circuit 424 generates a summation result SR1, the summation result SR1 being linearly related to the equivalent electrical characteristic received from the bit line BL.

Control circuitry 422 is coupled to programming circuitry 420 and sensing circuitry 424 to control write and/or read operations performed on memory array 40. In at least one embodiment, control circuitry 422 is configured to receive a plurality of weight data corresponding to a plurality of weight values and control programming circuitry 420 to perform a write operation on the memory cells such that the electrical characteristics of the memory cells can be programmed in the order of the weight values. In at least one embodiment, the electrical characteristics of the memory cells are programmed in a sequential order of weight values. Examples of control circuitry 422 include, but are not limited to, a Central Processing Unit (CPU), a memory controller, a Microprocessor Control Unit (MCU), an Application Specific Integrated Circuit (ASIC), a circuit implementation of a Field Programmable Gate Array (FPGA), or a circuit implementation according to a hardware description language (e.g., verilog, VHDL), etc. Other types or configurations of control circuitry 422 are also within the scope of the various embodiments.

Fig. 4B illustrates a table 400a, the table 400a showing the weight values and memory cell resistance values of a read operation performed by the sense circuit 424 when the weight data is a signed number, in accordance with some embodiments. In this embodiment, four memory cells MC1-MC4 are arranged in parallel between the source line SL and the bit line BL in the memory array 40, with all memory cells MC1-MC4 controlled to be enabled by word lines WL1-WL 4. In addition, each memory cell MCI-MC4 is a two-bit MLC capable of storing weight data.

Table 400a shows the weight values stored by memory cells MC1-MC4, the cell resistances of memory cells MC1-MC4, and the equivalent resistances Req and conductivities 1/Req of memory cells MCI-MC4 arranged in parallel. More specifically, table 400a shows a read operation performed on memory cells MC1-MC4 that store negative weight values. In this example, the electrical characteristics of each memory cell are programmed in the sequence order of the weight values rather than the bit order of the weight data. More specifically, the cell resistance of each memory cell is programmed to be inversely proportional to the weight value, while the conductivity is proportional to the weight value. Thus, the conductivity of each memory cell is linear with the corresponding weight value.

As shown in Table 400a, the total conductivity 1/Req of memory cells MC1-MC4 is also proportional to the sum of the weight values programmed in memory cells MC1-MC 4. In other words, when the weight data is a signed number, the linear relationship between the programmed conductivity of each memory cell and the stored weight value remains unchanged in the memory cells of the same bit line. This linear relationship enables the sense circuit 424 to obtain the summed result SR1 from the total current on the bit line BL, the summed result SR1 being linearly related to the summation of the weight values. As a result, the sum of the weight values on the same bit line can be programmed and obtained by the sense circuit 424 by receiving the total current of the memory cells on the same bit line without requiring additional circuitry to convert signed and unsigned numbers prior to addition. Thus, sense circuit 424 is capable of summing signed and/or unsigned numbers stored in memory cells coupled to the same bit line by performing a read operation. In at least one embodiment, the summation result SR1 generated by the readout circuit 424 is unsigned data, and thus the summation result SR1 is linear with weight values, as discussed above with respect to FIGS. 3A-3D.

In at least one embodiment, memory system 4 performs CiM operations to calculate a sum of products (SOP) result. In at least one embodiment, the input data In1-Inn is received by control circuitry 422 to control the voltages on word lines WL1-WLn, respectively, so that each memory cell MC1-MCn may be enabled or disabled accordingly. For example, when input data having an input value of 1 is received, the address decoder may provide a read voltage to the corresponding word line to enable the selected memory cell. Otherwise, when receiving the input data with the input value of 0, the corresponding memory cell is disabled. Thus, each memory cell is enabled or disabled according to the corresponding input data, and a total current corresponding to the sum of the conductivities of the enabled memory cells is provided to the bit line BL. The total current flowing through the bit line BL is equal to the SOP result of the input data In1-Inn multiplied by the weight data stored In the memory cells MC1-MCn, respectively. In other words, when a read operation is performed on the memory cells MC1 to MCn, SOP results of the input data In1 to Inn are multiplied by weight data stored In the memory cells MC1 to MCn, respectively, thereby realizing CiM operation.

However, since the summation result SR1 generated by the readout circuit 424 is unsigned data, additional data conversion is required when the weight data stored in the memory cell is signed numbers. In at least one embodiment, the shift converter 426 is coupled to the readout circuit 424 and is configured to generate a signed summation result SSR based on the summation result SR1 from the readout circuit 424. Specifically, as discussed above with respect to fig. 3A-3D, the summation result SR1 is unsigned data that follows the sequential order of the weight values, as opposed to the bit order of signed weight data. Thus, the shift converter 426 is provided in the processing circuit 42. The shift converter 426 is coupled to the readout circuit 424 and is configured to generate a signed summation result SSR by converting the summation result SR1 into signed data using a two's complement representation.

In at least one embodiment, shift converter 426 includes an accumulator 428 and a subtractor 430. Accumulator 428 is configured to receive input data In1-Inn and sum input data In1-Inn, and then multiply the sum of input data In1-Inn by 2 ^n-1 To generate a summation result SR2. Subtractor 430 is coupled to the accumulationAdder 428 and is configured to subtract summation result SR2 from summation result SR1 to generate signed summation result SSR.

Specifically, the multiplication and accumulation results between the input data In1-Inn and the weight data stored by the memory cells MC1-MCn can be derived as follows:

wherein W is _s1 To W _sn Respectively representing weight data to be stored in the memory cells MC1-MCn, W _u1 To W _un Respectively represent unsigned weight data read from the corresponding memory cells. As described above with respect to fig. 3A-3D, by subtracting 2 ^n-1 Each signed weight data is equivalent to corresponding unsigned data. Thus, in the above derivation, each signed weight data W _sn Can be represented by corresponding unsigned weight data W _un From which 2 is subtracted ^n-1 Instead of. In addition, the input data In1-Inn are multiplied by signed weight data W, respectively _s1 -W _sn The SOP results of (c) may be organized as a sum of two parts. The first part is equal to the input data In1-Inn multiplied by the unsigned weight data W _u1 -W _un Corresponds to the sum of the products of the sum SR1. The second part is equal to the input data In1-Inn multiplied by (-2) ^n-1 ) Corresponds to the negative value of the summation result SR 2. Thus, according to the above derivation, the input data In1-Inn are multiplied by the signed weight data W, respectively _s1 -W _sn Can be obtained by subtracting the sum result SR2 from the sum result SR1. Thus, when the weight data is a signed number, a signed summation result SSR can be generated by operation of accumulator 428 and subtractor 430. In some embodiments, the shift converter 426 is enabled when the weight data is a signed number. Otherwise, when the weight data is an unsigned number, the shift converter 426 is disabled and the summed result SR1 may be provided as an SOP result of the input data and weight value.

Fig. 5A illustrates a flow chart of a method of operation 500 according to some embodiments. The method of operation 500 may be implemented and performed by the memory systems 1 and 4 as shown in fig. 1 and 4A. The operation method 500 includes steps S50, S51.

Although the memory array 40 in fig. 4A is a NAND-type memory array, other types of memory arrays, such as a NOR-type memory array, are also suitable. For example, memory cells in a NOR-type memory array may be coupled in series, and the calculation result may be obtained by measuring the voltage or equivalent resistance of the series-coupled memory cells. Further, fig. 2A-2B, 3A-3D, 4B are for illustration purposes only. Those skilled in the art can modify the electrical values of the memory cells to enable the memory system to accommodate various design concepts and system requirements.

In step S50, a plurality of weight data corresponding to a plurality of weight values is received. In step S51, a write operation is performed on the memory cells, thereby programming the electrical characteristics of the memory cells in the sequential order of the weight values.

More specifically, the received weight data may be signed or unsigned numbers. Since the bit order of the weight data and the sequence order of the weight values of the unsigned numbers are the same but different for the signed numbers, the control circuit 122 or the control circuit 422 needs to perform additional conversion when performing the write operation of the signed numbers, and thus the electrical characteristics of the memory cells can be programmed in the sequence order of the corresponding weight values. In at least one embodiment, the programming operation may be performed by accessing the programming parameters through registers based not only on the received data, but also on the recognition result of whether the weight data is signed.

Fig. 5B illustrates a flow chart of a further method of operation 502 in accordance with some embodiments. The method of operation 502 includes steps S52-S54. The method of operation 502 may be implemented and performed by the memory systems 1 and 4 as shown in fig. 1 and 4A. The method of operation 502 includes steps S52-S54.

In step S52, voltages on the word lines are controlled according to the plurality of input data, respectively, and thus each memory cell storing the sign number is controlled to be enabled or disabled. In step S53, a read operation is performed to read the electrical characteristics of the enabled memory cells and generate a first summation result, wherein the first summation result is based on unsigned data. In step S54, a signed summation result is generated by encoding the first summation result using a two' S complement representation.

More specifically, the electrical characteristics of each memory cell are programmed to store signed weight data. The electrical characteristics are programmed to follow a sequential order of weight values corresponding to the weight data. More specifically, the electrical characteristic is programmed to be linearly dependent on the weight value, and thus the first summation result of the weight values can be obtained by reading the equivalent electrical characteristic of the memory cell in step S53. However, since the electrical characteristics are linearly related to the weight values, the first summation result obtained from the electrical characteristics of the memory cells corresponds to unsigned data. Therefore, data conversion from unsigned first summation to signed summation result is required in step S54.

In at least one embodiment, a memory system for performing memory Computing (CiM) operations includes a memory array and processing circuitry. The memory array includes a plurality of memory cells. The processing circuitry is coupled to the memory array. The processing circuit includes a programming circuit and a control circuit. The programming circuit is coupled to the memory array and is configured to perform a write operation for programming the electrical characteristics of the memory cells. The control circuit is coupled to the programming circuit and configured to: receiving a plurality of weight data corresponding to a plurality of weight values; and controlling the write operation performed by the programming circuit to program the electrical characteristics of the memory cells in a sequential order of the weight values.

In the above memory system, the plurality of weight data are signed numbers encoded in a two's complement representation.

In the above memory system, the electrical characteristics of the memory cells are programmed so that the electrical characteristics increase with an increase in the corresponding weight values.

In the above memory system, the electrical characteristics of each memory cell are programmed to be proportional to the corresponding weight value.

In the above memory system, the memory cells are coupled to the bit lines and controlled by the plurality of word lines, respectively, the memory system comprising: a sense circuit is coupled to the bit line and configured to perform a read operation on the memory cell for reading an electrical characteristic of the memory cell to generate a first summation result, the first summation result corresponding to a sum of products of the plurality of input values multiplied by the weight value.

In the above memory system, the control circuit is further configured to: receiving a plurality of input data corresponding to a plurality of input values; and controlling voltages on the word lines according to the plurality of input data, respectively, to control each memory cell to be enabled or disabled.

In the above memory system, the sense circuit is further configured to read a total current generated by the enabled memory cells coupled to the bit lines to generate a first summation result.

In the above memory system, the first summation result is linearly related to the equivalent electrical characteristics of the memory cells.

In the above memory system, the first summation result is based on unsigned data.

In the above memory system, further comprising: a shift converter is coupled to the readout circuit and configured to generate a signed summation result by encoding the first summation result using a two's complement representation.

In the above memory system, the shift converter includes: an accumulator configured to receive and sum the plurality of input data and multiply the sum of the input data by 2 ^n-1 To generate a second summation result, where n is the number of bits of the weight data; and a subtractor configured to subtract the second summation result from the first summation result to generate a signed summation result.

In the above memory system, the shift converter is enabled when the plurality of weight data are signed numbers.

In at least one embodiment, a memory system for performing memory Computing (CiM) operations includes a memory array and processing circuitry. The memory array comprises a plurality of memory units, and the plurality of memory units respectively store a plurality of weight data corresponding to a plurality of weight values. The plurality of weight data are signed numbers. The memory cells are coupled to bit lines and are controlled by a plurality of word lines, respectively. The processing circuitry is coupled to the memory array. The processing circuit includes a control circuit, a readout circuit, and a shift converter. The control circuit is coupled to the programming circuit and configured to: receiving a plurality of input data corresponding to a plurality of input values; and controlling voltages on the word lines according to the plurality of input data, respectively, thereby controlling each memory cell to be enabled or disabled. The sense circuit is coupled to the bit line and is configured to perform a read operation to read an electrical characteristic of the enabled memory cell and generate a first summation result, wherein the first summation result is based on unsigned data. The shift converter is coupled to the readout circuit and configured to generate a signed summation result by encoding the first summation result using a two's complement representation.

In the above memory system, the sense circuit is configured to read the total current generated by the enabled memory cells from the bit lines to generate a first summation result.

In the above memory system, the first summation result corresponds to the sum of products of the input values multiplied by the weight values, respectively.

In the above memory system, the first summation result is linearly related to the equivalent electrical characteristics of the enabled memory cells.

In at least one embodiment, a memory array includes a plurality of memory cells that respectively store a plurality of weight data corresponding to a plurality of weight values, the memory cells being coupled to bit lines and respectively controlled by a plurality of word lines. An operational method for operating a memory array, comprising: controlling voltages on the word lines according to the plurality of input data, respectively, thereby controlling each memory cell to be enabled or disabled; performing a read operation to read an electrical characteristic of the enabled memory cell and generate a first summed result, wherein the first summed result is unsigned data; and generating a signed summation result by encoding the first summation result using a two's complement representation.

In the above method of operation, the step of generating a signed summation result by encoding the first summation result using a two's complement includes: receiving and summing a plurality of input data, multiplying the summation of the input data by 2 ^n-1 To generate a second summation result, where n is the number of bits of the weight data; and subtracting the second summation result from the first summation result to generate a signed summation result.

In the above method of operation, the first summation result is linearly related to the equivalent electrical characteristics of the enabled memory cells.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A memory system for performing computing operations in a memory, the memory system comprising:

a memory array including a plurality of memory cells; and

processing circuitry coupled to the memory array, the processing circuitry comprising:

programming circuitry coupled to the memory array and configured to perform a write operation for programming an electrical characteristic of the memory cell; and

control circuitry coupled to the programming circuitry and configured to:

receiving a plurality of weight data corresponding to a plurality of weight values; and

the write operations performed by the programming circuit are controlled to program the electrical characteristics of the memory cells in a sequential order of the weight values.

2. The memory system of claim 1, wherein the plurality of weight data is signed numbers encoded in a two's complement representation.

3. The memory system of claim 1, wherein the electrical characteristic of the memory cell is programmed such that the electrical characteristic increases with the corresponding increase in the weight value.

4. The memory system of claim 1, wherein the electrical characteristic of each memory cell is programmed to be proportional to the corresponding weight value.

5. The memory system of claim 1, wherein the memory cells are coupled to bit lines and are each controlled by a plurality of word lines, the memory system comprising:

a sense circuit is coupled to the bit line and configured to perform a read operation on the memory cell for reading the electrical characteristic of the memory cell to generate a first summed result corresponding to a sum of a plurality of input values multiplied by the weight value.

6. The memory system of claim 5, wherein the control circuit is further configured to:

receiving a plurality of input data corresponding to the plurality of input values; and

voltages on the word lines are controlled according to the plurality of input data, respectively, to control each memory cell to be enabled or disabled.

7. The memory system of claim 6, wherein the sense circuit is further configured to read a total current generated by the memory cells coupled to the enablement of the bit line to generate the first summation result.

8. The memory system of claim 5, wherein the first summation result is linearly related to an equivalent electrical characteristic of the memory cell.

9. A memory system for performing computing operations in a memory, the memory system comprising:

a memory array including a plurality of memory cells, the plurality of memory cells respectively storing a plurality of weight data corresponding to a plurality of weight values, the plurality of weight data being signed numbers, the memory cells being coupled to bit lines and respectively controlled by a plurality of word lines; and

control circuitry coupled to the programming circuitry and configured to:

receiving a plurality of input data corresponding to a plurality of input values; and

controlling voltages on the word lines according to the plurality of input data, respectively, thereby controlling each memory cell to be enabled or disabled;

a sense circuit coupled to the bit line and configured to perform a read operation to read an electrical characteristic of the memory cell that is enabled and generate a first summed result, wherein the first summed result is based on unsigned data; and

a shift converter is coupled to the readout circuit and configured to generate a signed summation result by encoding the first summation result using a two's complement representation.

10. A method of operation of a memory array, the memory array comprising a plurality of memory cells that respectively store a plurality of weight data corresponding to a plurality of weight values, the plurality of weight data being signed numbers, the memory cells being coupled to bit lines and respectively controlled by a plurality of word lines, the method of operation comprising:

controlling voltages on the word lines according to a plurality of input data, respectively, thereby controlling each memory cell to be enabled or disabled;

performing a read operation to read an electrical characteristic of the memory cell that is enabled and generating a first summation result, wherein the first summation result is unsigned data; and

a signed summation result is generated by encoding the first summation result using a two's complement representation.