CN112289351B - Memory computing circuit based on magnetic memory - Google Patents
Memory computing circuit based on magnetic memory Download PDFInfo
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- CN112289351B CN112289351B CN201910662244.9A CN201910662244A CN112289351B CN 112289351 B CN112289351 B CN 112289351B CN 201910662244 A CN201910662244 A CN 201910662244A CN 112289351 B CN112289351 B CN 112289351B
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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- G11C11/1657—Word-line or row circuits
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- G11C—STATIC STORES
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- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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- G11C11/1673—Reading or sensing circuits or methods
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- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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Abstract
The invention provides a memory computing circuit based on a magnetic memory, which comprises: a magnetic memory array and a multi-way reading circuit, wherein the magnetic memory array shares a word line with a plurality of memory cells of each row, shares a source line with a plurality of memory cells of each column, and shares a pair of complementary bit lines with a plurality of memory cells of each column or each row, each memory cell comprising: the MOS tube is used for controlling reading and writing of the two MTJs, the drain electrode of the MOS tube is connected with the two MTJs, the storage states of the two MTJs are opposite, the two MTJs are a group and used for recording one bit of data, and the two MTJs are respectively connected with one bit line of the corresponding complementary bit lines; the reading circuit is used for reading the state of one or more memory cells in a column or a row sharing a pair of complementary bit lines so as to realize logic operation according to bits. The invention can directly realize memory calculation on the memory array.
Description
Technical Field
The invention relates to the technical field of magnetic memories, in particular to a memory computing circuit based on a magnetic memory.
Background
In existing von neumann architectures, the memory wall between the processor and the memory becomes a performance bottleneck affecting data computation, and data migration between the processor and the memory increases power consumption.
In order to increase the data calculation speed, there is a method of: a small number of processing units are arranged in the memory or near the memory to realize near memory calculation, so that the original data in the memory can be preprocessed, the transmission bandwidth requirement between the memory and the processor is reduced, the performance is improved, and the power consumption is reduced.
However, in the process of implementing the present invention, the inventors found that at least the following technical problems exist in the prior art:
the processing unit and the storage unit are integrated on the same chip, so that the manufacturing difficulty is high.
Disclosure of Invention
To solve the above problems, the present invention provides a magnetic memory-based memory computing circuit, which can directly implement memory computing on a memory array.
The invention provides a memory computing circuit based on a magnetic memory, which comprises: a magnetic memory array and a multi-way read circuit, wherein,
the magnetic memory array comprises a plurality of memory cells distributed in an array, the plurality of memory cells in each row share a word line, the plurality of memory cells in each column share a source line, and the plurality of memory cells in each column or each row share a pair of complementary bit lines, each memory cell comprising: the MOS tube is used for controlling reading and writing of the two MTJs, the grid electrode of the MOS tube is connected with a corresponding word line, the source electrode of the MOS tube is connected with a corresponding source line, the drain electrode of the MOS tube is connected with the two MTJs, the storage states of the two MTJs are opposite, the two MTJs are in one group and used for recording one bit of data, and the two MTJs are respectively connected with one bit line of corresponding complementary bit lines;
the reading circuit is used for reading the state of one or more memory cells in a column or a row sharing a pair of complementary bit lines so as to realize logic operation according to bits.
Optionally, in each memory cell, the MTJ is a spin transfer torque writing-based MTJ, wherein a reference layer of one MTJ is connected with a drain of the MOS transistor, and a free layer is connected with the bit line; the free layer of the other MTJ is connected with the drain of the MOS tube, and the reference layer is connected with the complementary bit line.
Optionally, in each storage unit, the MTJ is a spin-orbit torque writing MTJ, each row or each column of the magnetic memory array shares a write bit line, there is a spin-orbit torque providing line under a free layer of the MTJ, the spin-orbit torque providing lines of the two MTJs are connected in series, and the spin-orbit torque providing line of one MTJ is connected to the drain of the MOS transistor, and the spin-orbit torque providing line of the other MTJ is connected to the write bit line.
Optionally, the read circuit comprises: sense amplifier, phase inverter and multiplexer, sense amplifier's input and a pair of complementary bit line are connected, a comparison result signal of sense amplifier's output, the comparison result signal divide into two the tunnel, wherein direct input of one kind the multiplexer, another way is through the phase inverter input the multiplexer, the multiplexer is arranged in selecting one of them to export from two tunnel input signal.
Optionally, the sense amplifier is a current-type sense amplifier or a voltage-type sense amplifier.
Optionally, three memory cells in one column or one row sharing a pair of complementary bit lines are used to implement one of a bitwise AND, NAND, OR, and NOR operation, where the MTJ storage state of one memory cell is an opcode and the MTJ storage states of the other two memory cells are operands.
Optionally, the storage unit as the operation code is located in the first row or the first column of the magnetic memory array, and the storage unit as the operand is located in any two rows or any two columns of the magnetic memory array different from the storage unit as the operation code.
The memory calculation circuit based on the magnetic memory comprises a magnetic memory array and a multi-path reading circuit, can directly realize memory calculation on the memory array through reading operation, overcomes the difficulty of manufacturing and integrating the memory and a processor, and has the advantages that the calculation speed and the reading operation of the memory are in the same order of magnitude, and the calculation speed is high. The calculation operation is non-destructive, has no influence on the stored data, and the calculation result can be directly and locally stored in the nonvolatile MRAM array.
Drawings
FIG. 1 is a schematic diagram of a magnetic memory based memory computing circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a magnetic memory based memory computing circuit according to another embodiment of the present invention;
FIG. 3 is a schematic diagram of a magnetic storage based memory computing circuit according to another embodiment of the present invention;
FIG. 4 is a diagram illustrating a memory computing circuit based on a magnetic storage device according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a memory computing circuit based on a magnetic memory, as shown in fig. 1, including: a magnetic memory array 101 and a multi-way read circuit 102, wherein,
the magnetic memory array 101 includes a plurality of memory cells distributed in an array, in this embodiment, the memory array 101 includes a plurality of memory cells in N rows and M columns, the plurality of memory cells in each row share a word line WL, respectively denoted as WL 0-WL (N-1), the plurality of memory cells in each column share a source line SL, respectively denoted as SL 0-SL (M-1), the plurality of memory cells in each column share a pair of complementary bit lines BL and BLB, respectively denoted as BL 0-BL (M-1) and BLB 0-BLB (M-1), and each memory cell includes: the MOS tube is used for controlling reading and writing of the two MTJs, the grid electrode of the MOS tube is connected with the word line of the row where the MOS tube is located, the source electrode of the MOS tube is connected with the source line of the column where the MOS tube is located, the drain electrode of the MOS tube is connected with the two MTJs, the storage states of the two MTJs are opposite, the two MTJs are in one group and used for recording one bit of data, and the two MTJs are respectively connected with one bit line of complementary bit lines of the column where the two MTJ are located;
the read circuit 102 is used for reading the state of one or more memory cells in a column sharing a pair of complementary bit lines to realize a bitwise logic operation.
Optionally, in this embodiment, as shown in fig. 1, the MTJ is an MTJ written based on Spin Transfer Torque (STT), two MTJs of each memory cell are in a parallel relationship, specifically, a reference layer of one MTJ is connected to a drain of the MOS transistor, and a free layer is connected to the bit line BL; the free layer of the other MTJ is connected to the drain of the MOS transistor, and the reference layer is connected to the complementary bit line BLB. The read circuit 102 includes: the sense amplifier SA comprises a sense amplifier SA, an inverter INV and a multiplexer MUX, wherein the input end of the sense amplifier SA is connected with a pair of complementary bit lines, a comparison result signal is output by the output end of the sense amplifier SA and is divided into two paths, one path of the comparison result signal is directly input into the multiplexer MUX, the other path of the comparison result signal is input into the multiplexer MUX through the inverter INV, and the multiplexer MUX is used for selecting one path of the comparison result signal from two paths of input signals to be output. The sense amplifier SA can adopt a current type sense amplifier or a voltage type sense amplifier, if the current type SA is adopted, the same voltage is applied to a memory cell for reading operation, and two currents input by the SA are compared; if voltage type SA is used, the same current is applied to the memory cell for read operation, and the two voltages at the SA input are compared. In this embodiment, the sense amplifier SA is a current-mode sense amplifier.
The memory computing circuit based on the magnetic memory can realize logic computation according to bits through reading operation, has high computing speed, is non-destructive in computing operation, has no influence on stored data, and can directly store the computing result in the nonvolatile STT-MRAM. The reading process of the SA is a process of logical operation by bits, and the logical operation that can be realized includes and, nand, or, nor, not, and xor. Meanwhile, the two MTJs in each storage unit can be read and written at the same time, so that the power consumption is reduced, the speed of data storage and logic calculation is improved, and the reliability of data is also improved by writing data at the same time due to the fact that the two MTJs are required to be in opposite states.
Based on fig. 1, a memory cell of the magnetic memory array is written, and taking a memory cell connected to the word line WL0 and the source line SL0 as an example, when the memory cell is written, WL0 is switched on to turn on the MOS transistor, SL0 is grounded, BL0 is switched on to the write voltage Va, and BLB0 is switched on to the write voltage Vb, or BL0 is switched on to the write voltage-Va, BLB0 is switched on to the write voltage-Vb, and after the write operation, the storage states of MTJ001 and MTJ002 are opposite.
Designating the MTJ of each memory cell connected to bit line BLB as a first MTJ and the MTJ of each memory cell connected to BL as a second MTJ, the numbering of the MTJs in the memory array may be as follows: two MTJs in the memory cell of i row and j column (0 ≦ i ≦ N-1, 0 ≦ j ≦ M-1) are denoted as MTJ (ij1) and MTJ (ij 2). The data of each memory cell is represented by (state of first MTJ, state of second MTJ), and (P, AP) is represented as data of memory cell 0 and (AP, P) is represented as data of memory cell 1. For example, a memory cell including MTJ001 and MTJ002, the data of the memory cell is 0 when the MTJ001 and MTJ002 states are (P, AP); when the MTJ001 and MTJ002 states are (AP, P), the data of the memory cell is 1.
When the logical operation of and, nand, or, nor is realized, it is necessary to simultaneously read data of three memory cells in a column sharing a pair of complementary bit lines, wherein the storage state of MTJ of one memory cell is an operation code, which can determine the type of the bitwise logical operation, and the storage states of MTJ of the other two memory cells are operands. Generally, for simplicity of design, the memory cell position as the operation code is fixed, and generally, the memory cell positioned in the first row of a column sharing a pair of complementary bit lines is taken, and the memory cell position as the operand is arbitrary, and may be the memory cells in any other two rows of a column sharing a pair of complementary bit lines.
The operation principle of each logic operation will be described in detail by taking three memory cells connected to SL0 and WL0, WL1 and WL2 as an example. In the three memory cells, each memory cell includes two MTJs, and one set of two MTJs records one bit (1bit) of data. The storage states of the two MTJs (MTJ001, MTJ002) of the memory cell connected to WL0 are used as operation codes to determine the type of bitwise logical operation, and the storage states of the two MTJs (MTJ101, MTJ102) of the memory cell connected to WL1 and the two MTJs (MTJ201, MTJ202) of the memory cell connected to WL2 are used as operands.
1. AND operation
When the data of the memory cell representing the operation code is 0, i.e. the states MTJ001 and MTJ002 are (P, AP), and the control signal CON of the multiplexer MUX selects the output signal of the output SA, the output result of the MUX is an and operation of two operands.
The specific analysis is as follows:
when the data of the memory cell representing the operand is 00, namely the states of the MTJ101 and the MTJ102 are (P, AP), the states of the MTJ201 and the MTJ202 are (P, AP), the three MTJ states connected by the BLB are all P, and the three MTJ states connected by the BL are all AP, therefore, the SA reads the data of the three memory cells at the same time, the current on the BLB is larger than the current on the BL, the SA outputs 0, and the MUX outputs 0;
when the data of the memory cell representing the operand is 01, namely the states of the MTJ101 and the MTJ102 are (P, AP), the states of the MTJ201 and the MTJ202 are (AP, P), three MTJs connected with BLB are two P, one is AP, three MTJs connected with BL are two AP and one is P, therefore, SA reads the data of the three memory cells simultaneously, the current on BLB is larger than that on BL, SA outputs 0, and MUX outputs 0;
when the data of the memory cells representing the operand is 10, namely the states of the MTJ101 and the MTJ102 are (AP, P), the states of the MTJ201 and the MTJ202 are (P, AP), three MTJs connected with BLB are two P, one is AP, three MTJs connected with BL are two AP and one is P, therefore, SA reads the data of the three memory cells simultaneously, the current on BLB is larger than that on BL, SA outputs 0, and MUX outputs 0;
when the data of the memory cell representing the operand is 11, namely the states of the MTJ101 and the MTJ102 are (AP, P), the states of the MTJ201 and the MTJ202 are (AP, P), three MTJs connected by BLB are two AP, one P, three MTJs connected by BL are two P, and one AP, therefore, SA reads the data of the three memory cells simultaneously, the current on BLB is less than that on BL, SA outputs 1, and MUX outputs 1.
In summary, the truth table for the AND operation is shown in Table 1:
TABLE 1
2. NAND operation
When the data of the memory cell representing the operation code is 0, i.e. the states MTJ001 and MTJ002 are (P, AP), and the control signal CON of the multiplexer MUX selects the output signal of the output inverter INV, the output result of the MUX is an nand operation of two operands.
The specific analysis is as follows:
when the data of the memory cell representing the operand is 00, namely the states of the MTJ101 and the MTJ102 are (P, AP), the states of the MTJ201 and the MTJ202 are (P, AP), the three MTJ states connected by the BLB are all P, and the three MTJ states connected by the BL are all AP, therefore, the SA reads the data of the three memory cells at the same time, the current on the BLB is larger than the current on the BL, the SA outputs 0, and the MUX outputs 1;
when the data of the memory cell representing the operand is 01, namely the states of the MTJ101 and the MTJ102 are (P, AP), the states of the MTJ201 and the MTJ202 are (AP, P), three MTJs connected with BLB are two P, one is AP, three MTJs connected with BL are two AP and one is P, therefore, SA reads the data of the three memory cells simultaneously, the current on BLB is larger than that on BL, SA outputs 0, and MUX outputs 1;
when the data of the memory cells representing the operand is 10, namely the states of the MTJ101 and the MTJ102 are (AP, P), the states of the MTJ201 and the MTJ202 are (P, AP), three MTJs connected with BLB are two P, one is AP, three MTJs connected with BL are two AP and one is P, therefore, SA reads the data of the three memory cells simultaneously, the current on BLB is larger than that on BL, SA outputs 0, and MUX outputs 1;
when the data of the memory cell representing the operand is 11, namely the states of the MTJ101 and the MTJ102 are (AP, P), the states of the MTJ201 and the MTJ202 are (AP, P), three MTJs connected by BLB, two are AP, one is P, three MTJs connected by BL, two are P, and one is AP, therefore, SA reads the data of the three memory cells simultaneously, the current on BLB is less than that on BL, SA outputs 1, and MUX outputs 0.
In summary, the truth table for the NAND operation is shown in Table 2:
TABLE 2
3. Operation of "OR
When the data of the memory cell representing the operation code is 1, i.e. the states MTJ001 and MTJ002 are (AP, P), and the control signal CON of the multiplexer MUX selects the output signal of the output SA, the output result of the MUX is an or operation of two operands.
The specific analysis is as follows:
when the data of the memory cell representing the operand is 00, namely the states of the MTJ101 and the MTJ102 are (P, AP), the states of the MTJ201 and the MTJ202 are (P, AP), three MTJs connected with BLB are P, one MTJ is AP, three MTJs connected with BL are AP, and one P, therefore, SA reads the data of the three memory cells simultaneously, the current on BLB is larger than that on BL, SA outputs 0, and MUX outputs 0;
when the data of the memory cell representing the operand is 01, namely the states of the MTJ101 and the MTJ102 are (P, AP), the states of the MTJ201 and the MTJ202 are (AP, P), three MTJs connected with BLB are two AP, one P, three MTJs connected with BL are two P, and one AP, therefore, SA reads the data of the three memory cells simultaneously, the current on BLB is less than that on BL, SA outputs 1, and MUX outputs 1;
when the data of the memory cells representing the operand is 10, namely the states of the MTJ101 and the MTJ102 are (AP, P), the states of the MTJ201 and the MTJ202 are (P, AP), three MTJs connected with BLB are two AP, one P, three MTJs connected with BL are two P, and one AP, therefore, SA reads the data of the three memory cells simultaneously, the current on BLB is less than that on BL, SA outputs 1, and MUX outputs 1;
when the data of the memory cell representing the operand is 11, that is, the MTJ101 and MTJ102 states are (AP, P), the MTJ201 and MTJ202 states are (AP, P), the three MTJ states connected by BLB are all AP, and the three MTJ states connected by BL are all P, so SA reads the data of the three memory cells at the same time, the current on BLB is less than the current on BL, SA outputs 1, and MUX outputs 1.
In summary, the truth table for the OR operation is shown in Table 3:
TABLE 3
4. NOR operation
When the data of the memory cell representing the operation code is 1, i.e. the states MTJ001 and MTJ002 are (AP, P), and the control signal CON of the multiplexer MUX selects the output signal of the output inverter INV, the output result of MUX is a nor operation of two operands.
The specific analysis is as follows:
when the data of the memory cell representing the operand is 00, namely the states of the MTJ101 and the MTJ102 are (P, AP), the states of the MTJ201 and the MTJ202 are (P, AP), three MTJs connected with BLB are P, one MTJ is AP, three MTJs connected with BL are AP, and one P, therefore, SA reads the data of the three memory cells simultaneously, the current on BLB is larger than that on BL, SA outputs 0, and MUX outputs 1;
when the data of the memory cell representing the operand is 01, namely the states of the MTJ101 and the MTJ102 are (P, AP), the states of the MTJ201 and the MTJ202 are (AP, P), three MTJs connected with BLB are two AP, one P, three MTJs connected with BL are two P, and one AP, therefore, SA reads the data of the three memory cells simultaneously, the current on BLB is less than that on BL, SA outputs 1, and MUX outputs 0;
when the data of the memory cells representing the operand is 10, namely the states of the MTJ101 and the MTJ102 are (AP, P), the states of the MTJ201 and the MTJ202 are (P, AP), three MTJs connected with BLB are two AP, one P, three MTJs connected with BL are two P, and one AP, therefore, SA reads the data of the three memory cells simultaneously, the current on BLB is less than that on BL, SA outputs 1, and MUX outputs 0;
when the data of the memory cell representing the operand is 11, that is, the MTJ101 and MTJ102 states are (AP, P), the MTJ201 and MTJ202 states are (AP, P), the three MTJ states connected by BLB are all AP, and the three MTJ states connected by BL are all P, so SA reads the data of the three memory cells at the same time, the current on BLB is less than the current on BL, SA outputs 1, and MUX outputs 0.
In summary, the truth table for the NOR operation is shown in Table 4:
TABLE 4
5. XOR operation
An exclusive-or operation is the result of an and operation on two operands and the result of a nor operation on both operands, which results from a nor operation.
6. NOT operation
When a read operation is performed on a memory cell, WL0 is switched on to enable the MOS tube to be conducted, SL0 is switched on to read voltage Vr, BL0 and BLB0 are grounded, and when the control signal CON of the multiplexer MUX selects to output the output signal of SA, the output result of MUX is the data of MTJ001 and MTJ002 which are read normally; if the control signal CON of the multiplexer MUX selects the output signal of the output inverter INV, the output result of MUX is equivalent to performing a not operation.
Another embodiment of the present invention provides a memory computing circuit based on a magnetic memory, as shown in fig. 2, including: a magnetic memory array 201 and a multi-way read circuit 202, wherein,
the magnetic memory array 201 includes a plurality of memory cells distributed in an array, in this embodiment, the memory array 201 includes a plurality of memory cells in N rows and M columns, the plurality of memory cells in each row share a word line WL, respectively denoted as WL 0-WL (N-1), the plurality of memory cells in each column share a source line SL, respectively denoted as SL 0-SL (M-1), the plurality of memory cells in each column share a pair of complementary bit lines BL and BLB, respectively denoted as BL 0-BL (M-1) and BLB 0-BLB (M-1), and each memory cell includes: the MOS tube is used for controlling reading and writing of the two MTJs, the grid electrode of the MOS tube is connected with the word line of the row where the MOS tube is located, the source electrode of the MOS tube is connected with the source line of the column where the MOS tube is located, the drain electrode of the MOS tube is connected with the two MTJs, the storage states of the two MTJs are opposite, the two MTJs are in one group and used for recording one bit of data, and the two MTJs are respectively connected with one bit line of complementary bit lines of the column where the two MTJ are located;
the read circuit 202 is used for reading the state of one or more memory cells in a column sharing a pair of complementary bit lines to realize a logical operation by bit.
Alternatively, in this embodiment, as shown in fig. 2, the MTJ is a Spin Orbit Torque (SOT) -based MTJ, and the plurality of memory cells in each row in the magnetic memory array share a write bit line BLW, denoted as BLW 0-BLW (N-1), specifically, there is a Spin Orbit Torque supply line under the free layer of the MTJ, and the Spin Orbit Torque supply lines of the two MTJs are connected in series, and the Spin Orbit Torque supply line of one MTJ is connected to the drain of the MOS transistor, and the Spin Orbit Torque supply line of the other MTJ is connected to the write bit line. The structure of the read circuit 202 is the same as that of the embodiment shown in fig. 1, and the difference is only that the read and write principles of the MTJ are slightly different from those of the embodiment shown in fig. 1, but the principles of the logic operation are the same, and the logical operations of and, nand, or, nor, xor, and not are not described again.
The memory computing circuit based on the magnetic memory can realize logic computation according to bits through reading operation, has high computing speed, is non-destructive in computing operation, has no influence on stored data, and can directly store the computing result in the non-volatile SOT-MRAM. The reading process of the SA is a process of logical operation by bits, and the logical operation that can be realized includes and, nand, or, nor, not, and xor. Meanwhile, the two MTJs in each storage unit can be read and written at the same time, so that the power consumption is reduced, the speed of data storage and logic calculation is improved, and the reliability of data is also improved by writing data at the same time due to the fact that the two MTJs are required to be in opposite states.
In addition, it should be noted that there is another case of the magnetic memory array, in which a plurality of memory cells in each row share a pair of complementary bit lines, and the state of one or more memory cells in a row sharing a pair of complementary bit lines is read by a reading circuit to implement the bitwise logic operation. Fig. 3 shows a case where the MTJ in the storage unit is an MTJ written based on spin transfer torque STT and the plurality of storage units of each row share a pair of complementary bit lines, and fig. 4 shows a case where the MTJ in the storage unit is an MTJ written based on spin orbit torque SOT and the plurality of storage units of each row share a pair of complementary bit lines. In both cases, the principle of the logic operation is the same, but the object of the logic operation is changed from one or three memory cells in a row to one or three memory cells in a column, and the principle and the truth table of the logic operation can refer to the foregoing embodiments, which are not described herein again.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. A magnetic memory based memory computing circuit, comprising: a magnetic memory array and a multi-way read circuit, wherein,
the magnetic memory array comprises a plurality of memory cells distributed in an array, the plurality of memory cells in each row share a word line, the plurality of memory cells in each column share a source line, and the plurality of memory cells in each column or each row share a pair of complementary bit lines, each memory cell comprising: the MOS tube is used for controlling reading and writing of the two MTJs, the grid electrode of the MOS tube is connected with a corresponding word line, the source electrode of the MOS tube is connected with a corresponding source line, the drain electrode of the MOS tube is connected with the two MTJs, the storage states of the two MTJs are opposite, the two MTJs are in one group and used for recording one bit of data, and the two MTJs are respectively connected with one bit line of corresponding complementary bit lines;
the reading circuit comprises a sense amplifier, a phase inverter and a multiplexer, wherein the input end of the sense amplifier is connected with a pair of complementary bit lines, the output end of the sense amplifier outputs a comparison result signal which is divided into two paths, one path of the comparison result signal is directly input into the multiplexer, the other path of the comparison result signal is input into the multiplexer through the phase inverter, the multiplexer selects one path of the comparison result signal from the two paths of input signals to output, the reading circuit is used for reading the state of three storage units on one column or one row sharing the pair of complementary bit lines, one of bit-based AND, NAND, OR and NOR operation is realized, and the reading circuit is also used for reading the state of one storage unit on one column or one row sharing the pair of complementary bit lines, and the NOR operation is realized.
2. The magnetic memory based memory computing circuit of claim 1, wherein in each memory cell, the MTJ is a spin transfer torque based MTJ with a reference layer connected to the MOS transistor drain and a free layer connected to the bit line; the free layer of the other MTJ is connected with the drain of the MOS tube, and the reference layer is connected with the complementary bit line.
3. The magnetic memory-based memory computation circuit of claim 1, wherein in each memory cell, the MTJ is a spin-orbit torque-based MTJ, each row or each column of the magnetic memory array shares a write bit line, there is a spin-orbit torque supply line under a free layer of the MTJ, the spin-orbit torque supply lines of the two MTJs are connected in series, and the spin-orbit torque supply line of one MTJ is connected to the drain of the MOS transistor and the spin-orbit torque supply line of the other MTJ is connected to the write bit line.
4. The magnetic memory-based memory computing circuit of claim 1, wherein the sense amplifier is a current-mode sense amplifier or a voltage-mode sense amplifier.
5. The magnetic memory-based memory computation circuit of claim 1, wherein three memory cells in one column or one row sharing a pair of complementary bit lines are used to implement one of a bitwise and, nand, or and nor operation, wherein the MTJ storage state of one memory cell is an opcode and the MTJ storage states of the other two memory cells are operands.
6. The magnetic memory based memory computing circuit of claim 5, wherein the memory cells as opcodes are located in a first row or a first column of the magnetic memory array, and the memory cells as operands are located in any two rows or any two columns of the magnetic memory array different from the memory cells as opcodes.
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