CN103069495B - The write of resistive storage device and erasing scheme - Google Patents
The write of resistive storage device and erasing scheme Download PDFInfo
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- CN103069495B CN103069495B CN201180039621.5A CN201180039621A CN103069495B CN 103069495 B CN103069495 B CN 103069495B CN 201180039621 A CN201180039621 A CN 201180039621A CN 103069495 B CN103069495 B CN 103069495B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0009—RRAM elements whose operation depends upon chemical change
- G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
- G11C2013/0066—Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/10—Resistive cells; Technology aspects
- G11C2213/15—Current-voltage curve
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/33—Material including silicon
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49004—Electrical device making including measuring or testing of device or component part
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Abstract
A kind of method for programming the resistive storage device of both-end, the method includes: bias voltage is applied to the first electrode of the resistive of equipment；Measure the electric current flowing through unit；And if measured electric current is equal to or more than predetermined value, then stop applying bias voltage.
Description
Cross-Reference to Related Applications
Nothing
Technical field
The method and apparatus that the present invention relates to a kind of non-volatile memory device comprising resistive (cell) for programmed and erased.
Background technology
Recently, as the potential candidate of ultra high-density non-volatile information storage unit, resistive random access memory (resistiverandom-accessMemory, RRAM) creates the biggest interests.Typical RRAM equipment is provided with insulating barrier between pair of electrodes, and presents the hysteretic, resistive transition effects caused by electric pulse.
Resistance switching is construed to: due to Joule heat with at binary oxide (such as, NiO and TiO2Electrochemical process in) or comprise the oxidation-reduction process of ion conductor of oxide, sulfide and polymer, forms conductive filament (conductivefilament) in insulator.Resistance switching is also interpreted as: ion is at TiO2Diffusion is assisted with the field in amorphous silicon (a-silicon) film.
In the case of a-silicon structure, what electric field caused is diffused in silicon the formation causing conductive filament by metal ion, it reduces the resistance of a-silicon structure.After removing biasing (or programming) voltage, these filaments still retain, thus equipment gives its non-volatile feature, and by under the power of the voltage applied in reversed polarity by ion to metal electrode reverse reflux, it is possible to remove these filaments.
Resistive device based on a-silicon structure, especially forms resistive device based on a-silicon structure on the polysilicon, typically presents good persistency or life cycle.But, if in the write repeated with apply too high bias voltage during the erasing cycle, partially due to Joule heat and the movement in a-silicon structure of the non-essential a large amount of metal ion so that the persistency of resistive device can be shortened.Typically also, the yield of RRAM equipment is affected by electrical forming process, wherein, during this electrical forming process, by big voltage (or electric current) signal is applied to this equipment, forms the major part of conductive path in insulation switchable layer.
Summary of the invention
The present invention relates to a kind of non-volatile memory device, a kind of resistive storage device, particularly relates to a kind of bias voltage (or electric current) method and apparatus with the resistive in this equipment of programmed and erased for controlling to be applied to storage cell by change based on the electric current flowing through storage cell.
In one embodiment, a kind of method for programming the resistive storage device of both-end, the method includes: at the first electrode of the resistive that bias voltage (or bias current) is applied to equipment；Measure the electric current flowing through this unit；And if surveyed electric current is equal to or more than predetermined value, stop applying bias voltage.
In another embodiment, a kind of method forming conductive filament structure in switching equipment includes: arrange resistive switching equipment；Apply a voltage to switching equipment and while equipment is applied voltage, measure the electric current flowing through this switching equipment；Climbing is used to increase the voltage applied；Obtaining the graph of a relation of voltage and electric current while voltage increases, this figure comprises slope；Obtaining the threshold voltage for forming conductive filament structure, this threshold voltage is the voltage when slope is changed into predetermined value or becomes greater than predetermined value；And if it is determined that voltage about then stops applying voltage at threshold voltage, wherein, along with applying voltage to switching equipment, switching device forms conductive filament structure.After determining voltage predetermined time delay about at threshold voltage, voltage is stopped.
In another embodiment, a kind of method forming conductive filament structure in switching equipment includes: arrange the resistive switching equipment including top electrodes, switching device and bottom electrode；Multiple potential pulses are applied to switching equipment and when each potential pulse is applied to equipment measurement flow through the electric current of this switching equipment, the voltage of this potential pulse increases in time；Obtain the rate of change of electric current when applying each potential pulse, if the rate of change of electric current is more than or equal to predetermined value, then measure the resistance value of equipment；And if institute's measuring resistance value is less than predetermined value, then start termination procedure to stop applying potential pulse.Along with potential pulse is applied to switching equipment, switching device forms conductive filament structure.In one embodiment, the voltage in potential pulse increases in time with linear model.In another embodiment, the voltage in potential pulse increases the most in time.In further embodiment, when starting termination procedure and have passed through regular hour delay, complete termination procedure and stop applying potential pulse.
In another embodiment, a kind of method forming conductive filament structure in switching equipment includes: arrange the resistive switching equipment including top electrodes, switching device and bottom electrode；In predetermined time period, predetermined voltage is applied to equipment；And measure the rate over time of the electric current in equipment in predetermined time period；If the rate of change of electric current more than predetermined value, then starts termination procedure to stop applying predetermined voltage, and if the rate of change of electric current is less than predetermined value, then continue to predetermined voltage.Along with predetermined voltage is applied to switching equipment, switching device forms conductive filament structure.
In yet another embodiment, a kind of method forming conductive filament structure in switching equipment includes: arrange the resistance switching equipment including top electrodes, switching device and bottom electrode；In predetermined time period, scheduled current is applied to equipment；Measure the voltage rate over time striding across equipment in predetermined time period；If striding across the rate of change of the voltage that equipment declines more than predetermined value, then start termination procedure to stop applying scheduled current, and if stride across the rate of change of the voltage that equipment declines less than predetermined value, then continue to scheduled current.Along with electric current is applied to switching equipment, switching device forms conductive filament structure.
In yet another embodiment, a kind of method forming conductive filament structure in switching equipment includes: arrange the resistive switching equipment including top electrodes, switching device and bottom electrode；Multiple current impulses are applied to switching equipment and when each current impulse is applied to equipment measurement stride across the voltage of switching equipment, the electric current in current impulse increases in time；If the rate of change of voltage is more than predetermined value, then measure the resistance value of equipment；And if institute's measuring resistance value is less than predetermined resistance, then start termination procedure.Along with current impulse is applied to switching equipment, switching device forms conductive filament structure.In one embodiment, the electric current in current impulse increases in time with linear model.In another is implemented, the electric current in current impulse increases the most in time.In another embodiment, when have passed through regular hour delay after starting termination procedure, termination procedure is completed.
Describe one or more embodiments of the detail in the accompanying drawings and the description below.From description, accompanying drawing and claim, other features, target and advantage will be apparent from.
Accompanying drawing explanation
Hereinafter, will be described in connection with the drawings exemplary embodiment, wherein similar reference represents similar element, and wherein:
Fig. 1 illustrates the non-volatile memory device including bottom electrode, switchable dielectric and top electrodes according to an embodiment of the invention；
Fig. 2 illustrates the resistance switching characteristics of equipment according to an embodiment of the invention；
Fig. 3 A is shown through program voltage VpthIt is applied to top electrodes and is in the two-end device of open mode；
Fig. 3 B is shown through erasing voltage VethThe two-end device being applied to top electrodes and be closed.
Fig. 4 illustrates according to an embodiment of the invention based on non-crystalline silicon or the crossbar memory array 400 of amorphous silicon (a-Si).
Fig. 5 illustrates the block diagram of the non-volatile memory device including control circuit and unit array according to an embodiment of the invention.
Fig. 6 A illustrates the volt-ampere curve of programming cycle about non-volatile memory device according to an embodiment of the invention.
Fig. 6 B illustrates the volt-ampere curve in the programmed and erased cycle of non-volatile memory device according to an embodiment of the invention.
Fig. 7 illustrates according to an embodiment of the invention for the circuit of programming nonvolatile storage device.
Fig. 8 illustrates the oscillogram of the circuit in Fig. 7 according to an embodiment of the invention.
Detailed description of the invention
Fig. 1 illustrates the non-volatile memory device 100 including bottom electrode 102, switchable dielectric 104 and top electrodes 106 according to an embodiment of the invention.Switchable dielectric 104 presents a resistance, and by using suitable control circuit, this resistance can be selectively set to each value and be reset.In the present embodiment, equipment 100 is the resistive random access memory of both-end (RRAM).It will be appreciated by those of skill in the art that, equipment 100 can also be used as programmable variable capacitor or other kinds of equipment.
RRAM is the two-end device being provided with switchable dielectric between top electrodes and bottom electrode.By electrode is applied the signal of telecommunication such that it is able to control the resistance of switchable dielectric.The signal of telecommunication can be based on electric current or based on voltage.As utilized herein, term " RRAM " or " resistive storage device " refer to a kind of storage device using switchable dielectric, by the applying signal of telecommunication it is thus possible to control the resistance of this switchable dielectric, and the ferroelectricity of switchable dielectric, magnetization and phase place will not change.
In the present embodiment, equipment 100 is RRAM based on amorphous silicon and uses amorphous silicon (a-Si) as switchable dielectric 104.Change the resistance of switchable dielectric 104 according to being formed in a-Si switchable dielectric or take conductive filament away, wherein form or take away the conductive filament voltage with applying as foundation.Top electrodes 106 is the conductive layer comprising silver (Ag) and the source as the ion forming filament in a-Si structure.Although employing silver in the present embodiment, it will be understood that, top electrodes 106 can be formed by other suitable metals various, such as gold (Au), nickel (Ni), aluminum (Al), chromium (Cr), ferrum (Fe), manganese (Mn), tungsten (W), vanadium (V) and cobalt (Co).Bottom electrode 102 is boron doped or the polysilicon electrode of other p-type, and this electrode contacts with the lower surface of a-Si structure.
Fig. 2 illustrates the resistance switching characteristics of equipment 100 according to an embodiment of the invention.Switchable dielectric 104 shows bipolarity handover mechanism.The change of the resistance of switchable dielectric 104 is determined by top electrodes 106 and bottom electrode 102 is applied to the polarity of current signal and the size of switchable dielectric 104.When applying equal to or more than programmed threshold voltage (or program voltage) VpthPositive voltage time, equipment 100 becomes open mode (low resistance state).In an embodiment, based on switchable dielectric 104 and the material of top electrodes 106, the scope of program voltage is between 2 volts to 5 volts.When applying equal to or more than erasing threshold voltage (or erasing voltage) VethNegative voltage time, equipment 100 switches back to closed mode (high resistance state).In an embodiment, the scope of erasing voltage is from-2 volts to-5 volts.If the voltage applied is at two threshold voltage VpthAnd VethBetween, then equipment state is unaffected, and this allows for low pressure and reads process.Once equipment 100 is set to specific resistance states, and the most in the event of a power failure, equipment 100 also remains the information of certain time period (or retention time).
Fig. 3 A and Fig. 3 B illustrates the handover mechanism of equipment 100 during on and off according to an embodiment of the invention.Switching in a-Si medium 104, based on forming and take away a conductive filament or multiple filament in the filament region in a-Si medium 104, wherein forms and takes away the conductive filament programmed and erased voltage with the electrode 102 and 106 that is applied to equipment 100 as foundation.
Fig. 3 A is shown through program voltage VpthIt is applied to top electrodes 106 and is in the equipment 100 of open mode.The switchable dielectric 104 being made up of a-Si is arranged between bottom electrode 102 and top electrodes 106.The top of switchable dielectric 104 includes the metallic region (or conductive path) 302 above top electrodes extends to bottom electrode 102 at about 10nm.During electrical forming process, when the voltage (such as 3～5V) more slightly larger than switching voltage afterwards is applied to top electrodes 106, form metallic region 302.This big voltage causes being spread to bottom electrode 102 from top electrodes 106 by metal ion by what electric field caused, thus forms continuous print conductive path 303.The bottom of switchable dielectric 104 limits filament region 304, in this filament region 304, as the after-applied program voltage V in electrical forming processpthTime formed filament 305.Also region 303 and 305 can be formed during electrical forming process together.As the program voltage V appliedpthThere is provided enough activation energy with by a large amount of metal ions when metallic region 302 pushes bottom electrode 102 to, filament 305 comprises the metallic in the omission of a succession of bottom being limited in switchable dielectric 104.
Thinking that filament 305 includes many metallics, these metallics are separated from each other by nonconducting switchable dielectric and are not limited continuous print conductive path, the path 303 being different from metallic region 302.Based on embodiment, filament 305 extends about 2-10nm.Conductive mechanism in the on-state is the metallic in electron tunneling filament 305.Device on resistance is by running through resistance control between metallic 306 and bottom electrode 102.In the on-state, metallic 306 is near the metallic of bottom electrode 102 and be metallic only surplus in filament region 304 in filament region 304.
Fig. 3 B is shown through erasing voltage VethThe equipment 100 being applied to top electrodes and be closed.Erasing voltage applies enough electromagnetic force to remove at the metallic of vacant capture of a-Si and to take at least some of filament away from filament region 304.Under in off position, the metallic 308 near bottom electrode separates the distance bigger than metallic 306 in the on-state from bottom electrode.Compared with open mode, equipment 100 is placed in high resistance state by this distance increased between metallic 308 and bottom electrode.In one embodiment, opening/closed mode between the scope of resistivity be from 10E3 to 10E7.In the on-state, equipment 100 shows as resistor, and in off position under, show as capacitor (under the most in off position, the substantial amounts of electric current of switchable dielectric non-conducting and show as insulator).In embodiments, in the on-state, resistance is 10E5 ohm, and in off position under, resistance is 10E10 ohm.In another embodiment, in the on-state, resistance is 10E4 ohm, and in off position under, resistance is 10E9 ohm.In further embodiment, in off position under, resistance is at least 10E7 ohm.
In an embodiment, equipment 100 presents controlled open mode, and electric current is 10nA-10mA and persistency is more than 10E6.But, at room temperature, equipment 100 presents the relatively low retention time of 6 years.Think that the reason of low retention time of equipment 100 is to only exist the metallic that a small amount of defect area at filament region 304 catches.Due to the limited amount of the metallic at filament region 304, thus only remove a small amount of metallic and can increase the resistance of equipment 100 significantly and cause equipment 100 to be switched to closed mode from open mode.In order to increase retention time, equipment 100 by increasing quantity vacant in filament region 304 so that catching metallic in omission, and should provide greater amount of metallic in filament region 304.
But, equipment 100 has p-type as bottom electrode 102, and has amorphous silicon as switchable dielectric 104.Owing to a-Si switchable dielectric 104 is formed on polysilicon bottom electrode 102, thus the amorphous silicon being formed on polysilicon bottom electrode 102 is actually similar and between a-Si and p-type polysilicon interface and has relatively small number of omission.Cause the metallic can being captured in filament region 304 less in the less omission in interface.Therefore, the notable of the percentage ratio catching the available omission of the metallic in filament region 304 is needed to change even if the little variation in omission is formed can result in.This retention time that can result in from an equipment to one equipment with from a programming state to another programming state has big fluctuation.It is preferred, therefore, that provide the filament region 304 of the switchable dielectric 104 with higher disappearance density, to increase retention time and to make more can predict retention time.But, vacant formation needs to be controlled, and this makes to produce too many omission in filament region, otherwise will seriously reduce the persistency of equipment 100, as being filed in the U.S. Patent Application No. 12/582 on October 20th, 2009, illustrated by 086, it is herein incorporated as with reference to entirety.
Fig. 4 illustrates based on non-crystalline silicon or a-Si according to an embodiment of the invention crossbar memory array 400.Crossbar memory array 400 includes the parallel array of the bottom electrode 402 extended along a first direction.In an embodiment, bottom electrode 402 includes bottom metal (not shown) and the p-type (not shown) being formed in bottom metal.In the present embodiment, bottom electrode 402 is nanometer scale.Such as, the width of bottom electrode 402 is about 40nm and spacing is about 60nm.
The parallel array of top electrodes 404 extends along second direction to intersect with bottom electrode 402.Top electrodes 404 includes the metal being capable of supply that the ion forming filament, such as silver (Ag), gold (Au), nickel (Ni), aluminum (Al), chromium (Cr), ferrum (Fe), manganese (Mn), tungsten (W), vanadium (V) and cobalt (Co).In an embodiment, top electrodes 404 and bottom electrode 402 are orthogonal.Top electrodes 404 is width about 60nm and the nano wire of spacing about 150nm.
Each cross point 406 of two arrays defines two-terminal resistive memory cell 408.Storage cell 408 at each cross point 406 includes that two are switched the electrode that layer 410 separates.Switchable layer or structure can have the width identical with bottom electrode or narrower than bottom electrode.In certain embodiments, each storage cell in crossbar memory array can store individual bit.In other embodiments, storage cell presents multilevel resistance thus allows to store multiple bit in each unit.
In the present embodiment, switchable layer 410 includes amorphous silicon or other non-crystalline silicons.As used herein, term " amorphous silicon " (amorphoussilicon) refers to be essentially at amorphous phase and can include the silicon materials of a small amount of crystalline silicon.As used herein, term " non-crystalline silicon " (non-crystallinesilicon) refer to present the amorphous silicon of controllable resistor or noncrystalline polysilicon, and combinations thereof etc..
In one embodiment, above-mentioned crossbar memory array can be manufactured on a silicon substrate.In another embodiment, III-V type semiconductor compound (such as GaAs (GaAs), gallium nitride (GaN), boron nitride (BN) etc.) or II-VI type semiconductor compound (such as cadmium selenide, zinc telluridse etc.) are used as substrate.
Fig. 5 illustrates the block diagram of nonvolatile solid state resistive device 500 according to an embodiment of the invention.Equipment 500 includes unit array 502, and this array includes multiple resistive.Resistive can be NAND, NOR, intersection or other configurations.Program/erase voltage (or electric current) is provided unit array by control circuit 504, with the unit in programming or erasure unit array.First selection circuit 506 is configured to select to be applied with a line unit of resistance of the program/erase voltage of control circuit 504.First selection circuit is configured to supply the conductive path of the top electrodes of selected unit, and this makes program/erase program can be applied to this unit.Second selection circuit 508 is coupled to the bottom electrode of the unit in unit array.Second selection circuit is configured to the row of the selected unit that selection will program or wipe, and bottom electrode (or the row selected) ground connection of selected unit.Second selection circuit 508 would correspond to the bottom electrode that the voltage of program/erase voltage is applied to not have selected unit, and this only makes selectively unit be programmed or wipe.Sensing circuit 510 is configured to sense the curtage of selected unit, and reads the resistance states of selected unit.According to embodiment, equipment 500 can use different electric current configurations to be programmed or wipe.
Fig. 6 A illustrates the volt-ampere curve 600 of programming operation about resistive storage device (such as equipment 100) according to an embodiment of the invention.Equipment 100 remains turned-off, until till in switchable layer, bias voltage has reached the program voltage (such as, 4 volts) this point (reference 604) of filament formation, and equipment is opened.Switchable layer becomes resistor from insulator transition.When equipment 100 is opened when, equipment 100 point 604 at experience current peak (if or current signal be used for switching equipment, then stride across equipment decline voltage reduce rapidly).Current peak is I=V/R or 2 μ A in the present embodiment.It will be apparent to one skilled in the art that the embodiment along with equipment is changed by program voltage and the magnitude of current.Such as, according to embodiment, program voltage can change between 1-4 volt.
Once equipment 100 is opened, then equipment 100 shows as resistor in region 602 and region 603.Electric current is increased or decreased linearly along with the bias voltage applied.At region 602, equipment 100 stands too high Joule heat and too high electric current density, and this makes equipment be deteriorated and limits its life cycle.Owing to equipment has already turned on, thus the biasing at region 602 is unwanted.Once equipment is opened, and is preferably putting at 604 or is putting near 604, and bias voltage should stop.But, owing to two identical equipment can not be manufactured, thus it is difficult to arrange well the time of programming operation.Each equipment has slight feature difference.Additionally, due to same equipment stands the program/erase cycle repeatedly, even if thus the feature of same equipment be likely to change over.
Result is, program/erase voltage is typically to have preset some overdrive voltages, to guarantee the program/erase of equipment.If this overdrive voltage can be limited, then persistency or the life cycle of equipment can increase.In other words, once form filament at filament region, then should close bias voltage and open equipment at point 604.
In one embodiment, the change of the electric current being flow through equipment by use replaces distributing predetermined program voltage (or erasing voltage), controls the programming operation of equipment 100.A kind of method is if the time dependent rate of change of electric current is equal to or more than predetermined value, then close bias voltage.Another kind of method is if electric current equals to or more than predetermined value with the rate of change of change in voltage, then close bias voltage.These methods can be implemented below.
In one embodiment, bias voltage is applied to equipment 100.The electric current of the equipment that flows through is measured while bias voltage is applied to equipment.Bias voltage increases linearly as a function of time.By tested electric current compared with the predetermined value being confirmed as being suitable for forming filament in the switchable layer of equipment 100.If electric current reaches predetermined value, then bias voltage is stopped.Or, bias voltage can be applied in slightly long-time, to guarantee that equipment 100 has been opened before cutting off bias voltage.
In another embodiment, the potential pulse (or bias voltage pulse) that multiple amplitudes increase is applied to equipment 100.While potential pulse is applied to equipment 100, measure streaming current in device 100.Relatively the rate of change of electric current be confirmed as the predetermined value that is suitable for forming filament in the switchable layer of equipment 100.Potential pulse is applied to equipment 100, until the rate of change of electric current is equal to or more than predetermined value.The resistance value of measurement equipment 100.If resistance value is less than predetermined resistance, then stops potential pulse or stop being applied to equipment, and terminate programming operation.On the other hand, if resistance value is more than predetermined resistance, then potential pulse is applied until resistance value becomes less than predetermined resistance.Or, after resistance value becomes less than predetermined resistance, another potential pulse can be applied, to guarantee that equipment has been opened.
In yet another embodiment, predetermined voltage is applied to equipment 100 in predetermined time period.In predetermined time period, measure the electric current rate over time in equipment 100.If the rate of change of electric current is less than the predetermined value being confirmed as being suitable for forming filament in switchable layer, then predetermined voltage is continually applied to equipment 100.If the rate of change of electric current equals to or more than predetermined value, then stop applying predetermined voltage.
Fig. 6 B illustrates the volt-ampere curve 650 in the programmed and erased cycle of non-volatile memory device (such as, equipment 100) according to an embodiment of the invention.Curve 650 is in the way of the most identical with programming operation, it is shown that erasing operating function.Main difference is that use negative pressure as erasing voltage, to take the filament formed in the filament region of the switchable layer of equipment 100 away.
Fig. 7 illustrates the non-volatile memory device 700 including the control circuit 702 for programming resistive unit 750 according to an embodiment of the invention.As just schematically, programming operation described herein uses linearly increasing bias voltage.It is also possible, however, to use potential pulse or other programmed methods.
Resistive unit 750 includes one or more resistive.An embodiment, unit cell 750 is the unit array with multiple resistive.These units can be crossed array, NAND configuration, NOR configuration or another configuration.For illustrating easily, unit cell 750 is described as single resistive.It will be appreciated by those skilled in the art that control circuit 702 can be implemented with other circuit (such as, the circuit in Fig. 5) being used together with the unit array with multiple unit.
Control circuit 702 includes electric circuit inspection unit 710 and bias voltage applying unit 720, this electric circuit inspection unit 710 flows through the electric current of unit cell 750 for detection, this bias voltage applying unit 720 is for the result according to current detecting, in response to setting signal SET and reset signal RET, bias voltage is applied to unit cell 720.
Bias voltage applying unit 720 includes control signal generator 722, voltage transmitter 724, comparator 726 and bias voltage applicator 728.
Control signal generator 722 is configured to receive setting signal SET, to start programming operation and reset signal RET, to terminate programming operation.In one embodiment, control signal generator 722 produces in response to the first and second enable signal Q setting signal SETbWith Q and in response to the first and second anergy signal Q of the reset signal RST fed back from electric current retrieval unit 710bAnd Q.In one embodiment, control signal generator 722 is trigger.
Voltage transmitter 724 output and corresponding for the input voltage V1 voltage V2 being input to this voltage transmitter 724.Voltage transmitter includes transmission gate, and this transmission gate includes PMOS transistor P1, nmos pass transistor N1 and includes the drop-down unit of nmos pass transistor N2.According to the first control signal Q received from control signal generatorbIt is coupled in the primary nodal point for receiving input voltage V1 and between the secondary nodal point of output voltage V2 with the second control signal Q, PMOS transistor P1 and nmos pass transistor N1.When starting programming operation, open PMOS transistor P1 and nmos pass transistor N1, to obtain reflecting the voltage V2 of input voltage V1.At the end of programming operation, close PMOS transistor P1 and nmos pass transistor N1, to disconnect the relation of input voltage V1 and input voltage V2.Nmos pass transistor N2 is coupled between secondary nodal point and ground voltage terminal, and is configured to its gate terminal and receives the second anergy signal Q, and voltage V2 is pulled down to ground voltage, to terminate programming operation.
Comparator 726 receives voltage V2 in its first input, and receives bias voltage in its second input, and exports comparison signal COM.Bias voltage is applied to unit cell with the voltage being programmed it.In one embodiment, comparator 726 includes difference amplifier, to detect the voltage difference between two input nodes, and amplifies this voltage difference.Comparator 726 can include difference amplifier or have the operational amplifier of difference amplifier feature.
Bias voltage, in response to the comparison signal COM from comparator 726, is fed to unit cell by bias voltage applicator 728.In one embodiment, bias voltage applicator 728 includes the nmos pass transistor N3 being coupled between current detecting unit 710 and unit cell 750.The gate terminal of nmos pass transistor N3 is configured to receive comparison signal COM.
Current detecting unit 710 measures the magnitude of current flowing through unit cell during programming operation, and according to measured magnitude of current output reset signal RST.When measured electric current reaches program current, i.e. when unit cell 750 is opened, enable reset signal RST.In the present embodiment, current detecting unit 710 includes current supply unit 712, and this current supply unit 712 includes PMOS transistor P2, P3 and resistor R1.PMOS transistor P2 of current supply unit and the gate terminal of P3 are commonly coupled to drain electrode end and the drain electrode end of PMOSP2 of the nmos pass transistor N3 of program voltage applicator.The source terminal of PMOS transistor P2 and P3 is coupled to supply voltage.The drain electrode end of POMSP2 is coupled to the drain electrode end of nmos pass transistor N3 and also is coupled to the gate terminal of PMOS transistor P2 and P3.The drain electrode end of PMOSP3 is coupled to node ND2, is used for exporting reset signal RST and carrys out control signal generator 722.One end of resistor R1 is coupled to the drain electrode end of PMOS transistor P3, i.e. node ND2, and another end is coupled to ground.When opening resistor R1, resistor R1 is provided with the resistance being substantially the same with unit cell 750, and this makes reflection at node ND2 flow through the electric current of unit cell 750.
Fig. 8 illustrates the oscillogram of circuit 702 according to an embodiment of the invention.Input voltage V1 is set to rise to 3V, exceedes the 2V of program voltage.
It is imported into control signal generator 722 along with setting signal SET, starts programming operation.The output of control signal generator enables signal QbAnd Q.Enable signal QbIt is that logic high the gate terminal being applied to nmos pass transistor N1 are to open it.Enable signal Q to be logic low and be applied to PMOS transistor P1 and the gate terminal of nmos pass transistor N2.Open PMOS transistor P1 and close nmos pass transistor N2.
When programming operation starts, input voltage V1 it is applied to voltage transmitter 724 and is gradually increasing, such as, rising to 3V from 0V.Enable signal QbWith Q turn on PMOS transistor P1 and nmos pass transistor N1, with to conductive path provide input voltage V1.The voltage V2 that voltage transmitter output is corresponding with input voltage V1.Owing to the nmos pass transistor N2 signal Q that is enabled closes, thus output voltage V2 is applied to an input node of comparator 726.
The voltage of output voltage V2 reflection input voltage V1 raises.This voltage increased of voltage V2 increases the voltage difference between itself and the bias voltage V3 of another node of being input to comparator 726.Increasing the voltage difference between V2 and V3 causes comparator 726 output to increase the comparison signal COM of voltage.Comparison signal COM is applied to nmos pass transistor N3(or program voltage applicator 728) gate terminal.
Open program voltage applicator 728 bias voltage to be applied to unit of cells (top electrodes of such as, selected resistive).Bias voltage increases along with the increase of the voltage of comparison signal COM.That is, the rising of bias voltage reflection input voltage V1.Initially, unit of cells keeps high resistance state and stops electric current to flow through this unit of cells.Therefore, at output node ND2, it is not detected by electric current.When bias voltage reaches 2V, when i.e. reaching program voltage, unit of cells is converted into low resistance state (that is, being converted into resistor) and allows electric current to flow through this unit of cells.The big change (di/dt) of current spike or electric current is detected and is applied to control signal generator 722 as reset signal RST at output node ND2.
When receiving reset signal RST, control signal generator 722 exports anergy control signal Qb of logic low and anergy control signal Q of logic high, to close nmos pass transistor N1 and PMOS transistor P1.The conductive path opened in advance for input voltage V1 becomes closing.Although input voltage V1 continuously rises to 3 volts, but owing to conductive path is closed, thus the bias voltage being applied to unit of cells is unaffected.
Anergy control signal Q also opens nmos pass transistor N2 and voltage V2 pulled down to ground voltage.Comparator 726 in turn exports the comparison signal COM closing nmos pass transistor N3.Therefore, once unit of cells is the most programmed and stands the least overdrive voltage, then unit of cells stops receiving electric current.Therefore many non-essential unnecessary Joule heats are avoided.Unit of cells keeps programming state until receiving erasing voltage.Erasing operation substantially runs in the way of identical with above-mentioned programming operation.One difference should be to apply negative bias voltage to replace positive bias voltage.
Although Fig. 8 show voltage level in time and with climbing increase input voltage V1 and bias voltage V2, but can use in time and the potential pulse increased or additive method perform this programming operation.
According to embodiments of the invention, stop momently after reaching program voltage due to bias voltage and equipment has been opened (such as, at point 604 in fig. 6 or near putting 604), thus equipment 100 stands the least unnecessary Joule heat and improves the persistency of equipment significantly.
Have been described with substantial amounts of embodiment.It will be understood, however, that without departing from the spirit and scope of the present invention, it can be carried out various amendment.Such as, according to embodiment, can overturn the order of layer on substrate, wherein top electrodes is arranged on below bottom electrode.Therefore, term " top " should not be taken to be limiting the relative position of the electrode that the side that the source electrode of the ion that offer forms filament is contrary with at it in a-Si structure is arranged with " bottom ".Therefore, other embodiment falls within the scope of the following claims.
Claims (15)
1., for the method programming resistive storage device, the method includes:
Bias voltage is applied to the first electrode of the resistive of described resistive storage device；
Measure and flow through the electric current of described resistive, wherein, measure described electric current and include detecting electric current in time or the rate of change of voltage；And
When measured electric current is equal to or more than predetermined value, then start termination procedure to stop applying this bias voltage.
Method the most according to claim 1, wherein, described resistive storage device includes:
Top electrodes；
Switching device；And
Bottom electrode.
Method the most according to claim 2, wherein, described resistive storage device farther includes:
Metal oxide materials, this metal oxide materials is polycrystal and has crystal boundary；And
Conductive filament structure, is included in described crystal boundary the one or more Lacking oxygen or metallic voids formed.
Method the most according to claim 1, wherein, after have passed through the time delay of restriction, completes described termination procedure after starting described termination procedure.
5. the method forming conductive filament structure in switching equipment, described method includes:
The resistive switching equipment including top electrodes, switching device and bottom electrode is set；
In predetermined time period, predetermined voltage is applied to described resistive switching equipment；
Measure the rate of change over time of the electric current in described resistive switching equipment during described predetermined time period；
When the described rate of change of described electric current is more than the first limit value, then starts termination procedure and apply described predetermined voltage with stopping, and
When the described rate of change of described electric current is less than the second limit value, then continue to described predetermined voltage,
Wherein, when described predetermined voltage is applied to described resistive switching equipment, conductive filament structure is formed in described switching device.
Method the most according to claim 5, after have passed through the time delay of restriction, terminates described termination procedure after starting described termination.
Method the most according to claim 5, wherein, the rate of change measuring described electric current includes measuring the resistance value of described resistive switching equipment.
8. the method forming conductive filament structure in switching equipment, described method includes:
The resistive switching equipment including top electrodes, switching device and bottom electrode is set；
In predetermined time period, scheduled current is applied to described resistive switching equipment；
Measure the voltage rate over time crossing over described resistive switching equipment in described predetermined time period；
When crossing over the rate of change of voltage of described resistive switching equipment more than the first limit value, then start termination procedure and apply described scheduled current with stopping, and
When crossing over the rate of change of voltage of described resistive switching equipment less than the second limit value, then continue to described scheduled current,
Wherein, when described electric current is applied to described resistive switching equipment, conductive filament structure is formed in described switching device.
Method the most according to claim 8, after further including at the time delay that have passed through restriction after starting termination procedure, completes described termination procedure.
Method the most according to claim 8, wherein, applies described scheduled current and includes applying current impulse and to increase described scheduled current linearly as a function of time.
11. methods according to claim 8, wherein, the rate of change of the voltage measuring the described resistive switching equipment of leap includes the resistance value measuring described resistive switching equipment.
12. 1 kinds of circuit being used for programming resistive storage device, this circuit includes:
For bias voltage being applied to the device of the first electrode of the resistive of the resistive storage device of both-end；
For measuring the device of electric current flowing through described resistive, wherein, include for detecting electric current in time or the device of rate of change of voltage for measuring the device of described electric current；And
When measured electric current is equal to or more than predetermined value then for starting termination procedure to stop applying the device of described bias voltage.
13. circuit according to claim 12, wherein, the resistive storage device of described both-end includes:
Top electrodes；
Switching device；And
Bottom electrode.
14. circuit according to claim 13, the resistive storage device of wherein said both-end farther includes:
Metal oxide materials, this metal oxide materials is polycrystal and has crystal boundary；And
Conductive filament structure, is included in described crystal boundary the one or more Lacking oxygen or metallic voids formed.
15. circuit according to claim 12, terminate the device of described termination procedure after further including at the time delay that have passed through restriction after starting described termination procedure.
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| US12/815,369 US8274812B2 (en) | 2010-06-14 | 2010-06-14 | Write and erase scheme for resistive memory device |
| PCT/US2011/040362 WO2011159705A2 (en) | 2010-06-14 | 2011-06-14 | Write and erase scheme for resistive memory device |
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| CN103069495A CN103069495A (en) | 2013-04-24 |
| CN103069495B true CN103069495B (en) | 2016-08-03 |
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| EP (1) | EP2580760A2 (en) |
| JP (1) | JP5969991B2 (en) |
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| US8351241B2 (en) | 2010-06-24 | 2013-01-08 | The Regents Of The University Of Michigan | Rectification element and method for resistive switching for non volatile memory device |
| US8502185B2 (en) | 2011-05-31 | 2013-08-06 | Crossbar, Inc. | Switching device having a non-linear element |
-
2010
- 2010-06-14 US US12/815,369 patent/US8274812B2/en active Active
-
2011
- 2011-06-14 EP EP11796307.4A patent/EP2580760A2/en not_active Withdrawn
- 2011-06-14 KR KR1020137000986A patent/KR102014944B1/en active IP Right Grant
- 2011-06-14 WO PCT/US2011/040362 patent/WO2011159705A2/en active Application Filing
- 2011-06-14 JP JP2013515455A patent/JP5969991B2/en active Active
- 2011-06-14 CN CN201180039621.5A patent/CN103069495B/en active Active
- 2011-06-14 DE DE112011101999T patent/DE112011101999T5/en not_active Withdrawn
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2012
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Also Published As
| Publication number | Publication date |
|---|---|
| US8274812B2 (en) | 2012-09-25 |
| US20110305066A1 (en) | 2011-12-15 |
| KR102014944B1 (en) | 2019-08-27 |
| KR20130139217A (en) | 2013-12-20 |
| EP2580760A2 (en) | 2013-04-17 |
| US20120320660A1 (en) | 2012-12-20 |
| DE112011101999T5 (en) | 2013-08-01 |
| JP2013537678A (en) | 2013-10-03 |
| WO2011159705A2 (en) | 2011-12-22 |
| WO2011159705A3 (en) | 2012-04-19 |
| CN103069495A (en) | 2013-04-24 |
| US8787069B2 (en) | 2014-07-22 |
| JP5969991B2 (en) | 2016-08-17 |
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