KR20170034290A - Weighting device, neural network, and operating method of the weighting device - Google Patents

Abstract

Disclosed are a weighting device capable of driving at low voltage and implementing a multi-level, a neural network, and an operating method thereof. The weighting device comprises: a switching layer capable of being switched in a high resistance state and a low resistance state according to voltage application; and a charge capture material layer for capturing or emitting a charge in accordance with the resistance state of the switching layer. The weighting device can be used for controlling a weighting value on the neural network.

Description

[0001] The present invention relates to a weighting device, a neural network, and a method of operating the weighting device,

The present disclosure relates to a weighting element, a neural network, and a method of operation of a weighting element capable of implementing multi-level weights.

There are hundreds of billions of neurons in the brain, and they are connected together to form neural networks. These neurons have synapses that can send and receive signals to and from different neurons, which can serve as learning and memory. The synapse refers to the junction between neurons and the junction of the posterior synaptic dendrites to which the signal is received and the pre-synaptic axon protrusion to which the signal is transmitted. In general, one neuron has synapses with thousands of other neurons. Development of neuromorphic network to simulate such biological neural networks is attempted. In the development of such a circuit, a device having characteristics similar to neural phenomena is required. A neural network using electronic computation of the existing Von Neuman structure is presented. The key element of this neural network is a weighting device, which has the function of accumulating information by repetitive input signals Device is required.

A weight device capable of driving at a low voltage and capable of implementing a multi-level, a neural network, and a method of operating a weight device.

The weighting device according to the present disclosure includes: a substrate; A source region electrically connected to the source region; a first channel region located between the source region and the common region; a second channel region located on the first channel region; A charge trapping material layer provided on the first gate insulating layer; a switching layer provided on the charge trapping material layer and capable of switching to a high resistance state and a low resistance state; Wherein the charge trapping material layer includes a first transistor facing the region adjacent to the first channel region in the shared region with the first gate insulating layer interposed therebetween; And a drain region electrically connected to the drain region, a second channel region located between the common region and the drain region, and a second channel region disposed on the second channel region. And a second transistor including a second gate insulating layer formed on the first gate insulating layer and a second gate electrode provided on the second gate insulating layer, the second transistor having the common region as a source.

The first transistor may further include a leakage preventing region disposed in contact with the source region on the substrate and forming a PN diode structure with the source region, and the source electrode may be in contact with the leakage preventing region.

The leakage preventing region may be surrounded by the source region other than an area in contact with the source electrode.

The first channel region and the second channel region may have conductivity opposite to each other.

The first transistor may further include a well surrounding the source region, the first channel region, and the common region in the substrate and having a conductivity opposite to the second channel region.

The first gate electrode and the source electrode may be electrically connected to each other.

And a boosting electrode facing the charge trapping material layer with the first gate insulating layer and the substrate interposed therebetween.

The switching layer may include a nanofilament material that can be switched to the low resistance state by forming a conductive nanofilament according to voltage application.

The switching layer may include a PN diode layer.

The method of claim 1, further comprising: applying a selection voltage to the second gate electrode to open the second channel region; Applying a write voltage to the drain electrode; And grounding the first gate electrode, wherein charge can flow into the charge trapping material layer through the first gate electrode by the write voltage to record information in the charge trapping material layer.

Alternatively, the second channel region may be opened by applying a selection voltage to the second gate electrode. Applying a erase voltage to the first gate electrode; And grounding the drain electrode, wherein the charge trapped in the charge trapping material layer is removed by the erase voltage to erase the information.

Alternatively, the second channel region may be opened by applying a selection voltage to the second gate electrode. Applying a read voltage to the source electrode; And And measuring the measured current at the drain electrode to read the amount of charge trapped in the charge trapping material layer.

The step of applying the write voltage may include applying a pulse voltage to the drain electrode to reflect the weight, and the weighting may be adjusted by applying the pulse voltage.

The step of applying the erase voltage may include applying a pulse voltage to the first gate electrode to reflect the weight, and the weighting may be adjusted by applying the pulse voltage.

The neural network according to the present disclosure A plurality of weighting elements described above; And a plurality of neuron transistors for selectively switching a gate voltage applied to the plurality of weight elements.

Wherein the plurality of neuron transistors are two-dimensionally arranged, A drain electrode of the plurality of neuron transistors being connected to a first gate electrode of the plurality of weight elements and connected to a gate electrode of a neuron transistor located in the same column to apply a selection voltage; And And an input line connected to the source electrode of the neuron transistor located in the same row to apply the input voltage.

The plurality of weight elements may be arranged one-dimensionally or two-dimensionally.

In the method of operating a neural network according to the present disclosure, input information input through the plurality of neuron transistors and output information output through the plurality of weight elements are predetermined, and a weight value of the neural network corresponding thereto is determined May be supervised learning.

Alternatively, it may be an unsupervised learning method in which the weight value of the neural network is autonomously determined according to input information input through the neuron transistor.

The weighting device according to another embodiment includes a third transistor having a third gate electrode, a first electrode, and a second electrode; A fourth transistor sharing the third transistor and the second electrode, the fourth transistor including a fourth gate electrode and a third electrode; A fifth transistor having a fifth gate electrode, a fourth electrode, and a common region as a drain; A sixth transistor having a sixth gate electrode, a fifth electrode and serving as the source region; A switching layer formed on the first electrode and the third electrode, the switching layer being switchable between a high resistance state and a low resistance state; A charge trapping material layer located on the switching layer, the charge trapping material layer capturing or discharging charge according to a resistance state of the switching layer; And an interconnect interconnecting the charge trapping material layer and the sixth gate electrode.

According to the disclosed embodiments, a weight element having multi-level characteristics can be implemented. According to the disclosed embodiments, it is possible to implement a weighting device which can be operated at a low voltage.

According to the disclosed embodiments, the 4 terminal weight element can perform the operations of read, write, and erase.

According to the disclosed embodiments, the 3-terminal weight element is a modification of the 4-terminal weight element and can prevent current leakage to the source electrode.

According to the disclosed embodiments, the 6 terminal weight element may have a relatively large multilevel characteristic.

And may be utilized in a neural network through a connection between weighting elements in accordance with the disclosed embodiments.

1 is a cross-sectional view illustrating a weight device according to one embodiment.
2 is a cross-sectional view illustrating a write operation of the weight element of FIG.
3 is a cross-sectional view showing the erasing operation of the weight element of FIG.
4A to 4C are cross-sectional views illustrating the read operation of the weighting device of FIG.
5 is a cross-sectional view showing a weight device according to another embodiment.
6 is a cross-sectional view showing a weighting device according to another embodiment.
7 is a cross-sectional view showing a weighting device according to another embodiment.
8 is a cross-sectional view showing a write operation of the weight element of FIG.
9 is a cross-sectional view showing the erasing operation of the weighting element of FIG.
FIGS. 10A and 10B are diagrams showing an operation method for adjusting a weight value of a weight element.
11 is a cross-sectional view showing a weighting device according to another embodiment.
12 is a cross-sectional view showing a weighting device according to another embodiment.
13 is a cross-sectional view showing a weighting device according to another embodiment.
14 is a graph showing a current curve of the PN diode layer according to the applied voltage according to FIG.
15A to 15D are diagrams schematically showing another weighting element and a method of operating the same.
16 is a diagram schematically showing the principle of a neural network.
17A to 17C are schematic diagrams showing a method of driving a weight element on a neural network.
18A to 18C schematically illustrate the operation of a neural network composed of a plurality of columns of synapses and a single row of perceptrons.
19 is a diagram for learning using a neural network.
20 is a graph relating to the control learning.
21 is a graph relating to uncontrolled learning.

Brief Description of the Drawings The advantages and features of the present invention, and how to accomplish them, will become apparent with reference to the embodiments described hereinafter with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification, and the size and thickness of each element in the drawings may be exaggerated for clarity of explanation. The description of the same reference numerals can be omitted within the overlapping range.

The terms used in this specification will be briefly described and the present invention will be described in detail.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. Also, in certain cases, there may be a term selected arbitrarily by the applicant, in which case the meaning thereof will be described in detail in the description of the corresponding invention. Therefore, the term used in the present invention should be defined based on the meaning of the term, not on the name of a simple term, but on the entire contents of the present invention.

When an element is referred to as "including" an element throughout the specification, it is to be understood that the element may include other elements, without departing from the spirit or scope of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. In order to clearly explain the present invention in the drawings, parts not related to the description will be omitted.

1 is a cross-sectional view illustrating a weight device according to an embodiment of the present invention. The weighting device according to the present embodiment can be understood as a weighting device having four terminals. In neuroscience or computer science, weights refer to strength or strength of connections between two nodes. Particularly, in a neural network, the weight may mean the intensity of a signal transmitted to a plurality of neurons connected to one neuron. Mathematically, when the input value in the pre-neuron is x, the output value in the post-neuron is y, and the weight matrix value of the pre-neuron and post-neuron is w _ij , x, y, w _ij The following equation can be established.

 The following Equation 1 can be established.

Equation 1 means that the sum of the product of the input value x of the pre-neurons and the weight w _ij is the output value y. Thus, when specific input information is applied in a complex neural network, The output value to be transmitted to the post-neuron may be changed according to the corresponding weight value. This is similar to the neurotransmission process of living organisms. Electric pulse signals generated in the pre-neurons of living organisms reach the synapses and cause chemical processes. The neurotransmitters that are formed through the chemical process are transferred to post-neurons. The amount of neurotransmitter material delivered at this time determines whether the post-neuron will again generate an electrical pulse signal, and thus the amount of neurotransmitter material may correspond to the weight _wij . The weighting element may be a device that constitutes a neural network that simulates a real neural network, and may be a device capable of storing and reading the weight value _wij in a multi-level memory. The weighting device may have a transistor structure and may include a charge trapping material layer CL and a threshold voltage converting layer TL. The weighting element can receive a pulse signal as an input value. The charge trapping material layer CL can store various amounts of charge depending on the number of input pulse signals. The switching layer SL can prevent leakage of the amount of charge trapped in the layer of charge trapping material CL. Details will be described later.

Referring to FIG. 1, the weighting device according to the present embodiment may be provided on a substrate SUB. The substrate SUB may be a semiconductor substrate. For example, the substrate SUB may include group elements such as silicon (Si). The weighting element may include a first transistor TR1 and a second transistor TR2.

The first transistor TR1 includes a source electrode SE and a first gate electrode GE1 and may serve as a drain region of the common region SD. The first transistor TR1 may include a charge trapping layer M1 capable of storing a weight value. The charge trapping layer M1 includes a switching layer SL which can be switched to a high resistance state and a low resistance state in response to a voltage application and a charge trapping material SL for trapping or releasing charges depending on the resistance state of the switching layer SL. Layer CL.

The first transistor TR1 may include a first channel region C1. The first transistor TR1 may be a depletion type transistor. The first channel region C1 of the first transistor TR1 of the depletion type can have an open state in which electricity can flow through the first channel region C1 without applying a voltage to the first gate electrode GE1 have. The first channel region C1 may have a closed state in which electricity can not flow when a negative voltage is applied to the first channel region C1. For example, when a sufficient charge is accumulated in the layer of charge trapping material CL located on the first channel region C1, a negative voltage due to charge is applied to the first channel region C1, (C1) can be closed.

The second transistor TR2 includes the second gate electrode GE2 and the drain electrode DE, and can use the common region SD as a source. The first transistor TR1 may serve as a drain region and the second transistor TR2 may serve as a source region SD. The substrate SUB may include a source region S1 and a common region SD which are spaced apart from each other. The first channel region C1 may be provided between the source region S1 and the common region SD.

 The second transistor TR2 may include a second channel region C2. The second channel region C2 may be provided between the common region SD and the drain region D1. The second channel region C2 may be an enhancement type. The second channel region C2 of the second transistor of increased type can have an open state in which electricity can flow through the second channel region C2 when a voltage is applied to the second gate electrode GE2. The second channel region C2 may have a closed state in which electricity can not flow through the second channel region C2 unless a voltage is applied.

A gate oxide layer GO may be provided on the substrate SUB. The gate insulating layer GO can be formed by oxidizing the surface of the substrate SUB. For example, if the substrate SUB includes silicon, the gate insulating layer GO may be formed of silicon oxide. The gate insulating layer GO may have a role of a buffer layer. The gate insulating layer GO may serve as an insulating layer for insulating a channel region from each gate electrode of the first transistor TR1 and the second transistor TR2. For example, the gate insulating layer GO may serve as a first gate insulating layer GO1 for insulating the first channel region C1 of the first transistor TR1 from the charge trapping layer M1 . For example, the gate insulating layer GO may serve as a second gate insulating layer GO2 for insulating the second channel region C2 of the second transistor TR2 from the second gate electrode GE2 The weight element 100 formed on the substrate SUB may be of NMOS type or PMOS type. For example, the NMOS-type weight element 100 may include a substrate SUB doped with a p-type dopant, a source region S1 doped with an n-type dopant, a common region SD, and a drain region D1 have. The PMOS type weight element can be doped with a dopant having conductivity opposite to that of the NMOS type described above. The NMOS type and the PMOS type have only the opposite operation method, and the technical characteristics are not different. Therefore, although the NMOS type weight element is disclosed in the present embodiment, the present invention is not limited thereto and may include a PMOS type. The weighting device may also include an N-well, which is a well formed of an n-type dopant, or a P-well, which is a well formed of a p-type dopant.

The charge trapping layer M1 includes a charge trap layer CL formed on a portion of the first channel region C1 and the interface region SD adjacent to the first channel region C1, And a switching layer SL formed on the trapping material layer CL.

A part of the surface of the charge trapping material layer CL may face a part of the interface region SD and the first gate insulating layer GO1. Details will be described later with reference to Fig.

The material constituting the charge trapping material layer CL may include, for example, silicon nitride (Si _x N _y ) or polycrystalline silicon. Alternatively, the charge trapping material layer CL may be formed of a metal such as tungsten, molybdenum, cobalt, nickel, platinum, rhodium, palladium and iridium, a mixture thereof, or an alloy thereof. Alternatively, the charge trapping material layer CL may be formed of a material selected from the group consisting of silicon, germanium, a mixture of silicon and germanium, a group III-V compound (a combination of Al, Ga, In and V of Group III, P, (A combination of O, S, Se, and Te of Group VI of Zn, Cd, Hg and Group VI). Alternatively, the charge trapping material layer CL may be formed of an insulator having a high trapping density for charges, such as an aluminum oxide film (Al ₂ O ₃ ), a hafnium oxide film (HfO), a hafnium aluminum oxide film (HfAlO), a hafnium silicon oxide film (HfSiO) As shown in FIG.

The maximum amount of charge that can be stored in the charge trapping material layer CL may be proportional to the volume of the charge trapping material layer CL. The charge trapping material layer CL can store binary information according to whether the charge is stored or not. For example, you can see 1 when the charge is stored and 0 when it is not, which allows you to store the digital signal. Further, it is possible to have a multi-level weight value capable of storing a plurality of information in stages in accordance with the stored charge amount. For example, assuming that the charge is stored in the charge trapping material layer CL at a maximum of 100%, it is assumed that 0 is stored when the charge is not stored, 1 is stored when the charge is 25%, and 50% 2, the charge is 75% stored as 3, and the charge is stored as 100%. One such weighting element can be regarded as storing 4 bits of information. The finer the division of the stored charge, the more weights can be stored in one device, but the more errors can occur. The total amount of charge storable in the charge trapping material layer CL and the volume of the charge trapping material layer CL may be proportional to each other. Therefore, as the volume of the charge trapping material layer CL increases, more multi-level weighting can be realized. Since the multilevel is determined according to the amount of charge trapped in the charge trapping material layer CL, the charge trapping layer M1 has a non-volatility such that even when no voltage is applied to the charge trapping material layer CL, And a switching layer (SL).

The switching layer SL may have a variable resistance material property in which the resistance varies depending on the voltage applied to the switching layer SL. The resistance of the switching layer SL is divided into a high-resistance state and a low-resistance state, and can be switched according to an applied voltage. For example, the magnitude of the resistance of the switching layer SL may vary nonlinearly depending on the applied voltage, and when the specific voltage or higher is applied, the resistance value may be nonlinearly lowered. The resistance state of the switching layer SL when the voltage is not applied to the switching layer SL or when a voltage smaller than the specific voltage is applied is regarded as a high resistance state. Further, a voltage higher than the above-mentioned specific voltage is applied to the switching layer SL, and the resistance state when the magnitude of the resistance of the switching layer SL is non-linearly reduced can be regarded as a low resistance state. This particular voltage may be referred to as a threshold switching voltage. In addition, the weighting device according to the present embodiment can store charges in the charge trapping material layer CL without using the tunneling method of charges, so that deterioration of the interface state due to repeated use of the device can be prevented.

The switching layer SL may be formed of a threshold voltage conversion material. The threshold voltage conversion material is a material that maintains a high resistance state at normal times, changes to a low resistance state only when a voltage equal to or higher than a threshold voltage inherent to the threshold voltage conversion material is applied, and is reduced to a high resistance state when the applied voltage is removed . The switching layer SL made of such a material blocks charge transfer between the first gate electrode GE1 and the charge trapping material layer CL in a high resistance state in which no voltage is applied, The charge transfer between the first gate electrode GE1 and the charge trapping material layer CL is made possible in the resistance state.

The threshold voltage conversion material may comprise, for example, a chalcogenide-based material or a transition metal oxide. The chalcogenide-based material may include at least one transition metal selected from Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc and Re and at least one chalcogen ) ≪ / RTI > elements. The transition metal oxide may be, for example, Ti oxide, Ta oxide, Ni oxide, Zn oxide, W oxide, Co oxide, Nb oxide, TiNi oxide, LiNi oxide, InZn oxide, V oxide, SrZr oxide, SrTi oxide, A Fe oxide, a Cu oxide, a Hf oxide, a Zr oxide, an Al oxide, and a mixture thereof.

The switching layer SL may comprise a nano-filamentary material having a low resistance state formed by nano-filaments. Details will be described later with reference to FIG.

The switching layer SL may be formed of a PN diode. Details will be described later with reference to FIG.

The weighting device according to the present embodiment may have four terminals. The operation of the weight elements can be controlled through each terminal. Such an electrode may include a source electrode SE, a first gate electrode GE1, a second gate electrode GE2, and a drain electrode DE. The source electrode SE is connected to the source region S1. And the drain electrode DE is connected to the drain region D1. The meaning of 'connection' may include the meaning of electrical contact. The electrode may be made of a material having high electrical conductivity, for example, Pd, Pt, Ru, Au, Ag, Mo, Mg, Al, W, Ti, Ir, Ni, Cr, Nd or Cu. In addition, graphene, or a transparent conductive metal oxide such as ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum zinc oxide), or GZO (gallium zinc oxide) may be used.

A voltage can be applied to each electrode of the 4 terminal weight element to operate the weight element. The operation of each electrode will be described below. Hereinafter, the first channel region C1 is assumed to be a depletion type and the second channel region C2 is assumed to be an increase type, but the present invention is not limited thereto. The first channel region C1 may be a depletion type or an augment type, and the second channel region C2 may be a depletion type or an augment type. Whether the first channel region C1 and the second channel region C2 are a depletion mode or an augmentation type may change the operation method of the weight device, but may not change the characteristics of the weight device.

The source electrode SE may be associated with a read operation. When a read voltage is applied to the source electrode SE, a sensing current may flow through the first channel region C1. The magnitude of the measurement current can be varied according to the amount of charge trapped in the layer of charge trapping material CL located on the first channel region C1. For example, when the holes of the first channel region C1 are attracted by the electric field due to the charge trapped in the layer of charge trapping material CL, the amount of current flowing along the first channel region C1 may decrease have. The greater the amount of charge trapped in the charge trapping material layer CL, the more the amount of current flowing along the first channel region C1 is further reduced. Therefore, the amount of charge trapped in the charge trapping material layer CL can be determined according to the magnitude of the measurement current. For example, the amount of charge trapped in the layer of charge trapping material CL can be measured from the amount of decrease in the measured current based on the value of the measured current when there is no trapped charge in the layer of charge trapping material CL .

The first gate electrode GE1 may be associated with a clearing operation. The erase voltage applied to the first gate electrode GE1 may be transferred to the common area SD through the second channel region C2. The erase voltage can be distributed to the switching layer (SL), the charge trapping material layer (CL) and the gate insulating layer (GO). When the voltage applied to the switching layer SL exceeds the threshold voltage, the charge trapping material layer CL can emit the charge. If the voltage applied to the switching layer SL does not exceed the threshold voltage, the trapped charge trapping material layer CL can not emit the charge.

The second gate electrode GE2 may be associated with the selection of the weight element. When a selection voltage higher than a certain level is applied to the second gate electrode GE2, the second channel region C2 of the second transistor TR2 can be opened. The second channel region C2 of the second transistor TR2 must be open in the write, erase, and erase operations of the weight element according to the present embodiment, so that the second gate electrode GE2 is applied with a selection voltage Whether or not to select a weighting element.

The drain electrode DE may be associated with a write operation. The drain electrode DE may be applied with a write voltage. The write voltage applied to the drain electrode DE can be distributed to the switching layer SL, the charge trapping material layer CL and the gate insulating layer GO. When the voltage distributed to the switching layer SL is equal to or higher than the threshold voltage, the charge trapping material layer CL can capture the charge. When the voltage distributed to the switching layer SL is lower than the threshold voltage, the charge trapping material layer CL can not capture the charge. As described above, the weighting device according to the present embodiment can have a multi-level memory function according to the amount of charge stored in the charge trapping material layer CL.

2 is a cross-sectional view illustrating a write operation of the weight element of FIG.

Referring to FIG. 2, the write voltage Vb is applied to the drain electrode DE of the weight element, the selection voltage Vw is applied to the second gate electrode GE2, and the first gate electrode GE1 can be grounded. The second channel region C2 is opened by the selection voltage Vw and the write voltage Vb applied to the drain electrode DE can be transferred to the common region SD. The write voltage Vb transferred to the common area SD may pass through the second channel region and there may be some voltage drop. Since a portion of the interface area SD faces a part of the surface of the charge trapping material layer CL, the write voltage Vb transferred to the common area can contribute to the electric field formed in the charge trapping material layer CL.

The voltage applied to the charge trapping material layer CL can be applied through a part of the interface area SD facing the charge trapping material layer CL. 2, the first upper surface 11, which is a part of the surface of the charge trapping material layer close to the common area SD, and the first lower surface 12, which is a region adjacent to the first channel region C1 in the common area SD, Can face each other. An electric field due to the write voltage Vb may be formed between the first upper surface 11 and the first lower surface 12. [ The first upper surface 11 and the first lower surface 12 facing each other can have a width sufficient to form an electric field between the interface region SD and the charge trapping material layer CL. For example, if the widths of the first upper surface 11 and the first lower surface 12 facing each other are excessively small, an electric field may not be sufficiently formed between the common area SD and the charge trapping material layer CL.

The first gate electrode GE1 is grounded so that the write voltage Vb can be distributed to the gate insulating layer GO of the first transistor TR1, the charge trapping layer M1 and the first gate electrode GE1. The voltage distribution can be distributed according to the voltage division law according to the resistance value of each layer. For example, the write voltage Vb may be divided by the voltage Vc applied to the charge trapping material layer CL and the voltage Vi applied to the gate insulating layer GO, which is the voltage Vt applied to the switching layer SL. For example, if the voltage Vt is larger than the threshold voltage Vth of the switching layer SL, the switching layer SL is switched to the low resistance state so that the charge trapping material layer CL can capture the charge. The amount of charge trapped by the charge trapping material layer CL can be determined according to the magnitude and duration of the voltage Vt applied to the switching layer SL.

The magnitude of the write voltage Vb may vary depending on the material, size and shape of the charge trapping material layer CL and the switching layer SL, and may be, for example, 0V to 10V. The weighting device according to the present embodiment can operate at a relatively low voltage, compared to the magnitude of the write voltage required in a weighting device of the floating gate type, from 15V to 20V.

FIG. 3 is a cross-sectional view illustrating a single erase operation of the weighting device of FIG. 1;

Referring to FIG. 3, the erase voltage Vw 'is applied to the first gate electrode GE1, the selection voltage Vw is applied to the second gate electrode GE2, and the drain electrode DE can be grounded. The second channel region C2 is opened by the selection voltage Vw and the erase voltage Vw 'is applied to the gate insulating layer GO of the first transistor TR1, the charge trapping layer M1 and the first gate electrode GE1 Lt; / RTI > In the erasing operation, an electric field opposite to the above-described writing operation is formed through a part of the interface area SD and a part of the surface of the charge trapping material layer CL.

 If the voltage Vt applied to the switching layer SL is larger than the threshold voltage Vth, the charge trapping material layer CL can emit the trapped charge. The magnitude of the erase voltage Vw 'can be changed depending on the material, size and shape of the charge trapping material layer CL and the switching layer SL, and may be, for example, 0V to 10V. The magnitude of the erase voltage Vw 'may be selected to be equal to the magnitude Vb of the write voltage described above. The weighting element according to the present embodiment can operate at a relatively low voltage as compared with the case where the magnitude of the erase voltage required in the weighting element of the floating gate type is between 15V and 20V.

4A to 4C are cross-sectional views illustrating the read operation of the weighting device of FIG.

As described above, since the first transistor (TR1 in FIG. 1) may be a depletion type, the first channel region C1 may be in an open state even if no voltage is applied. The larger the amount of charge trapped in the charge trapping material layer CL, the smaller the magnitude of the current passing through the first channel region C1. The greater the amount of charge trapped in the charge trapping material layer CL, the larger the resistance of the first channel region C1. The read voltage Vr may be applied to the source electrode SE. When the selection voltage Vw is applied to the second gate electrode GE2, the second channel region C2 can be opened.

The measurement current may flow through the first channel region C1 and the second channel region C2 through the drain electrode DE. The measured current corresponds to the amount of charge trapped in the layer of charge trapping material CL, and the amount of charge can correspond to the weight value of the weighting element. E.g,

In the case of FIG. 4A, since there is no charge stored in the charge trapping material layer CL, the measurement current Ia can flow relatively large. When the measurement current Ia is measured in this manner, it can be seen that the weight value 2 is stored in the weight element.

In the case of FIG. 4B, about half of the charges may be stored in the charge trapping material layer CL, and the measured current Ib may flow less than the measured current Ia. In this way, when the measurement current Ib is measured, it can be seen that the weight value 1 is stored in the weight element.

In the case of FIG. 4C, the charge trapping material layer CL may have a full charge stored therein, and the measured current Ic may be smaller than the measured current Ib. In this way, when the measurement current Ic is measured, it can be seen that the weight value 0 is stored in the weight element.

The weighting device according to the above-described example may store three kinds of multi-level weight values. However, it is needless to say that the present invention is not limited to these embodiments, and it is needless to say that the weight elements can have various multi-level weights depending on the volume and shape of the charge trapping material layer CL. Concrete determination of the weight value may be made from the measured current value measured by a galvanometer, a sensing analyzer, etc. connected to the drain electrode DE.

In the present embodiment, the measurement current is measured at the drain electrode DE to determine the weight value, but is not limited thereto. For example, since the amount of charge trapped in the layer of charge trapping material CL can change the degree of passing the current in the first channel region C1, it is sufficient to measure a criterion that can be quantitatively or qualitatively judged have. It may be difficult to judge the multilevel in details when the qualitative judgment is made, and the multilevel can be judged in detail when it is judged quantitatively. Any physical quantity, a measured current, a voltage, a resistance, or the like that can reflect characteristics of the first channel region C1 can be measured, and a specific measurement method is not limited.

The specific value of the read voltage Vr can be selected to be smaller than the write voltage Vb and the erase voltage Vw 'described above. For example, the read voltage can be selected from 0V to 4V. However, the read voltage is not limited to the above-described example, and the optimal value can be selected according to the material, size, and appearance of the weight device.

5 is a cross-sectional view showing a weight device according to another embodiment. The weighting device according to the present embodiment is substantially the same as the weighting device of the embodiment described with reference to Figs. 1 to 4 except that a boosting electrode BE is formed on the rear surface of the substrate of the weighting device. Therefore, overlapping description will be omitted, and only the boosting electrode BE will be described.

5, the position of the boosting electrode BE is located on the first channel region C1, and is separated from the region where the common region SD and the charge trapping material layer CL face each other, It can be positioned close to the region S1. The boosting electrode BE and the charge trapping material layer CL can face each other. For example, the second upper surface 21, which is a part of the charge trapping material layer CL near the source region S1, and the second lower surface 21, which is the surface where the boosting electrode BE contacts the substrate SUB, can do. 5, in the erase operation, a boosting voltage Vw 'equal to the erase voltage Vw' applied to the first gate electrode GE1 may be applied to the boosting electrode BE located on the opposite side of the substrate SUB . For example, the boosting voltage Vw 'applied to the boosting electrode BE is applied to the second lower surface 22 and can be canceled with the erase voltage Vw' applied to the second upper surface 21. This behavior can be called global self-boosting.

Since the boosting voltage Vw 'and the erase voltage Vw' are canceled each other, current leakage to the source electrode SE can be prevented. The boosting electrode BE may be positioned sufficiently far away from the interface region SD so that the boosting voltage V W 'applied to the boosting electrode BE does not affect the electric field near the common region SD have. For example, the second upper surface 21 and the first upper surface 11 may be sufficiently spaced. For example, the second lower surface 22 and the first lower surface 12 may be sufficiently spaced. 5, the electric field between the second upper surface 21 and the second lower surface 22 may not influence the electric field between the first upper surface 11 and the second lower surface 12.

6 is a cross-sectional view showing a weighting device according to another embodiment.

The weighting element according to the present embodiment is substantially the same as the weighting element of the embodiment described with reference to Figs. 1 to 4, except that it further includes the leakage preventing region S2. Therefore, redundant description will be omitted and differences will be mainly described.

Referring to Fig. 6, the weighting device according to the present embodiment may include a leakage preventing region S2 in contact with the source region S1. The leakage preventing region S2 can prevent current leakage from the first channel region C1 to the source electrode SE. The leakage preventing region S2 may have a conductivity opposite to that of the source region S1. The source electrode SE is formed on the leakage preventing region S2 and may not be in direct contact with the source region S1. For example, the leakage preventing region S2 may be surrounded by the source region S1 other than the surface in contact with the source electrode SE.

For example, in the NMOS type weight element, the source region S1 may have n-type conductivity, and the leakage preventing region S2 may have p-type conductivity. Since the leakage preventing region S2 and the source region S1 have the PN diode structure, leakage current flowing from the first channel region C1 to the source electrode SE can be prevented.

7 is a cross-sectional view illustrating a weight device according to another embodiment of the present invention. This embodiment can be understood as a weighting element having three terminals. The weighting device according to this embodiment is different from the weighting device of the embodiment described with reference to Figs. 1 to 4, except that the first gate electrode GE1 and the source electrode SE of the weighting device are electrically connected to each other. . Therefore, redundant description will be omitted and differences will be mainly described.

Referring to FIG. 7, the first gate electrode GE1 and the source electrode SE may be electrically connected to each other. . The source electrode SE and the first gate electrode GE1 of the weight element according to the present embodiment can function as one terminal. A neural network composed of three terminal structure weighting elements can have a smaller area than a neural network composed of weighting elements of a four terminal structure. The three terminal weight elements may be operated in a manner similar to the four terminal weight elements described above. The terminals of the three terminal weight elements are three of the first gate electrode GE1, the second gate electrode GE2, and the drain electrode DE connected to the source electrode SE.

8 is a diagram showing a write operation of the weighting element of FIG.

Referring to FIG. 8, the write voltage Vb is applied to the drain electrode DE of the weight element, the selection voltage Vw is applied to the second gate electrode GE2, and the first gate electrode GE1 can be grounded. The second channel region C2 is opened by the selection voltage Vw and the write voltage Vb applied to the drain electrode DE can be transferred to the common region SD.

Since a portion of the interface area SD faces a part of the surface of the charge trapping material layer CL, the write voltage Vb transferred to the common area can contribute to the electric field formed in the charge trapping material layer CL. The first gate electrode GE1 is grounded so that the write voltage Vb can be distributed to the gate insulating layer GO of the first transistor TR1, the charge trapping layer M1 and the first gate electrode GE1. The voltage distribution can be distributed according to the voltage division law according to the resistance value of each layer. The write operation mode of the 3-terminal weight element may be substantially the same as the write operation of the 4-terminal weight element.

FIG. 9 is a diagram showing a clearing operation of the weighting elements of FIG. 7. FIG.

Referring to FIG. 9, the erase voltage Vw 'is applied to the first gate electrode GE1, the selection voltage Vw is applied to the second gate electrode GE2, and the drain electrode DE can be grounded. The second channel region C2 is opened by the selection voltage Vw and the erase voltage Vw 'is applied to the gate insulating layer GO of the first transistor TR1, the charge trapping layer M1 and the first gate electrode GE1 Lt; / RTI > The erase operation method of the 3 terminal weight element may be substantially the same as the erase operation method of the 4 terminal weight element described above.

 Also, in the erasing operation of the 3-terminal weight element, since the first gate electrode GE1 and the source electrode SE are electrically connected, the erase voltage Vw 'can be transferred to the source region S1. The electric field formed by the erase voltage Vw 'transmitted through the source region and the erase voltage Vw' transmitted to the charge trapping layer M1 can be offset from each other. The operation of these three terminal weighting elements can be referred to as intrinsic self-boosting.

Referring to FIG. 9, the charge trapping material layer CL and the source region S1 can face each other with the gate insulating layer GO therebetween. For example, the third lower surface 32, which is a partial region close to the first channel region C1 of the source region S1, and the third upper surface 32a, which is a portion near the source region S1 of the charge trapping material layer CL 31 may face each other. For example, the erase voltage Vw 'may be transmitted to the third upper surface 31 and the erase voltage Vw' may be transmitted to the third lower surface 31, respectively, and the erase voltages Vw 'may cancel each other.

The electric field which is formed between the interface region SD and the charge trapping layer M1 and the electric field which is canceled each other at the portion of the source region S1 can be sufficiently separated. Therefore, the offset of the erase voltage Vw 'transferred to the source region S1 and the erase voltage Vw' transferred to the first gate electrode GE1 may not affect the operation of the weighting device. For example, the third upper surface 31 and the first upper surface 11 may be sufficiently spaced. For example, the third lower surface 32 and the first lower surface 12 may be sufficiently spaced. 9, the electric field between the third upper surface 31 and the second lower surface 32 may not affect the electric field between the first upper surface 11 and the second lower surface 12.

 The internal self-boosting weighting element does not require a separate boosting electrode (BE of FIG. 5) unlike the global self-boosting weighting element. Therefore, the internal self-boosting weighting device can have a simple structure compared to the weighting device of the global self-boosting method.

The 4-terminal weighting device can be operated by an internal self-boosting method only for the erase operation by connecting the source electrode SE and the first gate electrode GE1 by switching. In this case, leakage of current to the source electrode SE can be effectively prevented without a separate leakage preventing region (S2 in Fig. 6A) like the weighting element in Fig.

FIGS. 10A and 10B are diagrams showing an operation method for adjusting a weight value of a weight element. The weighting device according to the present embodiment may be applied with a pulse signal for adjusting the weight. The neural network to be described below may include a plurality of weighting elements and may reflect the weights to control the functional relationship between the input signal and the output signal.

The weighting element according to this embodiment is substantially the same as the weighting element of the embodiment described with reference to Figs. Therefore, the description of the redundant configuration of the weight elements is omitted. In addition, although the weighting element according to the present embodiment exemplifies a 3-terminal weight element, it is not limited thereto and may include the 4-terminal weight element described above.

Referring to FIG. 10A, in order to increase the weight of the weight element, the first gate electrode GE1 may be applied with a pulse voltage. Except for the pulse voltage being applied to the first gate electrode GE1, the same operation as the write operation of the weight element described above is omitted, and redundant description will be omitted. The weight increase amount of the weight element may be proportional to the number of pulse voltages applied to the first gate electrode GE1. The pulse voltage may have a magnitude greater than the write voltage described above. The holding time per pulse of the pulse voltage can be determined differently depending on the characteristics of the weight element. For example, the hold time per pulse may be determined differently depending on the material of the switching layer SL, and in particular, one pulse may be long enough to change the resistance state of the switching layer SL.

Referring to FIG. 10B, in order to reduce the weight of the weight element, the drain electrode DE may be applied with a pulse voltage. Except for the pulse voltage being applied to the drain electrode DE, the same operations as those of the above-described weight element erase operation are substantially the same and redundant explanations are omitted. The weight reduction amount of the weight element may be proportional to the number of pulse voltages applied to the drain electrode DE. The pulse voltage may have a magnitude greater than the erase voltage described above. As described above, the holding time per pulse of the pulse voltage can be determined differently depending on the characteristics of the weight element.

11 is a cross-sectional view showing a weighting device according to another embodiment. Referring to FIG. 11, the first channel region C1 and the second channel region C2 of the substrate SUB may have different conductivity. The structures of the first transistor TR1 and the second transistor TR2 except for the first channel region C1 and the second channel region C2 are the same as those described in FIGS. 1 to 4, do.

In the weighting device according to the present embodiment, the first transistor TR1 is a PMOS transistor located on the first channel region C1 having n-type conductivity, and the second transistor TR2 is a PMOS transistor located on the n- And may be an NMOS transistor located on the two-channel region C2. For example, the first transistor TR1 may be a PMOS formed on an N-well formed of an n-type dopant, and the second transistor TR2 may be formed on a substrate SUB doped with a p-type dopant NMOS.

For example, the source region S1 and the common region SD may be formed of a p-type dopant in an n-well. Therefore, the n-type well (N-well) surrounding the source region S1 and the source region S1 has a conductivity opposite to that of each other, so that a PN diode structure can be formed. The weighting device according to the present embodiment can prevent the reverse flow of current from the first channel region C1 to the source electrode SE. These embodiments are merely illustrative and not restrictive. For example, the first transistor TR1 may be an NMOS formed on a well formed of a p-type dopant, and the second transistor TR2 may be a PMOS formed on a substrate SUB doped with an n-type dopant. Alternatively, the first transistor TR1 may be formed on the substrate SUB, and the second transistor TR2 may be formed on the well.

 12 is a cross-sectional view showing a weighting device according to another embodiment. Except for the material of the switching layer SL, the weighting element according to this embodiment is substantially the same as that of the weighting element of FIG. 11 described above, so a duplicate description will be omitted. Referring to FIG. 12, the switching layer SL may include a nanofilament material in which a low resistance state is formed by nanofilaments.

The nanofilament material may be a material in which nanofilaments having conductivity are formed when a voltage higher than a specific value unique to the material is applied. The nanofilament may refer to a conductive path formed by a voltage. When a voltage lower than a specific value is applied to a nanofilament material, a nanofilament is not formed, so that it is difficult to cause a current to flow relatively.

The nanofilament material may include nanofilaments such as TiO _x . For example, when a voltage is applied to a nanofilament material, TiOx or the like inside the nanofilament may form a nanofilament and form a low resistance state. Depending on the voltage applied to the nanofilament material, the number or morphology of the nanofilaments may vary from substance to substance. As a result, the resistance behavior of nanofilament materials may be different. When the switching layer (SL) is formed of a nanofilament material, the resistance switching time can be very fast in nano-seconds.

13 is a cross-sectional view showing a weighting device according to another embodiment. 14 is a graph showing a current curve of the PN diode layer according to the applied voltage according to FIG.

Referring to FIG. 13, the switching layer SL may include a PN diode layer including a P-type diode layer and an N-type diode layer. Except for the material of the switching layer SL, the weighting element according to this embodiment is substantially the same as that of the weighting element of FIG. 11 described above, so a duplicate description will be omitted. The PN diode layer may be formed by combining the above-described threshold voltage conversion material. The PN diode layer facilitates charging of the charge trapping layer M1 and effectively prevents discharging. The PN diode layer can be applied with a smaller write voltage than the erase voltage in comparison with other embodiments of the switching layer SL described above, thereby saving power.

Referring to FIG. 14, in the current curve with respect to the applied voltage of the PN diode layer, the positive bias voltage region A1 indicates a low resistance region in which a current can flow even when a weak voltage is applied, and a negative bias voltage region A2 represents a high resistance region in which no current flows even when a voltage is applied, and a breakdown in which the reverse bias voltage of the diode exceeds the threshold value due to the breakdown of the high resistance, Resistance region that can flow. The boundary voltage between the negative bias voltage region A2 and the breakdown voltage region A3 may be referred to as a breakdown voltage.

The operation of the PN diode layer of the weight element according to this embodiment will be described with reference to FIG. A part common to the above-described operation method of the weight element will be briefly described.

In the write operation of the weight element according to this embodiment, the write voltage is applied through the drain electrode DE to distribute the positive bias voltage to the PN diode layer. Since the PN diode layer is located in the positive bias voltage region A1 in Fig. 14, the charge trapping material layer CL can capture the charge.

In the erasing operation of the weighting device according to the present embodiment, the erase voltage is applied through the first gate electrode GE1 to distribute the negative bias voltage to the PN diode layer. The PN diode layer may be located in the negative bias voltage region A2 or the breakdown voltage region A3 in Fig. 14B. If the voltage applied to the PN diode layer is greater than the breakdown voltage, the PN diode layer is located in the breakdown voltage region A3, and the charge trapping material layer CL can emit the charge. When the magnitude of the voltage applied to the PN diode layer is less than the breakdown voltage, the PN diode layer is located in the negative bias voltage region A2, and the charge trapping material layer CL can not emit the charge.

15A to 15D are cross-sectional views schematically showing still another weighting element and a method of operation thereof. Referring to FIG. 15A, the weighting element according to the present embodiment may be a 6 terminal weight element including 4 transistors TR3, TR4, TR5 and TR6.

The weighting device according to this embodiment includes a third transistor TR3 including a third gate electrode GE3, a first electrode E1 and a second electrode E2, And a fourth transistor TR4 sharing a second electrode E2 and including a fourth gate electrode GE4 and a third electrode E3. The fifth transistor TR4 includes a fifth gate electrode GE5, a fourth electrode E4 And a sixth transistor TR6 including a fifth transistor TR5 having a sixth gate electrode GE6 and a fifth electrode E5.

The names of the third transistor TR3, the fourth transistor TR4, the fifth transistor TR5 and the sixth transistor TR6 are the same as those of the first transistor (TR1 in FIG. 1), the second transistor Of TR2).

The third transistor TR3 may drain the first interface area SD1 and the fourth transistor TR4 may be the first interface area SD1. The fifth transistor TR5 may drain the second interface area SD2 and the sixth transistor TR6 may be the source of the second interface area SD2.

The weighting device according to this embodiment may include a charge trapping layer M2 electrically connected to the first electrode E1 and the third electrode E3. The weighting device according to the present embodiment may include an interconnect (IC) connecting the charge trapping layer M2 and the sixth gate electrode GE6. The third gate electrode GE3, the second electrode E2, the fourth gate electrode GE4, the fourth electrode E4, the fifth gate electrode GE4, and the fourth gate electrode GE4, which control the operation of the weight device according to this embodiment, GE5), and the fifth electrode (E5).

In the weighting device according to the present embodiment, the charge trapping layer M2 may be disposed on the first electrode E1 and the third electrode E3. In the weighting device according to the above-described embodiment, the charge trapping layer (M1 in Fig. 1) was located on the first channel region (C1 in Fig. 1) of the transistor, and the cross-sectional area of the charge trapping layer Can be limited by the area of the first channel region (C1 in Fig. 1). As described above, since the volume of the charge trapping layer M2 can determine the magnitude of the multilevel, the cross-sectional area of the charge trapping layer M2 may have to be sufficiently wide so that the weighting element has a large multilevel of several tens or more. Thus, the charge trapping layer M2 may be disposed on the first electrode E1 and the third electrode E3, and may have a sufficient cross-sectional area without limiting the area of the first channel region (C1 in Fig. 1).

Referring to FIG. 15B, the write operation of the weight element according to the present embodiment will be described.

The write voltage Vb is applied to the second electrode E2 and the selection voltage Vw may be applied to either the third gate electrode GE3 or the fourth gate electrode GE4. The fourth electrode E4 may be grounded, and the fifth gate electrode GE5 may be applied with the selection voltage Vw. As described above, the write voltage Vb can be divided into the switching layer SL and the charge trapping material layer CL through voltage distribution. For example, in the case where the switching layer SL includes a PN diode layer, even if a small voltage is applied to the switching layer SL, the charge trapping material layer CL can capture charges passing through the PN diode layer have. For example, when the switching layer SL includes the above-described other material other than the PN diode layer, a voltage higher than the threshold voltage must be applied to change the resistance state of the switching layer SL, ) Can capture the charge.

The erasing operation of the weighting device according to the present embodiment will be described with reference to FIG. 15C. The second electrode E2 may be grounded and the selection voltage Vw may be applied to either the third gate electrode GE3 or the fourth gate electrode GE4. The erase voltage Vw 'may be applied to the fourth electrode E4, and the selection voltage Vw may be applied to the fifth gate electrode GE5. When the voltage applied to the switching layer SL exceeds the threshold voltage, the charge trapped in the layer of charge trapping material CL can escape to the first electrode E1 or the third electrode E3. For example, when the switching layer SL includes a PN diode layer, a voltage higher than the breakdown voltage must be applied to the switching layer SL, so that the charge trapping material layer CL can emit the charge. For example, when the switching layer SL includes the above-described other material other than the PN diode layer, a voltage higher than the threshold voltage must be applied to change the resistance state of the switching layer SL, ) Can discharge this charge.

Referring to FIG. 15D, a read operation of the weight element according to the present embodiment will be described.

The fifth voltage E5 may be applied with the read voltage Vr and the fifth gate electrode GE5 may be applied with the selection voltage Vw. The weight value can be read by measuring the intensity of the current flowing to the fourth electrode E4 as described above. The third transistor (TR3 of FIG. 15A), and the fourth transistor (TR4 of FIG. 15A) may not be applied with a separate voltage.

16 is a diagram schematically showing the principle of a neural network. A neural network may include at least one or more rows of hidden layers between an input layer and an output layer. In the input layer, the input information is input as an electric signal, and the output layer can output the output information as an electric signal. The hidden layer may be a sort of black box that determines the correlation between input information and output information. Hidden layers can implement nonlinear function relationships as well as linear functional relationships. The hidden layer may include a plurality of the above-described weight elements. The nonlinear function relationship implemented by the hidden layer can be determined by the weight value of a plurality of weight elements included in the hidden layer.

Hidden layers can be composed of multiple columns, and as the number of columns increases, complex nonlinear function relationships can be realized. A neural network including a plurality of hidden layers can be used for deep learning. Deep learning can mean a nonlinear learning method.

Hidden layers can include synapses and perceptrons. The synapse can refer to the connection between the neurons shown by dots. Perceptron can be a neural network that implements functional relationships by weighting information transmitted through synapses and synapses. That is, the weighting element described above may correspond to a perceptron. A plurality of transistors included in the input layer correspond to neurons of an actual neural network, and will be referred to as neuron transistors hereinafter.

17A to 17C are schematic diagrams showing a method of driving a weight element on a neural network. The neural network according to the present embodiment may be a schematic configuration including a neuron transistor and a perceptron composed of one weight element. The synapse may correspond to the connection between the drain of the neuron transistor and the gate electrode of the weighting device. For example, the neuron transistor can selectively switch the gate voltage applied to the weight element. In order for the neuron transistor and the weight element to transmit and receive electrical signals, the synapse must be activated, which can correspond to the activation of the channel region of the neuron transistor and the channel region of the weight element. FIG. 17A shows a method of increasing the weight, FIG. 17B shows a method of reducing the weight, and FIG. 17C shows a method of reading the weight.

17A and 17B, a synapse connecting the neuron transistor and the perceptron may be activated by applying a selection voltage Vw to the neuron and the weight element. Thereafter, the method of increasing or decreasing the weight value of the perceptron is substantially the same as the operation of the weight element described above, so that it is omitted.

Referring to FIG. 17C, the weight value of the perceptron can be confirmed. Since the synapse connecting the neuron transistor and the perceptron does not need to be activated, the selection voltage Vw can be applied only to the weight element without applying the selection voltage to the neuron transistor.

18A to 18C are diagrams schematically showing the operation of a neural network composed of a plurality of columns of neuron transistors and a single row of perceptrons.

Referring to FIG. 18A, a plurality of neuron transistors can be two-dimensionally arranged as (a * b). In a two-dimensional array of (a * b), a may be a number representing a row and b may be a number representing a column. For example, a transistor located at the top of the neural network is located in the first row, so a = 1, and a transistor located in the lower row may be a = 2. For example, the transistor located at the leftmost side of the neural network is located in the first column, so that b = 1, and the transistor located in the right column can be b = 2. For example, a transistor located at (1 * 1) may refer to a neuron transistor located in the first column of the first row relative to the upper left corner of the neural network.

The neuron transistors according to the present embodiment can be two-dimensionally arranged as (n * n). That is, n transistors may be arranged along a row and n transistors may be arranged along a row. These embodiments are for convenience of description and are not limited thereto.

The source electrodes of each neuron transistor located in the same row can be connected to each other to form an input line. 18A, in order to distinguish input lines for each row, input lines include W _D1 to W _Dn . An input signal may be applied to the input line.

Gate electrodes of each neuron transistor located in the same column can be connected to each other to constitute a selection line. Referring to FIG. 18A, the selection lines may be referred to as selection lines x ₁ to x _n in order to distinguish the selection lines for each column. A selection voltage can be applied to the selection line. When a selection voltage is applied to a specific selection line, all the transistors in the column can be selected. The selection may mean that the channel region of the transistor in the row is open.

The perceptron may include a plurality of weighting elements according to the above-described embodiments.

Referring to Fig. 18A, when the neuron transistors are two-dimensionally arranged as (n * n), the perceptron can be arranged one-dimensionally with n weight elements. For example, the drain electrode of each neuron transistor located in the same row may be electrically connected to the first gate electrode of the weight element located in the same row to form a synapse. As described above, the weight value of each weight device can be adjusted by applying a write voltage to the drain electrode of each weight device. The drain electrode of each weight element can be divided into input lines W _C1 to W _CN .

The second gate electrodes of the weight elements constituting the perceptron may be connected to each other to constitute a selection line. Referring to FIG. 18A, the selection line of the perceptron can be represented by y1. When the selection voltage Vw is applied to the selection line y1, all the weight elements of the column can be selected. The selection of the weighting element may mean that the second channel region C2 is in the open state. Details will be omitted here.

The neural network adjusts the voltages applied to the input lines W _D1 to W _{Dn , the} selection lines x ₁ to x _{n , the} input lines W _C1 to W _CN , and the selection line y ₁ to calculate the weights h 1 to hn of the weight elements included in the perceptron Can be adjusted.

Referring to FIG. 18B, the write and erase operations of the neural network will be examined. For example, the selection voltage Vw is applied to the selection line x2 and may not be applied to x1 and x3 to xn. Therefore, neuron transistors located in the second column can be selected. Since the selection line y1 is applied with the selection voltage Vw, the weight element connected to the selection line y1 can be activated. Thus, the synapse between the neuron transistor located on the selection line x2 and the weighting element located on the selection line y1 can be activated. For example, the input line W _C1 may be applied with the input line write voltage Vc1, and the input line W _D1 may be grounded. Charge can flow through the synapse between the neuron transistor located at (1 * 2) and the weight element located at the first row, and the weight h1 can be increased. For example, the input line W _Cn Is grounded and the input line W _Dn The erase voltage V _Dn may be applied. the weight hn can be reduced by discharging the charge through the synapse between the neuron transistor located at (n * 2) and the weighting element located at the n-th row.

 As described above, the pulse voltage can be applied to the write voltage and the pulse voltage can be applied to the erase voltage.

Referring to FIG. 18C, the read operation of the neural network will be examined. For example, the input line W _c1 may be applied with a read voltage V _R. The weight h1 can be read by measuring the measurement current flowing through the weight element located in the first row. For example, the input line W _cn may be applied with a read voltage V _R , and the resulting weight hn may be read. As described above, the weight value of the corresponding weighting element can be read from the current value measured through the signal reader (S / A) or the ammeter (not shown). The reading of the weights h1 to hn may be independent of the synapse activity with the neuron transistor, so that the selection voltage is not necessarily applied to the selection lines x1 to xn.

In the neural network according to Figs. 18A to 18C, the perceptron is composed of a single row, but is not limited thereto. The neural network may include a plurality of columns of perceptrons, and such neural networks may be used for deep running as described above.

19 is a diagram for learning using a neural network. Neural networks can be divided into continuous learning and discrete learning. The neural network using the weight elements described above can be used for discrete learning because it is a network using a limited number of weight elements.

Neural networks that include non-volatile weighting elements can be used for supervised learning and unsupervised learning. Control learning is a method of machine learning to derive a specific function from training data. The training data is defined input information and output information. In general, the input information is included in a vector form, and predetermined output information is set for each input information vector. Control learning refers to learning a neural network such that predetermined output information is obtained for such input information. In the present disclosure, a neural network can be learned through adjustment of weights. Classification means using a learned neural network to determine what kind of value a given input vector is.

Referring to Fig. 20, the classification can be judged from the relation of the output (x2) to the input (x1) to the controlled learning neural network. For example, the classification is based on a neural network that is learned to control the B output value for the A input value, inputs the unidentified input values C and D to the network, and checks whether the result corresponds to the B output value As shown in FIG. Referring to FIG. 20, the input values corresponding to the B output values are shown in a circle, and the input values not corresponding to the B output value are shown with a check mark. These circles and scissors values correspond to those classified according to whether they correspond to the controlled neural network.

Uncontrolled learning is a kind of machine learning in which the target value of the output information for input information is not given, unlike the control learning described above. An example of uncontrolled learning is clustering. Clustering means statistically analyzing output values for inputs of neural networks learned by uncontrolled learning and dividing them into groups.

Referring to FIG. 21, the cluster can be determined by determining the relationship of the output (x2) to the input (x1) to the uncontrolled learned neural network. For example, the output values according to the input values inputted to the uncontrolled learned neural network are compared, and the coordinates belonging to the similar range can be grouped into one cluster. Referring to FIG. 21, the coordinates of the input value and the output value are shown in a circle, and the cluster is indicated by a dotted line according to whether the input value and the output value are included in the similar range.

Up to now, exemplary embodiments of a weight element, a neural network, and a method of operating a weight element have been described and shown in the accompanying drawings to assist in understanding the present invention. It should be understood, however, that such embodiments are merely illustrative of the present invention and not limiting thereof. And it is to be understood that the invention is not limited to the details shown and described. Since various other modifications may occur to those of ordinary skill in the art.

SUB: substrate GO: gate insulating layer
C1: first channel region C2: second channel region
GE1: first gate electrode GE2: second gate electrode
CL: charge trapping material layer SL: switching layer
S1: Source area S2: Leakage prevention area
D1: drain region SD: common region
SE: source electrode DE: drain electrode
GE1: first gate electrode GE2: second gate electrode
M1: Charge trap layer

Claims (20)

Board;
A source region electrically connected to the source region; a first channel region located between the source region and the common region; a second channel region located on the first channel region; A charge trapping material layer provided on the first gate insulating layer; a switching layer provided on the charge trapping material layer and capable of switching to a high resistance state and a low resistance state; Wherein the charge trapping material layer includes a first transistor facing the region adjacent to the first channel region in the shared region with the first gate insulating layer interposed therebetween; And
A drain region disposed on the substrate and spaced apart from the common region, a drain electrode electrically connected to the drain region, a second channel region located between the common region and the drain region, And a second transistor having a second gate insulating layer, a second gate electrode provided on the second gate insulating layer, and a source region serving as the common region. The method according to claim 1,
Wherein the first transistor comprises:
Further comprising a leakage prevention region disposed on the substrate in contact with the source region and forming a PN diode structure with the source region,
And the source electrode is in contact with the leakage preventing region. 3. The method of claim 2,
And the leakage preventing region is surrounded by the source region other than an area in contact with the source electrode. The method according to claim 1,
Wherein the first channel region and the second channel region have opposite conductivity. 5. The method of claim 4,
Wherein the first transistor comprises:
And a well surrounding the source region, the first channel region, and the common region in the substrate and having a conductivity opposite to the second channel region. The method according to claim 1,
Wherein the first gate electrode and the source electrode are electrically connected to each other. The method according to claim 1,
And a boosting electrode facing the charge trapping material layer with the first gate insulating layer and the substrate interposed therebetween. The method according to claim 1,
Wherein the switching layer comprises a nanofilament material capable of being switched to the low resistance state by forming a conductive nanofilament upon application of a voltage. The method according to claim 1,
Wherein the switching layer comprises a PN diode layer. A method of operating a weighting device according to claim 1,
Applying a selection voltage to the second gate electrode to open the second channel region;
Applying a write voltage to the drain electrode; And
And grounding the first gate electrode,
Wherein charge is introduced into the layer of charge trapping material through the first gate electrode by the write voltage to record information in the layer of charge trapping material. A method of operating a weighting device according to claim 1,
Applying a selection voltage to the second gate electrode to open the second channel region;
Applying a erase voltage to the first gate electrode; And
And grounding the drain electrode,
And removing the charge trapped in the charge trapping material layer by the erase voltage to erase the information. A method of operating a weighting device according to claim 1,
Applying a selection voltage to the second gate electrode to open the second channel region;
Applying a read voltage to the source electrode; And
And measuring the measured current at the drain electrode to read the amount of charge trapped in the layer of charge trapping material. 11. The method of claim 10,
Wherein the step of applying the write voltage comprises:
Applying a pulse voltage to the drain electrode to reflect a weight,
And the reflection of the weight is adjusted by the application number of the pulse voltage. 12. The method of claim 11,
The step of applying the erase voltage comprises:
Applying a pulse voltage to the first gate electrode to reflect a weight,
And the reflection of the weight is adjusted by the application number of the pulse voltage. A plurality of weighting elements according to claim 1; And
And a plurality of neuron transistors for selectively switching gate voltages applied to the plurality of weight elements. 16. The method of claim 15,
Wherein the plurality of neuron transistors are two-dimensionally arranged,
A drain electrode of the plurality of neuron transistors is connected to a first gate electrode of the plurality of weight elements,
A selection line connected to a gate electrode of a neuron transistor located in the same column to apply a selection voltage; And
And an input line connected to the source electrode of the neuron transistor located in the same row and capable of applying an input voltage. 16. The method of claim 15,
Wherein the plurality of weight elements are arranged one-dimensionally or two-dimensionally. 17. A method of operating a neural network according to claim 15,
An operation method of a supervised learning neural network for predetermining input information input through the plurality of neuron transistors and output information output through the plurality of weight elements and determining a weight value of the neural network corresponding thereto . 20. A method of operating a neural network according to claim 19,
A method of operating an unsupervised learning neural network in which weight values of a neural network are autonomously determined according to input information input through a neuron transistor. A third transistor having a third gate electrode, a first electrode, and a second electrode;
A fourth transistor sharing the third transistor and the second electrode, the fourth transistor including a fourth gate electrode and a third electrode;
A fifth transistor having a fifth gate electrode, a fourth electrode, and a common region as a drain;
A sixth transistor having a sixth gate electrode, a fifth electrode and serving as the source region;
A switching layer formed on the first electrode and the third electrode, the switching layer being switchable between a high resistance state and a low resistance state;
A charge trapping material layer located on the switching layer, the charge trapping material layer capturing or discharging charge according to a resistance state of the switching layer; And
And an interconnect connecting the charge trapping material layer and the sixth gate electrode.

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