KR102421528B1 - Organic light emitting display device - Google Patents

Abstract

The present application relates to an organic light emitting diode display capable of preventing cracks from occurring at the periphery of a display panel. An organic light emitting diode display according to the present application includes a base layer, a buffer layer disposed on the base layer, a gate insulating layer disposed on the buffer layer, a first interlayer insulating layer disposed on the gate insulating layer, and an upper portion of the first interlayer insulating layer and a second interlayer insulating layer disposed on the , and a planarization layer disposed on the second interlayer insulating layer. The buffer layer extends outwardly from the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, and the base layer extends outwardly from the buffer layer. The planarization layer extends outwardly from the second interlayer insulating layer to cover upper portions of the base layer and the buffer layer.

Description

Organic light emitting display device {ORGANIC LIGHT EMITTING DISPLAY DEVICE}

This application relates to an organic light emitting display device.

In the information society, many technologies have been developed in the field of display devices for displaying visual information as images or images. Among display devices, an organic light emitting diode display displays an image using an organic light emitting diode that generates light by recombination of electrons and holes. The organic light emitting diode display has a fast response speed and at the same time is able to express low grayscale according to self-luminescence, so it is in the spotlight as a next-generation display.

The organic light emitting diode display includes a display panel having a display area in which pixels displaying an image are provided and a non-display area disposed outside the display area to not display an image.

In particular, in recent years, the demand for flexible organic light emitting display devices in which the display panel can be bent is increasing. A foldable display device using a flexible display panel is being developed. The most fatal among defects that may occur when the flexible display panel is repeatedly folded or bent is a crack that prevents the display panel itself from being driven.

Cracks are generated at the outer edge of the display panel and propagate inside. When the display panel is repeatedly folded, physical stress is transferred to layers or films constituting the display panel. When the transferred stress is not tolerated, cracks occur in which the layers are broken, making it impossible to drive the display panel itself. It is possible to reduce the defect rate of the display panel only by reducing the crack occurrence rate.

An object of the present application is to provide an organic light emitting diode display capable of preventing cracks from occurring at the periphery of a display panel.

An organic light emitting diode display according to the present application includes a base layer, a buffer layer disposed on the base layer, a gate insulating layer disposed on the buffer layer, a first interlayer insulating layer disposed on the gate insulating layer, and an upper portion of the first interlayer insulating layer and a second interlayer insulating layer disposed on the , and a planarization layer disposed on the second interlayer insulating layer. The buffer layer extends outwardly from the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, and the base layer extends outwardly from the buffer layer. The planarization layer extends outwardly from the second interlayer insulating layer to cover upper portions of the base layer and the buffer layer.

In the present application, the buffer layer and the base layer are extended outwardly in steps in a step shape, and the upper surface of the step structure is covered with a flexible planarization film. Accordingly, the present application can increase the bonding force between the upper planarization layer and the organic material of the lower base layer, thereby preventing cracks from occurring or propagation of cracks from the outside.

1 is a conceptual block diagram of an organic light emitting display device according to the present application.
2 is an internal circuit diagram of a pixel according to an example of the present application.
3 is a cross-sectional view of a pixel according to an example of the present application.
4 is a plan view of an organic light emitting display device according to an example of the present application.
FIG. 5 is an enlarged view of FIG. 4 .
6 is a cross-sectional view taken along line I-I` of FIG. 5 according to an example.
7 is a cross-sectional view taken along line I-I` of FIG. 5 according to another example.

Advantages and features of the present application, and a method of achieving them will become apparent with reference to examples described below in detail in conjunction with the accompanying drawings. However, the present application is not limited to the examples disclosed below, but will be implemented in various different forms, and only examples of the present application allow the disclosure of the present application to be complete, and common knowledge in the technical field to which the present application belongs It is provided to fully inform those who have the scope of the invention, and the present application is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining an example of the present application are exemplary, and thus the present application is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present application, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present application, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless specifically stated otherwise.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described as 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present application.

"First horizontal axis direction", "second horizontal axis direction", and "vertical axis direction" should not be construed only as a geometric relationship in which the relationship between each other is vertical, and the range in which the configuration of the present application can function functionally It may mean to have a broader direction than within.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It may mean a combination of all items that can be presented from more than one.

Each feature of the various examples of the present application may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each example may be implemented independently of each other or may be implemented together in a related relationship. .

Hereinafter, a preferred example of an organic light emitting diode display according to the present application will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings.

1 is a conceptual block diagram of an organic light emitting display device according to the present application. The organic light emitting diode display according to the present application includes a display panel 100 , a gate driver 110 , a data driver 120 , and a timing controller (T-CON) 130 .

The display panel 100 includes a display area and a non-display area provided around the display area. The display area is an area in which pixels P are provided to display an image. The non-display area is outside the display panel 100 and is an area that protects the display area from external impact. The display panel 100 includes gate lines GL1 to GLp, where p is a positive integer greater than or equal to 2), data lines DL1 to DLq, q is a positive integer greater than or equal to 2), and sensing lines SL1 to SLq. do.

The data lines DL1 to DLq and the sensing lines SL1 to SLq may cross the gate lines GL1 to GLp. The data lines DL1 to DLq and the sensing lines SL1 to SLq may be parallel to each other. The display panel 100 may include a lower substrate on which the pixels P are provided and an upper substrate that performs an encapsulation function to protect the pixels P from external foreign substances. Each of the pixels P may be connected to any one of the gate lines GL1 to GLp, any one of the data lines DL1 to DLq, and any one of the sensing lines SL1 to SLq.

The gate driver 120 receives the gate driver control signal GCS from the timing controller 130 , generates gate signals according to the gate driver control signal GCS and supplies them to the gate lines GL1 to GLp.

The data driver 120 receives the data driver control signal DCS from the timing controller 130 , generates data voltages according to the data driver control signal DCS and supplies them to the data lines DL1 to DLq. In addition, the data driver 120 senses the voltage and current characteristics of each of the pixels P to generate the sensing data SEN and supply it to the timing controller 130 .

The timing controller 130 receives from the outside a timing signal TS for controlling the display timing of an image and digital video data DATA including color-specific information for realizing an image. A timing signal TS and digital video data DATA are input to the input terminal of the timing controller 130 according to a set protocol. Also, the timing controller 130 receives sensing data SEN according to voltage and current characteristics of each of the pixels P from the data driver 120 .

The timing signal TS includes a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a data enable signal (DE), and a dot clock (DCLK). include The timing controller 130 compensates the digital video data DATA based on the sensed data SEN.

The timing controller 130 generates driver control signals for controlling operation timings of the gate driver 110 , the data driver 120 , the scan driver, and the sensing driver. The driver control signals are the gate driver control signal GCS for controlling the operation timing of the gate driver 110 , the data driver control signal DCS for controlling the operation timing of the data driver 120 , and the operation timing of the scan driver. and a scan driver control signal for controlling the sensing driver and a sensing driver control signal for controlling an operation timing of the sensing driver.

The timing controller 130 operates the data driver 120 , the scan driver, and the sensing driver in any one of a display mode and a sensing mode according to a mode signal. The display mode is a mode in which the pixels P of the display panel 100 display an image, and the sensing mode is a mode in which the current of the driving transistor DT of each of the pixels P of the display panel 100 is sensed. When the waveform of the scan signal supplied to each of the pixels P and the waveform of the sensing signal are changed in each of the display mode and the sensing mode, the data driver control signal DCS, the scan driver control signal and The sensing driver control signal may also be changed. Accordingly, the timing controller 130 generates the data driver control signal DCS, the scan driver control signal, and the sensing driver control signal corresponding to the corresponding mode according to which mode is the display mode and the sensing mode.

The timing controller 130 outputs the gate driver control signal GCS to the gate driver 110 . The timing controller 130 outputs the compensated digital video data and the data driver control signal DCS to the data driver 120 . The timing controller 130 outputs the scan driver control signal to the scan driver. The timing controller 130 outputs the sensing driver control signal to the sensing driver.

Also, the timing controller 130 generates a mode signal for driving the data driver 120 , the scan driver, and the sensing driver according to which mode among the display mode and the sensing mode is driven. The timing controller 130 operates the data driver 120 , the scan driver, and the sensing driver in any one of a display mode and a sensing mode according to a mode signal.

2 is an internal circuit diagram of a pixel P according to an example of the present application. The pixel P according to an example includes a driving transistor DT, a light emitting device EL, a storage capacitor Cst, and first to sixth transistors T1 to T6 . In the following description, the driving transistor DT and the first to sixth transistors T1 to T6 according to an example of the present application have a gate electrode, a source electrode, and a drain electrode. It is assumed that the P-type MOSFET is implemented.

The gate electrode of the driving transistor DT is a first node N1 to which one electrode of the storage capacitor Cst, the drain electrode of the first transistor T1, and the drain electrode of the fifth transistor T5 are connected. is connected to The source electrode of the driving transistor DT is connected to the drain electrode of the third transistor T3 receiving the pixel driving power ELVDD as the source electrode. The drain electrode of the driving transistor DT is connected to the source electrode of the fourth transistor T4 .

When a voltage greater than the threshold voltage is applied to the gate electrode of the driving transistor DT, it is turned on. The turned-on driving transistor DT flows a driving current from the source electrode to the drain electrode.

The light emitting element EL includes an anode electrode and a cathode electrode. The light emitting element EL flows a driving current from the anode electrode to the cathode electrode. The anode electrode of the light emitting element EL is connected to the second node N2 to which the drain electrode of the fourth transistor T4 is connected. The cathode electrode of the light emitting element EL is connected to a ground line on which the low potential power voltage ELVSS is formed. The light emitting element EL emits light with a brightness corresponding to the driving current flowing from the driving transistor DT.

The storage capacitor Cst has both electrodes. One electrode of the storage capacitor Cst is connected to the first node N1 . The other electrode of the storage capacitor Cst is connected to the pixel driving power supply ELVDD line.

The storage capacitor Cst stores the difference voltage between the pixel driving power ELVDD and the first node N1 when the fifth transistor T5 connected to the first node N1 is turned on. The storage capacitor Cst maintains the differential voltage stored in the first node N1 when the fifth transistor T5 is turned off. Also, the storage capacitor Cst may control the driving of the driving transistor DT using the stored and maintained voltage.

The gate electrode of the first transistor T1 receives the second scan signal Scan2 . The source electrode of the first transistor T1 is connected to the drain electrode of the driving transistor DT. The drain electrode of the first transistor T1 is connected to the first node N1 . The first transistor T1 is turned on by the second scan signal Scan2 so that the voltage of the first node N1 is Vdata which is the sum of the data voltage Vdata and the threshold voltage Vtp of the driving transistor DT. Raise it to +Vtp.

The gate electrode of the second transistor T2 receives the second scan signal Scan2. The source electrode of the second transistor T2 is connected to the data line DL to receive the data voltage Vdata. The drain electrode of the second transistor T2 is connected to the source electrode of the driving transistor DT. The second transistor T1 is turned on by the second scan signal Scan2 to supply the data voltage Vdata to the source electrode of the driving transistor DT.

The gate electrode of the third transistor T3 receives the emission control signal EM. The source electrode of the third transistor T3 receives the pixel driving power ELVDD. The drain electrode of the third transistor T3 is connected to the source electrode of the driving transistor DT. The third transistor T3 is turned on by the emission control signal EM to supply the pixel driving power ELVDD to the driving transistor DT so that the driving transistor DT flows a driving current.

The gate electrode of the fourth transistor T4 receives the emission control signal EM. The source electrode of the fourth transistor T4 is connected to the drain electrode of the driving transistor DT. The drain electrode of the fourth transistor T4 is connected to the second node N2 . The fourth transistor T4 is turned on by the light emission control signal EM, and a driving current flows through the light emitting element EL to cause the light emitting element EL to emit light.

The gate electrode of the fifth transistor T5 receives the first scan signal Scan1 . The source electrode of the fifth transistor T5 is supplied with the initialization voltage Vinit. The drain electrode of the fifth transistor T5 is connected to the first node N1 . The fifth transistor T5 is turned on by the first scan signal Scan1 to initialize the voltage of the first node N1 to the initialization voltage Vinit.

The gate electrode of the sixth transistor T6 receives the first scan signal Scan1 . The source electrode of the sixth transistor T6 is supplied with the initialization voltage Vinit. The drain electrode of the sixth transistor T6 is connected to the second node N2 . The sixth transistor T6 is turned on by the first scan signal Scan1 to initialize the voltage of the second node N2 to the initialization voltage Vinit.

The pixel P according to the first embodiment of the present invention is composed of seven thin film transistors (TFTs) and one capacitor, and thus is collectively referred to as a 7T1C compensation circuit. Also, the pixel P according to the first embodiment of the present invention operates with two types of scan signals and one type of emission control signal EM.

At the start of an arbitrary frame, the difference voltage Vgs between the gate voltage and the source voltage of the driving transistor DT maintains the gate low voltage VGL state. In addition, the light emission control signal EM is also in the gate low voltage VGL state. Accordingly, the third and fourth transistors T3 and T4 are turned on. Accordingly, a certain amount of driving current flows through the driving transistor DT to cause the light emitting element EL to emit light.

Thereafter, the emission control signal EM has the gate high voltage VGH, and the source electrode and the drain electrode of the driving transistor DT are in a floating state.

Thereafter, the pixel P has an initialization step. In the initialization step, when the first scan signal Scan1 becomes the gate low voltage VGL, the fifth transistor T5 is turned on, and the initialization voltage Vinit is applied to the first node N1 . After the initialization step, when the first scan signal Scan1 becomes the gate high voltage VGH again, the fifth transistor T5 is turned off and the first node N1 is in a floating state.

Thereafter, the pixel P has a programming step. In the programming step, when the second scan signal Scan2 becomes the gate low voltage VGL, the first, second, and sixth transistors T1 , T2 , and T6 are turned on. The light emitting element EL is reset by the sixth transistor T6. In addition, the second transistor T2 is turned on to supply the data voltage Vdata to the source electrode of the driving transistor DT.

The initialization voltage Vinit of the pixel P according to an example of the present application is lower than the data voltage Vdata. In addition, the data voltage Vdata is supplied to the source electrode of the driving transistor DT, and the initialization voltage is supplied to the gate electrode of the driving transistor DT. Accordingly, the difference voltage Vgs between the gate voltage and the source voltage of the driving transistor DT has a negative voltage value.

When the difference voltage Vgs between the gate voltage and the source voltage has a negative voltage value, the driving transistor DT operates in a linear region. Accordingly, the voltage of the drain electrode of the driving transistor DT increases. Since the first transistor T1 is in a turned-on state, the drain electrode and the gate electrode of the driving transistor may be viewed as electrically identical nodes. As a result, the voltage of the first node N1 increases to Vdata+Vth, which is a voltage value obtained by summing the data voltage Vdata and the threshold voltage Vth of the driving transistor DT. Here, the threshold voltage Vth has a negative voltage value.

Thereafter, the pixel P has a threshold voltage Vth sensing step. In the threshold voltage Vth sensing step, since the voltage of the first node N1 has risen to a voltage value obtained by adding the data voltage Vdata and the threshold voltage Vth of the driving transistor DT, the driving transistor DT is It is turned off and only the leakage (subthreshold) current flows.

In this case, the threshold voltage Vth may be sensed by sensing the voltage Vdata+Vth of the gate electrode of the driving transistor DT based on the data voltage Vdata.

Thereafter, when the emission control signal EM becomes the gate low voltage VGL again, the pixel driving voltage ELVDD is supplied to the drain electrode of the driving transistor. Accordingly, the next frame starts, and the light emitting element EL emits light.

3 is a cross-sectional view of a pixel P according to an example of the present application. The pixel P according to an example has a base layer 210 , a buffer layer 220 , a semiconductor layer 230 , a gate insulating layer 235 , a first metal layer 240 , a second metal layer 250 , and a first interlayer. an insulating layer 260 , a third metal layer 270 , a second interlayer insulating layer 280 , a planarization layer 290 , an anode electrode 300 , a light emitting layer 320 , a cathode electrode 330 , and a barrier rib 340 . do.

The base layer 210 forms the lowermost layer of the organic light emitting diode display. The base layer 210 may support circuit elements and wirings forming the circuit unit provided thereon. Alternatively, the base layer 210 may be formed of a flexible polymer compound such as polyimide (PI) or plastic, so that the organic light emitting diode display can be flexible.

The buffer layer 220 covers an upper portion of the base layer 210 . The buffer layer 220 is formed of a material having excellent insulating properties. The buffer layer 220 protects circuit elements and wires forming the circuit unit provided on the base layer 210 from external impact or static electricity.

The semiconductor layer 230 is disposed on the buffer layer 220 . The semiconductor layer 230 is made of a doped semiconductor. The semiconductor layer 230 forms a channel of the thin film transistor constituting the pixel P. The semiconductor layer 230 includes a gate channel 231 , a first channel 232 , and a second channel 233 . The gate channel 231 forms a channel of the gate electrode of the thin film transistor. The first and second electrode layers 233 form channels of source and drain electrodes of the thin film transistor.

The gate insulating layer 235 is disposed on the buffer layer 220 and the semiconductor layer 230 . The gate insulating layer 235 entirely covers the buffer layer 220 and the semiconductor layer 230 . The gate insulating layer 235 is formed of a material having excellent insulating properties. The gate insulating layer 235 prevents the semiconductor layer 230 from being short-circuited with the first metal layer 240 , and separates a channel of the thin film transistor formed by the semiconductor layer 230 .

The first metal layer 240 is disposed on the gate insulating layer 235 . The first metal layer 240 is a gate metal layer forming the gate electrode and the gate lines GL1 to GLp of the thin film transistor. The first metal layer 240 may be formed of a metal or alloy having excellent electrical conductivity.

The first interlayer insulating layer 260 is disposed on the first metal layer 240 . The first interlayer insulating layer 260 is formed of a material having excellent electrical insulation properties.

The third metal layer 270 is disposed on the first interlayer insulating layer 260 . The third metal layer 270 is disposed to overlap the first metal layer 240 forming the gate electrode of the thin film transistor among the first metal layers 240 . The third metal layer 270 forms a mutual capacitance with the first metal layer 240 forming the gate electrode of the thin film transistor. The third metal layer 270 functions as an electrode on one side of the storage capacitance.

The second interlayer insulating layer 280 is disposed on the first interlayer insulating layer 260 and the third metal layer 270 . The second interlayer insulating layer 280 is formed of a material having excellent electrical insulation properties.

The second metal layer 250 is disposed on the second interlayer insulating layer 280 . The second metal layer 250 forms the first electrode 251 and the second electrode 252 of the thin film transistor constituting the pixel (P). The second metal layer 250 is a source/drain metal layer disposed on the first metal layer 240 . The second metal layer 250 may be formed of a metal or an alloy having excellent electrical conductivity.

The planarization layer 290 is disposed on the second interlayer insulating layer 280 and the second metal layer 250 . The planarization layer 290 reduces the height difference between the top surfaces. Accordingly, it is possible to solve that the planarization layer 290 has a height in the Z-axis direction with respect to the base layer 210 that varies depending on the region.

The anode electrode 300 is disposed on the planarization layer 290 . The anode electrode 300 is connected to the second electrode 252 of the thin film transistor constituting the pixel (P). The anode electrode 300 supplies a driving voltage or a data voltage to the second electrode 252 of the thin film transistor. The anode electrode 300 may be divided for each pixel P. Between the anode electrodes 300 adjacent to each other may be electrically insulated due to the barrier rib 340 .

The light emitting layer 320 is provided on the anode electrode 300 . The emission layer 320 may include a hole transporting layer, an organic light emitting layer, and an electron transporting layer. In the emission layer 320, when a voltage is applied to the anode electrode 300 and the cathode electrode 330, holes and electrons move to the organic emission layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the organic emission layer to emit light.

The cathode electrode 330 is provided on the emission layer 320 and the bank 340 . The cathode electrode 330 supplies a driving voltage.

The bank 340 is provided between the anode electrodes 300 of the pixels P. The bank 340 partitions the pixels P.

4 is a plan view of an organic light emitting display device according to an example of the present application.

An organic light emitting diode display according to an example includes a display panel 100 , a driving integrated circuit 400 , and a trimming line TRL.

The display panel 100 includes a display area DA and a non-display area provided around the display area. The display area DA is an area in which pixels P are provided to display an image. The non-display area is outside the display panel 100 and is an area that protects the display area from external impact.

The driving integrated circuit 400 is disposed in a non-display area of the display panel 100 . For example, the driving integrated circuit 400 may be disposed in a non-display area provided in the upper center of the display panel 100 . The driving integrated circuit 400 may have some or all of the functions of the gate driver 110 , the data driver 120 , and the timing controller 130 of FIG. 1 . For example, when the driving integrated circuit 400 has all the functions of the data driver 120 and the timing controller 130 , the driving integrated circuit 400 implements the functions of the data driver 120 and the timing controller 130 . In addition, the gate driver 110 may be implemented as a gate in panel (GIP) circuit built in one or both sides of the non-display area.

The trimming line TRL is formed on the non-display area of the display panel 100 . The trimming line TRL according to an example may be provided to surround the display area DA of the display panel 100 . The trimming line TRL defines both ends of a substrate made of glass or plastic constituting the display panel 100 . A driving circuit such as a gate-in panel circuit and driving lines may be disposed in an inner region of the trimming line TRL among the non-display regions. A folding pattern may be disposed in an area outside of the trimming line TRL among the non-display area. The organic light emitting diode display having the trimming line TRL may increase flexibility in the outer region. Accordingly, even when the organic light emitting diode display is repeatedly folded, it is possible to prevent a crack from occurring in the outer region.

FIG. 5 is an enlarged view of FIG. 4 . 6 is a cross-sectional view taken along line I-I` of FIG. 5 according to an example. 7 is a cross-sectional view taken along line I-I` of FIG. 5 according to another example.

In the organic light emitting diode display according to an example, in a non-display area, the base layer 210 , the buffer layer 220 , the gate insulating layer 235 , the first interlayer insulating layer 260 , the second interlayer insulating layer 280 , and the planarization layer are formed. (290).

The base layer 210 is integrally formed in the display area DA and the non-display area to form a lower surface of the organic light emitting diode display. The base layer 210 may be formed of a flexible polymer compound such as polyimide or plastic. Accordingly, the base layer 210 may allow the outer region of the non-display region to be flexible. The base layer 210 is cut based on the scribing line SCL among the outside of the non-display area.

The buffer layer 220 is integrally formed in the display area DA and the non-display area, and is disposed on the base layer 210 . The buffer layer 220 is formed of a material having excellent insulating properties. The buffer layer 220 covers the base layer 210 except for a partial area outside the base layer 210 disposed in the non-display area. The buffer layer 220 may be formed of an inorganic layer.

The gate insulating layer 235 is integrally formed in the display area DA and the non-display area, and is disposed on the buffer layer 220 . The gate insulating layer 235 is formed of a material having excellent insulating properties. The gate insulating layer 235 covers the buffer layer 220 except for a partial area outside the buffer layer 220 disposed in the non-display area. The gate insulating layer 235 has a predetermined hardness. The gate insulating layer 235 may be formed of an inorganic layer.

The first interlayer insulating layer 260 is integrally formed in the display area DA and the non-display area, and is disposed on the gate insulating layer 235 . The first interlayer insulating film 260 is formed of a material having excellent insulating properties. The first interlayer insulating layer 260 covers the entire upper portion of the gate insulating layer 235 . The first interlayer insulating film 260 has a predetermined hardness. The first interlayer insulating layer 260 may be formed of an inorganic layer.

The second interlayer insulating layer 280 is integrally formed in the display area DA and the non-display area, and is disposed on the first interlayer insulating layer 260 . The second interlayer insulating film 280 is formed of a material having excellent insulating properties. The second interlayer insulating layer 280 covers the entire upper portion of the first interlayer insulating layer 260 . The second interlayer insulating film 280 has a predetermined hardness. The second interlayer insulating layer 280 may be formed of an inorganic layer.

The planarization layer 290 is integrally formed in the display area DA and the non-display area, and is disposed on the second interlayer insulating layer 280 . The planarization layer 290 may be formed of an organic layer. The planarization layer 290 according to an example may be formed of a flexible polymer compound such as polyimide.

The buffer layer 220 according to an example extends outwardly from the gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 . The gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 are partially removed outside the non-display area.

The gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 are layers necessary for insulating between the metal layers constituting the thin film transistors constituting the pixel P in the display area DA. However, when the gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 are disposed in the entire region in which the buffer layer 220 is disposed, a predetermined hardness is obtained outside the non-display area. The layers having the layers are disposed outside the non-display area.

When the layers having hardness are disposed at the outside of the non-display area, there is a problem in that cracks are easily generated at the outside of the non-display area due to repeated folding. Also, when the layers having hardness are disposed outside the non-display area, cracks generated at the outside propagate in the direction of the display area DA to damage the driving circuit and wirings.

According to an example, the gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 are removed from the outside of the non-display area so that the buffer layer 220 is formed from the gate insulating layer 235 and the second insulating layer 235 . The first interlayer insulating layer 260 and the second interlayer insulating layer 280 protrude outwardly. When the buffer layer 220 protrudes to the outside, the possibility of cracks occurring at the outside of the non-display area is reduced. In addition, when the buffer layer 220 protrudes to the outside, even if a crack occurs at the outside, the possibility of the crack propagating to the gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 is reduced. do.

In addition, the base layer 210 according to an example extends outwardly than the buffer layer 220 . The base layer 210 and the buffer layer 220 are partially removed from the outside of the non-display area.

The base layer 210 is made of a flexible plastic or polyimide having excellent ductility, and the buffer layer 220 is made of a material having lower ductility than the base layer 210 . Accordingly, when only the base layer 210 is disposed in the outermost portion, the possibility of cracking is lower than when the base layer 210 and the buffer layer 220 form a stacked structure.

In an example of the present application, the base layer 210 extends a lot in the outer direction of the non-display area. The buffer layer 220 extends less in the outer direction of the non-display area than the base layer 210 , and extends more than the gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 . The gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 extend slightly in the outer direction of the non-display area. That is, the gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 are partially removed in the outer direction of the non-display area.

Due to this structure, it is possible to prevent cracks from occurring at the outside of the non-display area, and cracks in the outside area are passed through the gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 . Propagation in the display area DA direction may be prevented.

The planarization layer 290 of the organic light emitting diode display according to an example may be disposed on the second interlayer insulating layer 280 as shown in FIGS. 5 and 6 . The planarization layer 290 may be partially removed from the top of the second interlayer insulating layer 280 in an outer direction of the non-display area. In this case, generation and propagation of cracks are blocked by the first and second folding patterns FP1 and FP2.

However, in the case of such a structure, the gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 are laterally exposed outside the non-display area. More specifically, in the region where the buffer layer 220 is exposed, the gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 are exposed laterally. In this case, cracks may propagate through side surfaces of the gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 .

In order to prevent crack propagation through the side surfaces of the gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 , an organic light emitting diode display according to another example as shown in FIG. 7 is implemented. can

The planarization layer 290 of the organic light emitting diode display according to another example extends outwardly from the second interlayer insulating layer 280 . The extended planarization layer 290 covers the base layer 210 and the buffer layer 220 . The planarization layer 290 extends in an outer direction of the non-display area and covers the entire upper portion of the buffer layer 220 and partially covers the upper portion of the base layer 210 .

The planarization layer 290 according to an example covers side surfaces of the gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 . The planarization layer 290 may be formed of a flexible organic material. When the planarization layer 290 covers side surfaces of the gate insulating layer 235, the first interlayer insulating layer 260, and the second interlayer insulating layer 280, the gate insulating layer 235, the first interlayer insulating layer 260, and a buffer layer formed on a side surface of the second interlayer insulating layer 280 . Accordingly, it is possible to prevent cracks from occurring in the side surfaces of the gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 .

The planarization layer 290 according to an example has a step difference on the boundary line between the base layer 210 and the buffer layer 220 . The boundary line between the base layer 210 and the buffer layer 220 means an outer boundary line of the buffer layer 220 on the non-display area. The planarization layer 290 is a layer that does not have a step difference in the upper surface. However, on the boundary line between the base layer 210 and the buffer layer 220 , the planarization layer 290 has a structure in which an upper surface has a step difference.

The height of the upper surface of the planarization layer 290 according to an example is different in the area overlapping the upper surface of the base layer 210 and the area overlapping the upper surface of the buffer layer 220 . The height of the upper surface of the planarization layer 290 increases when the upper surface of the base layer 210 is changed from the exposed area to the exposed area of the buffer layer 220 . Accordingly, the planarization layer 290 has a stepped structure on the boundary line between the base layer 210 and the buffer layer 220 .

The planarization layer 290 according to an example has a step difference on the boundary line between the buffer layer 220 and the second interlayer insulating layer 280 . The boundary line between the buffer layer 220 and the second interlayer insulating layer 280 means an outer boundary line of the second interlayer insulating layer 280 on the non-display area.

The height of the top surface of the planarization layer 290 according to an example is different in a region overlapping the top surface of the buffer layer 220 and in a region overlapping the top surface of the second interlayer insulating layer 280 . The height of the upper surface of the planarization layer 290 increases when the upper surface of the buffer layer 220 is exposed to the area in which the upper surface of the second interlayer insulating layer 280 is exposed. Accordingly, the planarization layer 290 has a stepped structure on the boundary line between the buffer layer 220 and the second interlayer insulating layer 280 .

In this way, the stacked structure of the inorganic film is sequentially formed in a step form from the stacked form of the base layer 210 and the buffer layer 220 provided in the outer region of the non-display area and the stacked form of the buffer layer 220 and the second interlayer insulating film 280 . It can be formed into a structure having a phosphorus step. In addition, the planarization layer 290 , which is an organic layer, may be covered on the entire surface of the laminate structure of the inorganic layer provided in the outer region of the non-display area. In this case, the inorganic film serving as a transmission medium of cracks is removed. In addition, the planarization film 290, which is an organic film disposed on the upper and lower portions, serves as a cover layer. Accordingly, it is possible to completely block a crack that may be introduced from the outside or a propagation path of the generated crack, thereby minimizing the occurrence of cracks.

A side surface and an upper surface of the buffer layer 220 according to an example are in contact with the planarization layer 290 , respectively. In addition, a side surface and an upper surface of the second interlayer insulating film 280 are in contact with the planarization film 290 , respectively. The planarization layer 290 is in contact with the top surface of the second interlayer insulating layer 280 , and extends from the top surface of the second interlayer insulating layer 280 in the outer direction of the display device to be in contact with the side surface of the second interlayer insulating layer 280 . . In addition, the planarization layer 290 is formed to extend from the side surface of the second interlayer insulating layer 280 in the outer direction of the display device to contact the upper surface of the buffer layer 220 . In addition, the planarization layer 290 is formed to extend from the top surface of the buffer layer 220 in the outer direction of the display device to contact the side surface of the buffer layer 220 .

When the side and top surfaces of the buffer layer 220 and the second interlayer insulating layer 280 according to an example are in contact with the planarization layer 290, respectively, the planarization layer 290 forms the buffer layer 220 and the second interlayer insulating layer 280. They have a structure that binds them together. In particular, since the planarization layer 290 is formed to be integrally connected to the side and top surfaces of the buffer layer 220 and the second interlayer insulating layer 280 without being separated from each other, the planarization layer 290 is formed between the buffer layer 220 and the first interlayer. It has a structure in which the insulating film 260 and the second interlayer insulating film 280 are integrally coupled. Accordingly, when the planarization layer 290 has a contact structure, the bonding force between the buffer layer 220 and the second interlayer insulating layer 280 may be strengthened by using the planarization layer 290 .

The planarization layer 290 according to an example extends to one end of the base layer 210 . Since one end of the base layer 210 is defined by the trimming line TRL, the planarization layer 290 extends to the trimming line TRL. The planarization layer 290 is integrally formed on the upper surface of the base layer 210 and the upper surface of the buffer layer 220 . In addition, the planarization layer 290 is integrally formed on the upper surface of the buffer layer 220 and the side surfaces of the gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 . In this case, the flow of the upper surface of the base layer 210 and the upper surface of the buffer layer 220 may be prevented. In addition, flow between the upper surface of the buffer layer 220 and the side surfaces of the gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 may be prevented. Accordingly, the planarization layer 290 may increase the bonding force between the inorganic layer layers.

As described above, the first and second folding patterns FP1 and FP2 according to an example may be disposed to block generation and propagation of cracks.

The first folding pattern FP1 according to an example is provided on the upper surface of the base layer 210 . The first folding pattern FP1 is provided on the outer region of the base layer 210 to have a width corresponding to the first distance D1 . The first distance D1 may be 190 μm or more and 210 μm or less.

A plurality of first folding patterns FP1 may be formed, and the shape of the first folding pattern FP1 may be a rectangle as shown in FIG. 5 . However, the present invention is not limited thereto, and the shape of the first folding pattern FP1 may be a polygon or a pattern including a curve. The first folding pattern FP1 may be an embossed or engraved pattern.

The first folding pattern FP1 is formed on the base layer 210 . The first folding pattern FP1 allows the outer region of the base layer 210 to be more easily bent or bent. The first folding pattern FP1 allows the outer region of the base layer 210 to better absorb an external impact. When the first folding pattern FP1 is disposed, it is possible to reduce the occurrence of cracks at the periphery of the base layer 210 during a manufacturing process of the organic light emitting diode display, particularly, a scribing process. In addition, the first folding pattern FP1 may more effectively prevent a crack generated outside the base layer 210 from propagating in the display area DA direction.

Among the first folding patterns FP1 according to an example, the first folding patterns FP1 adjacent to each other in the X-axis direction or the horizontal direction in the first direction may not be parallel to each other but may be displaced from each other. The first folding pattern FP1 is disposed in a zigzag structure in the first direction. The first folding pattern FP1 is disposed parallel to the second direction intersecting the first direction.

When the first folding patterns FP1 adjacent to each other in the first direction are displaced in the first direction, the shock propagating in the first direction may be more efficiently absorbed. Even when an impact is applied in the first direction, the first folding pattern FP1 can efficiently disperse the impact, thereby preventing cracks from propagating in the first direction.

The second folding pattern FP2 is disposed outside the buffer layer 220 . The second folding pattern FP2 is disposed closer to the display area DA than the first folding pattern FP1 . The second folding pattern FP2 is formed on the base layer 210 . The second folding pattern FP2 is disposed to be spaced apart from the first folding pattern FP1 by a predetermined distance. The second folding pattern FP2 is spaced apart from the first folding pattern FP1 in the display area DA direction.

As shown in FIG. 5 , a second distance D2 is provided from the outer edge of the second folding pattern FP2 to the edge of the region where the second interlayer insulating layer 280 is disposed. The second distance D2 may be 340 μm or more and 360 μm or less. The second folding pattern FP2 is disposed in an area adjacent to the outer edge of the buffer layer 220 .

The second folding pattern FP2 may prevent cracks from propagating in the buffer layer 220 even when cracks occur in the outer region of the base layer 210 . Also, the second folding pattern FP2 may prevent separation or splitting between the base layer 210 and the buffer layer 220 when repeatedly folding or bending operations are performed.

Among the second folding patterns FP2 according to an example, the second folding patterns FP2 adjacent to each other in the X-axis direction or the horizontal direction in the first direction may not be parallel to each other but may be displaced from each other. The second folding pattern FP2 is disposed in a zigzag structure in the first direction. The second folding pattern FP2 is parallel to the second direction crossing the first direction.

When the second folding patterns FP2 adjacent to each other in the first direction are displaced in the first direction, the shock propagating in the first direction may be more efficiently absorbed. The second folding pattern FP2 can efficiently disperse even if an impact is applied in the first direction, thereby preventing cracks from propagating in the first direction.

5 and 6 , a third distance D3 is provided from the outer edge of the buffer layer 220 to the outer edge of the planarization layer 290 . The third distance may be 0.9 mm or more and 1.1 mm or less. In this case, since a relatively long distance is provided from the outer edge of the buffer layer 220 to the outer edge of the planarization layer 290 , only the functions of the first and second folding patterns FP1 and FP2, not the planarization layer 290 . to prevent cracks in the base layer 210 and the buffer layer 220 .

On the other hand, according to another example illustrated in FIG. 7 , a fourth distance D4 is provided from the trimming line TRL where the planarization layer 290 is started to the outer edge of the buffer layer 220 .

The fourth distance D4 may be 0.9 mm or more and 1.1 mm or less. The fourth distance D4 may be the same as the third distance D3 . Accordingly, the organic light emitting display device according to another example implements a structure covering the upper surfaces of the base layer 210 and the buffer layer 220 using the planarization layer 290 to form the base layer 210 and the buffer layer 220 . It is possible to prevent cracks from occurring on the upper surface.

The buffer layer 220 according to an example and another example extends outside the gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer insulating layer 280 by a fifth distance D5 . The fifth distance D5 may be 90 μm or more and 110 μm or less. When the buffer layer 220 is extended to the outside, a step structure between the buffer layer 220 and the second interlayer insulating layer 280 may be formed. When the step structure is formed, the planarization layer 290 is formed on the upper surface of the base layer 210 , the upper surface of the buffer layer 220 , and the gate insulating layer 235 , the first interlayer insulating layer 260 , and the second interlayer. The side surface of the insulating layer 280 may be integrally covered.

In the present application, the buffer layer and the base layer are extended outwardly in steps in a step shape, and the upper surface of the step structure is covered with a flexible planarization film. Accordingly, the present application can increase the bonding force between the upper planarization layer and the organic material of the lower base layer, thereby preventing cracks from occurring or propagation of cracks from the outside.

Those skilled in the art through the above-described content will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: gate driver
120: data driver 130: timing controller
P: pixel DT: driving transistor
EL: light emitting element Cst: storage capacitor
T1 to T6: first to sixth transistors 210: base layer
220: buffer layer 230: semiconductor layer
235: gate insulating layer 240: first metal layer
250: second metal layer 260: first interlayer insulating film
270: third metal layer 280: second interlayer insulating film
290: planarization film 300: anode electrode
320: light emitting layer 330: cathode electrode
340 bulkhead 400 drive integrated circuit
TRL: trim line SBL: scribe line
FP1, FP2: first and second folding patterns

Claims (10)

base layer;
a buffer layer disposed on the base layer;
a gate insulating layer disposed on the buffer layer;
a first interlayer insulating film disposed on the gate insulating layer;
a second interlayer insulating film disposed on the first interlayer insulating film;
a planarization layer disposed on the second interlayer insulating layer; and
a trimming line disposed closer to an end of the base layer than the buffer layer;
the buffer layer extends outwardly from the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer;
The base layer extends outwardly than the buffer layer,
The planarization layer extends outwardly from the second interlayer insulating layer to cover upper portions of the base layer and the buffer layer,
A driving circuit is disposed in an inner region of the trimming line on which the buffer layer is disposed,
The planarization layer is in direct contact with an upper surface of the base layer in an inner region of the trimming line. The method of claim 1,
The planarization layer has a step difference on a boundary line between the base layer and the buffer layer and on a boundary line between the buffer layer and the second interlayer insulating layer. The method of claim 1,
A top surface of the planarization layer has a higher height than a top surface of the base layer from a top surface of the buffer layer. The method of claim 1,
A top surface of the planarization layer has a higher height than a top surface of the buffer layer in a top surface of the second interlayer insulating layer. The method of claim 1,
An organic light emitting display device in which side surfaces and top surfaces of the buffer layer and the second interlayer insulating layer are in contact with the planarization layer, respectively. The method of claim 1,
The planarization layer extends to one end of the base layer. The method of claim 1,
The planarization layer is integrally formed on a top surface of the buffer layer and on side surfaces of the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The method of claim 1,
The organic light emitting diode display further comprising a first folding pattern provided in an outer region of the upper surface of the base layer. 9. The method of claim 8,
Among the first folding patterns, first folding patterns adjacent to each other in a first direction are disposed to be shifted in the first direction. 9. The method of claim 8,
and a second folding pattern spaced apart from the first folding pattern in a display area direction and provided outside the buffer layer.

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