KR102475639B1 - Organic light emitting display device - Google Patents

Abstract

The present application relates to an organic light emitting diode display capable of preventing an IR rising phenomenon in which a reference power supply voltage rises even when a driving voltage line and a reference power supply voltage line are electrically connected in a period in which a pixel emits light. An organic light emitting display device according to the present application includes pixels displaying images, a lighting test transistor connected to the pixel to perform a lighting test, an enable line supplying an enable signal for turning on the lighting test transistor, and a lighting test. and a lighting test data line for supplying lighting test data for a lighting test, a reference power supply voltage line for supplying a reference power supply voltage of a pixel, and a connection portion electrically connecting the lighting test data line and the reference power supply voltage line.

Description

Organic light emitting display device {ORGANIC LIGHT EMITTING DISPLAY DEVICE}

The present application relates to an organic light emitting display device.

In the information society, a lot of technologies in the field of display devices for displaying visual information as images or images are being developed. Among display devices, an organic light emitting diode display displays an image using an organic light emitting diode that generates light by recombination of electrons and holes. The organic light emitting display device has a fast response speed and at the same time is capable of expressing low gradation according to self-emission, and thus has been spotlighted as a next-generation display.

An organic light emitting display device includes a display panel having a display area in which pixels displaying images are provided and a non-display area disposed outside the display area and not displaying an image. Each of the pixels is driven by the scan signal and emits light with brightness corresponding to the size of the data voltage.

When the physical size of the reference power supply voltage line is not sufficient, a phenomenon in which the reference power supply voltage rises occurs. A phenomenon in which the reference power supply voltage rises is defined as an IR rising phenomenon. When the IR rising phenomenon occurs, the reference power supply voltage is supplied differently for each pixel, resulting in a luminance deviation within the display area.

An object of the present application is to provide an organic light emitting display device capable of preventing an IR rising phenomenon in which a reference power supply voltage rises even when a driving voltage line and a reference power supply voltage line are electrically connected in a period in which a pixel emits light.

An organic light emitting display device according to the present application includes pixels displaying images, a lighting test transistor connected to the pixel to perform a lighting test, an enable line supplying an enable signal for turning on the lighting test transistor, and a lighting test. and a lighting test data line for supplying lighting test data for a lighting test, a reference power supply voltage line for supplying a reference power supply voltage of a pixel, and a connection portion electrically connecting the lighting test data line and the reference power supply voltage line.

In the present application, the physical size of the reference power supply voltage line is increased by electrically connecting the lighting inspection data line and the reference power supply voltage line. As the physical size of the reference power supply voltage line increases, even if the driving voltage line and the reference power supply voltage line are electrically connected in a period in which pixels emit light, an IR rising phenomenon in which the reference power supply voltage increases can be prevented.

1 is a conceptual block diagram of an organic light emitting display device according to the present application.
2 is an internal circuit diagram of a pixel according to an example of the present application.
3 is a cross-sectional view of a pixel according to an example of the present application.
4 is a diagram illustrating an outer area of an organic light emitting display device according to the present application.
5 is a circuit diagram illustrating an outer area of an organic light emitting display device according to an exemplary embodiment.
6 is a plan view illustrating an outer area of an organic light emitting display device according to an exemplary embodiment.
FIG. 7 is a cross-sectional view taken along line Ⅰ-Ⅰ′ of FIG. 6 .
FIG. 8 is a cross-sectional view taken along line II-II′ of FIG. 6 .
9 is a circuit diagram illustrating an outer area of an organic light emitting display device according to another example.
10 is a plan view illustrating an outer area of an organic light emitting display device according to another example.
FIG. 11 is a cross-sectional view taken along line III-III′ of FIG. 10 .
12 is a circuit diagram illustrating an outer area of an organic light emitting display device according to another example.
13 is a plan view illustrating an outer area of an organic light emitting display device according to another example.
FIG. 14 is a cross-sectional view taken along line IV-IV` of FIG. 13 .
15 is a waveform diagram illustrating an enable signal, a lighting test data, an inverted enable signal, and digital video data in a lighting inspection area and a driving area of an organic light emitting display device according to the present application.

Advantages and features of the present application, and methods of achieving them, will become clear with reference to examples described below in detail in conjunction with the accompanying drawings. However, the present application is not limited to the examples disclosed below and will be implemented in a variety of different forms, only examples of the present application make the disclosure of the present application complete, and common knowledge in the art to which this application belongs It is provided to fully inform the person who has the scope of the invention, and this application is only defined by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining an example of the present application are exemplary, the present application is not limited to the matters shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present application, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present application, the detailed description will be omitted.

When 'includes', 'has', 'consists', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal precedence relationship is described in terms of 'after', 'following', 'next to', 'before', etc. It can also include non-continuous cases unless is used.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present application.

"First horizontal axis direction", "second horizontal axis direction", and "vertical axis direction" should not be interpreted only as a geometric relationship in which the relationship between each other is made vertically, and the range in which the configuration of the present application can function functionally It can mean having a wider direction than within.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, "at least one of the first item, the second item, and the third item" means not only the first item, the second item, or the third item, respectively, but also two of the first item, the second item, and the third item. It may mean a combination of all items that can be presented from one or more.

Each feature of the various examples of the present application can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each example can be implemented independently of each other or can be implemented together in a related relationship. .

Hereinafter, preferred examples of the organic light emitting display device according to the present application will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings.

1 is a conceptual block diagram of an organic light emitting display device according to the present application. An organic light emitting display device according to the present application includes a display panel 100 , a gate driver 110 , a data driver 120 , and a timing controller (T-CON) 130 .

The display panel 100 includes a display area and a non-display area provided around the display area. The display area is an area where the pixels P are provided to display an image. The non-display area is located outside the display panel 100 and protects the display area from external impact. Gate lines GL1 to GLp (where p is a positive integer greater than or equal to 2), data lines DL1 to DLq (where q is a positive integer greater than or equal to 2), and sensing lines SL1 to SLq are provided in the display panel 100 . do.

The data lines DL1 to DLq and the sensing lines SL1 to SLq may cross the gate lines GL1 to GLp. The data lines DL1 to DLq and the sensing lines SL1 to SLq may be parallel to each other. The display panel 100 may include a lower substrate on which the pixels P are provided and an upper substrate performing an encapsulation function to protect the pixels P from external foreign substances. Each of the pixels P may be connected to one of the gate lines GL1 to GLp, one of the data lines DL1 to DLq, and one of the sensing lines SL1 to SLq.

The gate driver 120 receives the gate driver control signal GCS from the timing controller 130, generates gate signals according to the gate driver control signal GCS, and supplies them to the gate lines GL1 to GLp.

The data driver 120 receives the data driver control signal DCS from the timing controller 130, generates data voltages according to the data driver control signal DCS, and supplies them to the data lines DL1 to DLq. In addition, the data driver 120 senses voltage and current characteristics of each of the pixels P to generate sensed data SEN and supplies it to the timing controller 130 .

The timing controller 130 receives a timing signal TS for controlling the display timing of an image and digital video data DATA including color-specific information for realizing an image from the outside. The timing signal TS and digital video data DATA are input to the input terminal of the timing controller 130 according to a set protocol. Also, the timing controller 130 receives sensing data SEN according to voltage and current characteristics of each of the pixels P from the data driver 120 .

The timing signal TS includes a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a data enable signal (DE), and a dot clock (DCLK). include The timing controller 130 compensates the digital video data DATA based on the sensing data SEN.

The timing controller 130 generates driver control signals for controlling operation timings of the gate driver 110 , the data driver 120 , the scan driver, and the sensing driver. The driver control signals include a gate driver control signal (GCS) for controlling the operation timing of the gate driver 110, a data driver control signal (DCS) for controlling the operation timing of the data driver 120, and an operation timing of the scan driver. A scan driver control signal for controlling and a sensing driver control signal for controlling an operation timing of the sensing driver are included.

The timing controller 130 operates the data driver 120, the scan driver, and the sensing driver in one of a display mode and a sensing mode according to a mode signal. The display mode is a mode in which the pixels P of the display panel 100 display an image, and the sensing mode is a mode in which a current of the driving transistor DT of each of the pixels P of the display panel 100 is sensed. When the waveform of the scan signal and the sensing signal supplied to each of the pixels P in the display mode and the sensing mode are changed, the data driver control signal DCS, the scan driver control signal and the The sensing driver control signal may also be changed. Accordingly, the timing controller 130 generates the data driver control signal DCS, the scan driver control signal, and the sensing driver control signal corresponding to the corresponding mode depending on which mode is selected from among the display mode and the sensing mode.

The timing controller 130 outputs the gate driver control signal GCS to the gate driver 110 . The timing controller 130 outputs the compensated digital video data and the data driver control signal DCS to the data driver 120 . The timing controller 130 outputs the scan driver control signal to the scan driver. The timing controller 130 outputs the sensing driver control signal to the sensing driver.

In addition, the timing controller 130 generates a mode signal for driving the data driver 120, the scan driver, and the sensing driver according to which mode among the display mode and the sensing mode is to be driven. The timing controller 130 operates the data driver 120, the scan driver, and the sensing driver in one of a display mode and a sensing mode according to a mode signal.

2 is an internal circuit diagram of a pixel P according to an example of the present application. The pixel P according to an example includes a driving transistor DT, a light emitting element EL, a storage capacitor Cst, and first to sixth transistors T1 to T6. In the following description, the driving transistor DT and the first to sixth transistors T1 to T6 according to an example of the present application have a gate electrode, a source electrode, and a drain electrode. Assume that it is implemented with a P-type MOSFET.

The gate electrode of the driving transistor DT is a first node (N1) to which one side electrode of the storage capacitor Cst, the drain electrode of the first transistor T1, and the drain electrode of the fifth transistor T5 are connected. connected to The source electrode of the driving transistor DT is connected to the drain electrode of the third transistor T3 receiving the pixel driving power source ELVDD as the source electrode. The drain electrode of the driving transistor DT is connected to the source electrode of the fourth transistor T4.

When a voltage higher than the threshold voltage is supplied to the gate electrode of the driving transistor DT, it is turned on. The turned-on driving transistor DT flows a driving current from the source electrode to the drain electrode.

The light emitting element EL includes an anode electrode and a cathode electrode. The light emitting element EL flows a driving current from the anode electrode to the cathode electrode. The anode electrode of the light emitting element EL is connected to the second node N2 to which the drain electrode of the fourth transistor T4 is connected. The cathode electrode of the light emitting element EL is connected to the ground line on which the low potential power supply voltage ELVSS is formed. The light emitting element EL emits light with brightness corresponding to the driving current flowing from the driving transistor DT.

The storage capacitor Cst has both electrodes. One electrode of the storage capacitor Cst is connected to the first node N1. The other electrode of the storage capacitor Cst is connected to the pixel driving power ELVDD line.

The storage capacitor Cst stores a difference voltage between the pixel driving power source ELVDD and the first node N1 when the fifth transistor T5 connected to the first node N1 is turned on. The storage capacitor Cst maintains the differential voltage stored in the first node N1 when the fifth transistor T5 is turned off. Also, the storage capacitor Cst may control driving of the driving transistor DT using the stored and maintained voltage.

The gate electrode of the first transistor T1 receives the second scan signal Scan2. The source electrode of the first transistor T1 is connected to the drain electrode of the driving transistor DT. The drain electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 is turned on by the second scan signal Scan2, and the voltage of the first node N1 is Vdata, which is the sum of the data voltage Vdata and the threshold voltage Vtp of the driving transistor DT. Raise to +Vtp.

The gate electrode of the second transistor T2 receives the second scan signal Scan2. The source electrode of the second transistor T2 is connected to the data line DL to receive the data voltage Vdata. The drain electrode of the second transistor T2 is connected to the source electrode of the driving transistor DT. The second transistor T1 is turned on by the second scan signal Scan2 and supplies the data voltage Vdata to the source electrode of the driving transistor DT.

The gate electrode of the third transistor T3 receives the emission control signal EM. The source electrode of the third transistor T3 receives the pixel driving power source ELVDD. The drain electrode of the third transistor T3 is connected to the source electrode of the driving transistor DT. The third transistor T3 is turned on by the emission control signal EM to supply the pixel driving power source ELVDD to the driving transistor DT so that the driving transistor DT can flow a driving current.

The gate electrode of the fourth transistor T4 receives the emission control signal EM. The source electrode of the fourth transistor T4 is connected to the drain electrode of the driving transistor DT. The drain electrode of the fourth transistor T4 is connected to the second node N2. The fourth transistor T4 is turned on by the emission control signal EM, so that a driving current flows through the light emitting element EL, thereby causing the light emitting element EL to emit light.

The gate electrode of the fifth transistor T5 receives the first scan signal Scan1. The source electrode of the fifth transistor T5 receives the initialization voltage Vinit. A drain electrode of the fifth transistor T5 is connected to the first node N1. The fifth transistor T5 is turned on by the first scan signal Scan1 to initialize the voltage at the first node N1 to the initialization voltage Vinit.

The gate electrode of the sixth transistor T6 receives the first scan signal Scan1. The source electrode of the sixth transistor T6 receives the initialization voltage Vinit. The drain electrode of the sixth transistor T6 is connected to the second node N2. The sixth transistor T6 is turned on by the first scan signal Scan1 to initialize the voltage of the second node N2 to the initialization voltage Vinit.

The pixel P according to the first embodiment of the present invention is composed of seven thin film transistors (TFTs) and one capacitor, and is collectively referred to as a 7T1C compensation circuit. Also, the pixel P according to the first embodiment of the present invention operates with two types of scan signals (Scan) and one type of emission control signal (EM).

When a certain frame starts, the difference voltage Vgs between the gate voltage and the source voltage of the driving transistor DT maintains the gate low voltage VGL. In addition, the emission control signal EM is also in the gate low voltage VGL state. Accordingly, the third and fourth transistors T3 and T4 are turned on. Accordingly, a certain amount of driving current flows through the driving transistor DT, thereby causing the light emitting element EL to emit light.

Thereafter, the emission control signal EM has a gate high voltage VGH, and the source and drain electrodes of the driving transistor DT become a floating state.

Thereafter, the pixel P has an initialization step. In the initialization step, when the first scan signal Scan1 becomes the gate low voltage VGL, the fifth transistor T5 is turned on and the initialization voltage Vinit is applied to the first node N1. After the initialization step, when the first scan signal Scan1 becomes the gate high voltage VGH again, the fifth transistor T5 is turned off and the first node N1 is in a floating state.

After that, the pixel P has a programming step. In the programming step, when the second scan signal Scan2 becomes the gate low voltage VGL, the first, second, and sixth transistors T1, T2, and T6 are turned on. The light emitting element EL is reset by the sixth transistor T6. Also, the second transistor T2 is turned on and the data voltage Vdata is supplied to the source electrode of the driving transistor DT.

The initialization voltage Vinit of the pixel P according to an example of the present application is lower than the data voltage Vdata. In addition, the data voltage Vdata is supplied to the source electrode of the driving transistor DT, and the initialization voltage is supplied to the gate electrode of the driving transistor DT. Accordingly, the difference voltage Vgs between the gate voltage and the source voltage of the driving transistor DT has a negative (-) voltage value.

When the difference voltage Vgs between the gate voltage and the source voltage has a negative voltage value, the driving transistor DT operates in a linear region. Accordingly, the voltage of the drain electrode of the driving transistor DT rises. Since the first transistor T1 is in a turned-on state, the drain electrode and the gate electrode of the driving transistor can be electrically regarded as the same node. As a result, the voltage of the first node N1 rises to Vdata+Vth, which is a sum of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT. Here, the threshold voltage (Vth) has a negative voltage value.

Thereafter, the pixel P has a threshold voltage (Vth) sensing step. In the threshold voltage (Vth) sensing step, since the voltage of the first node (N1) rises to the sum of the data voltage (Vdata) and the threshold voltage (Vth) of the driving transistor (DT), the driving transistor (DT) It is turned off and only the leakage (subthreshold) current flows.

In this case, the threshold voltage Vth may be sensed by sensing Vdata+Vth, which is the voltage of the gate electrode of the driving transistor DT, based on the data voltage Vdata.

Thereafter, when the emission control signal EM becomes the gate low voltage VGL again, the pixel driving voltage ELVDD is supplied to the drain electrode of the driving transistor. Accordingly, the next frame starts, and the light emitting element EL emits light.

3 is a cross-sectional view of a pixel P according to an example of the present application. The pixel P according to an example includes a base layer 210, a buffer layer 220, a semiconductor layer 230, a gate insulating layer 235, a first metal layer 240, a first bridge 241, and a second metal layer. (250), a first interlayer insulating film 260, a third metal layer 270, a second interlayer insulating film 280, a planarization film 290, an anode electrode 300, a light emitting layer 320, a cathode electrode 330, and a partition wall 340 .

The base layer 210 forms the lowest layer of the organic light emitting display device. The base layer 210 may support circuit elements and wires constituting the circuit unit provided thereon. Alternatively, the base layer 210 may be formed of flexible plastic to make the organic light emitting display device flexible.

The buffer layer 220 covers the top of the base layer 210 . The buffer layer 220 is formed of a material having excellent insulating properties. The buffer layer 220 protects circuit elements and wires constituting the circuit unit provided on the base layer 210 from external impact or static electricity.

The semiconductor layer 230 is disposed on top of the buffer layer 220 . The semiconductor layer 230 is made of a doped semiconductor. The semiconductor layer 230 forms a channel of a thin film transistor constituting the pixel P. The semiconductor layer 230 includes a gate channel 231 , a first channel 232 , and a second channel 233 . The gate channel 231 forms a channel of a gate electrode of a thin film transistor. The first and second electrode layers 233 form channels of the source and drain electrodes of the thin film transistor.

The gate insulating layer 235 is disposed on the buffer layer 220 and the semiconductor layer 230 . The gate insulating layer 235 entirely covers the buffer layer 220 and the semiconductor layer 230 . The gate insulating layer 235 is formed of a material having excellent insulating properties. The gate insulating layer 235 prevents the semiconductor layer 230 from being short-circuited with the first metal layer 240 and separates channels of thin film transistors formed by the semiconductor layer 230 .

The first metal layer 240 is disposed on top of the gate insulating layer 235 . The first metal layer 240 is a gate metal layer forming gate electrodes and gate lines GL1 to GLp of the thin film transistor. The first metal layer 240 may be formed of a metal or alloy having excellent electrical conductivity.

The first bridge 241 is disposed on the gate insulating layer 235 . The first bridge 241 is made of the first metal layer 240 . That is, the first bridge 241 is formed using the same material on the same layer as the layer forming the gate electrodes and gate lines GL1 to GLp of the thin film transistor.

The first interlayer insulating film 260 is disposed on the first metal layer 240 and the first bridge 241 . The first interlayer insulating film 260 is formed of a material having excellent electrical insulating properties.

The third metal layer 270 is disposed on the first interlayer insulating layer 260 . The third metal layer 270 is disposed overlapping the first metal layer 240 forming the gate electrode of the thin film transistor among the first metal layers 240 . The third metal layer 270 forms mutual capacitance with the first metal layer 240 forming the gate electrode of the thin film transistor. The third metal layer 270 serves as an electrode on one side of the storage capacitance.

The second interlayer insulating film 280 is disposed on the first interlayer insulating film 260 and the third metal layer 270 . The second interlayer insulating film 280 is formed of a material having excellent electrical insulating properties.

The second metal layer 250 is disposed on the second interlayer insulating layer 280 . The second metal layer 250 forms the first electrode 251 and the second electrode 252 of the thin film transistor constituting the pixel P. The second metal layer 250 forms the first electrode 253 of the first connection transistor CT1 , an inverted enable line 254 , an enable line 255 , and a turn-on test data line 256 . The second metal layer 250 is a source/drain metal layer disposed on top of the first metal layer 240 . The second metal layer 250 may be formed of a metal or alloy having excellent electrical conductivity.

The first and second contact holes CNT1 and CNT2 are provided in the first and second interlayer insulating films 260 and 280 disposed between the first and second metal layers 240 and 250 . The first contact hole CNT1 is provided through the first and second interlayer insulating films 260 and 280 in the region where the first electrode 253 of the first connection transistor CT1 is provided. The first contact hole CNT1 connects the first electrode 253 of the first connection transistor CT1 to the first bridge 241 . The second contact hole CNT2 is provided through the first and second interlayer insulating films 260 and 280 in the region where the lighting inspection data line 256 is provided. The second contact hole CNT2 connects the lighting inspection data line 256 and the first bridge 241 . The first bridge 241 connects the first electrode 253 of the first connection transistor CT1 and the lighting test data line 256 without making electrical contact with the inversion enable line 254 and the enable line 255. They can be electrically connected to each other.

The planarization layer 290 is disposed on the second interlayer insulating layer 280 and the second metal layer 250 . The planarization layer 290 reduces the height difference of the upper surface. Accordingly, the planarization layer 290 can solve the deviation of the height in the Z-axis direction relative to the base layer 210 depending on the region.

The anode electrode 300 is disposed on the planarization film 290 . The anode electrode 300 is connected to the second electrode 252 of the thin film transistor constituting the pixel P. The anode electrode 300 supplies a driving voltage or a data voltage to the second electrode 252 of the thin film transistor. The anode electrode 300 may be classified for each pixel P. Between adjacent anode electrodes 300 may be electrically insulated due to the barrier rib 340 .

The light emitting layer 320 is provided on the anode electrode 300 . The light emitting layer 320 may include a hole transporting layer, an organic light emitting layer, and an electron transporting layer. In the light emitting layer 320, when voltage is applied to the anode electrode 300 and the cathode electrode 330, holes and electrons move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the organic light emitting layer to emit light.

The cathode electrode 330 is provided on the light emitting layer 320 and the bank 340 . The cathode electrode 330 supplies a driving voltage.

The bank 340 is provided between the anode electrodes 300 of the pixels P. The bank 340 divides the pixels P.

4 is a diagram illustrating an outer area of an organic light emitting display device according to the present application. An organic light emitting display device according to the present application includes a pixel P, a lighting test transistor TAP, an enable line ENL, a lighting test data line APDATL, a reference power supply voltage line VSSL, and a connection unit CON. include

The pixel P is disposed in a display area displaying an image. As described above, the pixel P displays an image according to the driving current flowing through the light emitting element EL. In FIG. 3 , only one pixel P disposed in the outer region of the organic light emitting diode display is illustrated.

The lighting test transistor TAP is connected to the pixel P. The lighting test transistor TAP performs a lighting test (Auto Probe, AP) of the pixel P.

A gate electrode of the lighting test transistor TAP is connected to the enable line ENL. A first electrode of the lighting test transistor TAP is connected to the data line DL constituting the pixel P. A second electrode of the lighting test transistor TAP is connected to the lighting test data line APDATL. As shown in FIG. 3 , when the lighting test transistor TAP is implemented as a P-type MOS transistor, the first electrode may be a source electrode and the second electrode may be a drain electrode. However, the present invention is not limited thereto, and when the lighting test transistor TAP is implemented as an N-type MOS transistor, the first electrode may be a drain electrode and the second electrode may be a source electrode.

The lighting test transistor TAP is turned on by the enable signal EN. When turned on, the lighting test transistor TAP supplies the lighting test data APDAT to the data line DL constituting the pixel P through the first electrode. The lighting test transistor TAP receives the lighting test data APDAT from the lighting test data line APDATL through the second electrode. The lighting inspection data APDAT causes the pixel P to display a preset image pattern. When the pixel P normally displays a preset image pattern, it can be confirmed that the pixel P is normally driven.

The enable line ENL is provided on a non-display area disposed outside the display area to surround the area where the pixel P is disposed. The enable line ENL is connected to the gate electrode of the turn-on test transistor TAP. The enable line ENL supplies an enable signal EN. The enable signal EN controls the operation of the lighting test transistor TAP. The enable signal EN turns on the lighting inspection transistor TAP in a lighting inspection period in which lighting inspection is performed. The enable signal EN turns off the lighting test transistor TAP in a driving period in which the organic light emitting diode display displays a general image after the lighting test is finished.

The lighting inspection data line APDATL is disposed outside the enable line ENL in the non-display area. The lighting test data line APDATL is connected to the first electrode of the lighting test transistor TAP. The lighting test data line APDATL supplies lighting test data APDAT for performing lighting test.

The reference power supply voltage line VSSL is disposed outside the lighting inspection data line APDATL in the non-display area. The reference power supply voltage line VSSL supplies the reference power supply voltage VSS of the pixel P. The reference power supply voltage VSS is a voltage supplied to the cathode electrode of the light emitting element EL constituting the pixel P. The reference power supply voltage VSS may be a ground (GND) voltage or a voltage having a negative (-) magnitude.

The connection unit CON is disposed between the lighting test data line APDATL and the reference power supply voltage line VSSL. The connection unit CON electrically connects the lighting test data line APDATL and the reference power supply voltage line VSSL.

When the lighting inspection data line APDATL and the reference power supply voltage line VSSL are not connected, the arrangement area of the reference power supply voltage line VSSL is relatively small. When the reference power supply voltage line VSSL has a small area and is electrically connected to other lines, the size of the reference power supply voltage VSS may be easily changed.

In addition, in a period in which the pixel P emits light, a driving voltage line VDDL for supplying the driving voltage VDD to the pixel P and a reference power supply voltage for supplying the reference power supply voltage VSS to the pixel P Both the third and fourth transistors T3 and T4 turned on by the driving transistor DT between the lines VSSL and the emission control signal EM are turned on. Accordingly, the driving voltage line VDDL and the reference power supply voltage line VSSL are electrically connected.

The magnitude of the driving voltage VDD is the largest among voltages supplied to the pixel P. Accordingly, the magnitude of the driving voltage VDD is greater than that of the reference power supply voltage VSS. At this time, when the physical size of the reference power supply voltage line VSSL is not sufficient and the driving voltage line VDDL and the reference power supply voltage line VSSL are electrically connected, the reference power supply voltage VSS rises. phenomenon occurs. A phenomenon in which the reference power supply voltage (VSS) rises is defined as an IR rising phenomenon. When the IR rising phenomenon occurs, the reference power supply voltage VSS is supplied differently for each pixel, resulting in a luminance deviation within the display area.

The present application increases the physical size of the reference power supply voltage line (VSSL) by providing a connection unit (CON) electrically connecting the lighting inspection data line (APDATL) and the reference power supply voltage line (VSSL). The lighting test data line APDATL is used only in the lighting test section in which the lighting test is performed. The lighting test data line (APDATL) is not used after performing the lighting test. Even if the organic light emitting diode display device uses the lighting test data line APDATL as a line constituting the reference power supply voltage line VSSL in a driving period for displaying an image, a driving collision does not occur.

The present application increases the physical size of the reference power supply voltage line (VSSL) by using the connection unit (CON) so that the reference power supply voltage (VSS) greatly changes even when the reference power supply voltage line (VSSL) is electrically connected to other components. can prevent In the present application, the driving transistor DT and the third and fourth transistors T3 and T4 between the driving voltage line VDDL and the reference power supply voltage line VSSL are all turned on during the period in which the pixel P emits light. However, the reference power supply voltage VSS of the reference power supply voltage line VSSL does not greatly change. Accordingly, the organic light emitting display device according to the present application can prevent an IR rising phenomenon, uniformly supply the reference power supply voltage VSS for each pixel, and reduce luminance deviation within the display area.

5 is a circuit diagram illustrating an outer area of an organic light emitting display device according to an exemplary embodiment. The organic light emitting diode display according to an example further includes a first connection transistor CT1 and an inversion enable line IENL.

The first connection transistor CT1 is disposed between the lighting test data line APDATL and the reference power supply voltage line VSSL. A gate electrode of the first connection transistor CT1 is connected to the inversion enable line IENL. A first electrode of the first connection transistor CT1 is connected to the lighting test data line APDATL. A second electrode of the lighting test transistor TAP is connected to the reference power supply voltage line VSSL. As shown in FIG. 4 , when the first connection transistor CT1 is implemented as a P-type MOS transistor, the first electrode may be a source electrode and the second electrode may be a drain electrode. However, the present invention is not limited thereto, and when the lighting test transistor TAP is implemented as an N-type MOS transistor, the first electrode may be a drain electrode and the second electrode may be a source electrode.

The inversion enable line IENL is disposed inside the enable line ENL in the non-display area. The inversion enable line IENL is connected to the gate electrode of the first connection transistor CT1. The inversion enable line IENL supplies the inversion enable signal IENL. The inverted enable signal EN_I has a phase opposite to that of the enable signal EN_I.

The enable signal EN turns on the lighting inspection transistor TAP in the lighting inspection period and turns off the lighting inspection transistor TAP in the driving period. The inverted enable signal EN_I turns off the first connection transistor CT1 in the lighting inspection period and turns on the first connection transistor CT1 in the driving period.

In the lighting inspection period, the first connection transistor CT1 is turned off, so that the lighting inspection data line APDATL and the reference power supply voltage line VSSL are electrically cut off from each other. Accordingly, in the lit test period, the lit test data line APDATL is not affected by the reference power supply voltage line VSSL. The lighting test data APDAT may be supplied to the lighting test transistor TAP without being affected by the reference power supply voltage VSS.

In the driving period, the first connection transistor CT1 is turned on, and the lighting test data line APDATL and the reference power supply voltage line VSSL are electrically connected to each other. Lighting test data (APDAT) is not supplied in the driving section. The lighting test data line APDATL is originally in a floating state that does not have a specific electrical voltage level.

When electrically connecting the lighting test data line APDATL and the reference power voltage line VSSL, the lighting test data line APDATL serves as the reference power voltage line VSSL. Accordingly, the same effect as an increase in the physical size, more specifically, the width or area of the reference power supply voltage line VSSL is obtained.

As the physical size of the reference power supply voltage line VSSL increases in the driving period, the driving transistor DT and the third and fourth transistors between the driving voltage line VDDL and the reference power supply voltage line VSSL during the driving period Even when both (T3 and T4) are turned on, the reference power supply voltage VSS of the reference power supply voltage line VSSL does not greatly change. Accordingly, the organic light emitting display device according to the present application can prevent an IR rising phenomenon, uniformly supply the reference power supply voltage VSS for each pixel, and reduce luminance deviation within the display area.

6 is a plan view illustrating an outer area of an organic light emitting display device according to an exemplary embodiment. An organic light emitting display device according to an example includes first and second bridges BR1 and BR2 and first to fourth contact holes CNT1 to CNT4.

The first bridge BR1 connects the first connection transistor CT1 and the lighting test data line APDATL. One side of the first bridge BR1 is connected to the first electrode of the first connection transistor CT1. The other side of the first bridge BR1 is connected to the lighting inspection data line APDATL. The first electrode of the first connection transistor CT1 and one side of the first bridge BR1 are connected through the first contact hole CNT1. The lighting inspection data line APDATL and the other side of the first bridge BR1 are connected through the second contact hole CNT2.

The second bridge BR2 connects the first connection transistor CT1 and the reference power supply voltage line VSSL. One side of the second bridge BR2 is connected to the second electrode of the first connection transistor CT1. The other side of the second bridge BR2 is connected to the reference power supply voltage line VSSL. The second electrode of the first connection transistor CT1 and one side of the second bridge BR2 are connected through the third contact hole CNT3. The reference power supply voltage line VSSL and the other side of the second bridge BR2 are connected through the fourth contact hole CNT4.

FIG. 7 is a cross-sectional view taken along line Ⅰ-Ⅰ′ of FIG. 6 . An organic light emitting display device according to an embodiment includes a base layer 210, a buffer layer 220, a semiconductor layer 230, a gate insulating layer 235, a first metal layer 240, a first bridge 241, and a second metal layer. 250 , a first interlayer insulating film 260 , a third metal layer 270 , a second interlayer insulating film 280 , a planarization film 290 , and an anode electrode 300 .

The base layer 210 forms the lowest layer of the organic light emitting display device. The base layer 210 may support circuit elements and wires constituting the circuit unit provided thereon. Alternatively, the base layer 210 may be formed of flexible plastic to make the organic light emitting display device flexible.

The buffer layer 220 covers the top of the base layer 210 . The buffer layer 220 is formed of a material having excellent insulating properties. The buffer layer 220 protects circuit elements and wires constituting the circuit unit provided on the base layer 210 from external impact or static electricity.

The semiconductor layer 230 is disposed on top of the buffer layer 220 . The semiconductor layer 230 is made of a doped semiconductor. The semiconductor layer 230 forms a channel of a thin film transistor constituting the pixel P. The semiconductor layer 230 includes a gate channel 231 , a first channel 232 , and a second channel 233 . The gate channel 231 forms a channel of a gate electrode of a thin film transistor. The first and second electrode layers 233 form channels of the source and drain electrodes of the thin film transistor.

The gate insulating layer 235 is disposed on the buffer layer 220 and the semiconductor layer 230 . The gate insulating layer 235 entirely covers the buffer layer 220 and the semiconductor layer 230 . The gate insulating layer 235 is formed of a material having excellent insulating properties. The gate insulating layer 235 prevents the semiconductor layer 230 from being short-circuited with the first metal layer 240 and separates channels of thin film transistors formed by the semiconductor layer 230 .

The first metal layer 240 is disposed on top of the gate insulating layer 235 . The first metal layer 240 is a gate metal layer forming gate electrodes and gate lines GL1 to GLp of the thin film transistor. The first metal layer 240 may be formed of a metal or alloy having excellent electrical conductivity.

The first bridge 241 is disposed on the gate insulating layer 235 . The first bridge 241 is made of the first metal layer 240 . That is, the first bridge 241 is formed using the same material on the same layer as the layer forming the gate electrodes and gate lines GL1 to GLp of the thin film transistor.

The first interlayer insulating film 260 is disposed on the first metal layer 240 and the first bridge 241 . The first interlayer insulating film 260 is formed of a material having excellent electrical insulating properties.

The third metal layer 270 is disposed on the first interlayer insulating layer 260 . The third metal layer 270 is disposed overlapping the first metal layer 240 forming the gate electrode of the thin film transistor among the first metal layers 240 . The third metal layer 270 forms mutual capacitance with the first metal layer 240 forming the gate electrode of the thin film transistor. The third metal layer 270 serves as an electrode on one side of the storage capacitance.

The second interlayer insulating film 280 is disposed on the first interlayer insulating film 260 and the third metal layer 270 . The second interlayer insulating film 280 is formed of a material having excellent electrical insulating properties.

The second metal layer 250 is disposed on the second interlayer insulating layer 280 . The second metal layer 250 forms the first electrode 251 and the second electrode 252 of the thin film transistor constituting the pixel P. The second metal layer 250 forms the first electrode 253 of the first connection transistor CT1 , an inverted enable line 254 , an enable line 255 , and a turn-on test data line 256 . The second metal layer 250 is a source/drain metal layer disposed on top of the first metal layer 240 . The second metal layer 250 may be formed of a metal or alloy having excellent electrical conductivity.

The first and second contact holes CNT1 and CNT2 are provided in the first and second interlayer insulating films 260 and 280 disposed between the first and second metal layers 240 and 250 . The first contact hole CNT1 is provided through the first and second interlayer insulating films 260 and 280 in the region where the first electrode 253 of the first connection transistor CT1 is provided. The first contact hole CNT1 connects the first electrode 253 of the first connection transistor CT1 to the first bridge 241 . The second contact hole CNT2 is provided through the first and second interlayer insulating films 260 and 280 in the region where the lighting inspection data line 256 is provided. The second contact hole CNT2 connects the lighting inspection data line 256 and the first bridge 241 . The first bridge 241 connects the first electrode 253 of the first connection transistor CT1 and the lighting test data line 256 without making electrical contact with the inversion enable line 254 and the enable line 255. They can be electrically connected to each other.

The planarization layer 290 is disposed on the second interlayer insulating layer 280 and the second metal layer 250 . The planarization layer 290 reduces the height difference of the upper surface. Accordingly, the planarization layer 290 can solve the deviation of the height in the Z-axis direction relative to the base layer 210 depending on the region.

The anode electrode 300 is disposed on the planarization film 290 . The anode electrode 300 is connected to the second electrode 252 of the thin film transistor constituting the pixel P. The anode electrode 300 supplies a driving voltage or a data voltage to the second electrode 252 of the thin film transistor.

FIG. 8 is a cross-sectional view taken along line II-II′ of FIG. 6 . An organic light emitting display device according to an embodiment includes a base layer 210, a buffer layer 220, a gate insulating layer 235, a second bridge 242, a second metal layer 250, a first interlayer insulating layer 260, A two-layer insulating layer 280 and a planarization layer 290 are included. The structures and functions of the base layer 210, the buffer layer 220, the gate insulating layer 235, the first interlayer insulating film 260, the second interlayer insulating film 280, and the planarization film 290 are described with reference to FIG. 6. Since it is the same as described, the description thereof will be omitted below.

The second bridge 242 is disposed on the gate insulating layer 235 . The second bridge 242 is provided with the first metal layer 240 . That is, the second bridge 242 is formed using the same material on the same layer as the layer forming the gate electrodes and gate lines GL1 to GLp of the thin film transistor.

The second metal layer 250 is disposed on the second interlayer insulating layer 280 . The second metal layer 250 includes the first electrode 253 of the first connection transistor CT1 , the inverted enable line 254 , the enable line 255 , the lighting test data line 256 , and the reference power supply voltage line. (257). The second metal layer 250 is a source/drain metal layer disposed on top of the first metal layer 240 . The second metal layer 250 may be formed of a metal or alloy having excellent electrical conductivity.

The third and fourth contact holes CNT3 and CNT4 are provided in the first and second interlayer insulating films 260 and 280 disposed between the first and second metal layers 240 and 250 . The third contact hole CNT3 is provided through the first and second interlayer insulating films 260 and 280 in the region where the second electrode 253 of the first connection transistor CT1 is provided. The third contact hole CNT3 connects the second electrode 253 of the first connection transistor CT1 to the second bridge 242 . The fourth contact hole CNT4 is provided through the first and second interlayer insulating films 260 and 280 in the region where the reference power supply voltage line 257 is provided. The fourth contact hole CNT4 connects the reference power supply voltage line 257 and the second bridge 242 . The second bridge 242 does not electrically contact the inverted enable line 254, the enable line 255, and the lighting test data line 256, and the second electrode 253 of the first connection transistor CT1. and the reference power supply voltage line 257 may be electrically connected to each other.

9 is a circuit diagram illustrating an outer area of an organic light emitting display device according to another example.

The lighting test data line APDATL of the organic light emitting diode display according to another example includes a first line pattern LP1 and a second line pattern LP2. The first and second line patterns LP1 and LP2 are spaced apart from each other. The first line pattern LP1 receives lighting inspection data APDAT. The second line pattern LP2 is connected to the second electrode of the lighting test transistor TAP and the first electrode of the first connection transistor CT1. The second line pattern LP2 supplies the lighting test data APDAT to the lighting test transistor TAP.

Also, the organic light emitting diode display according to another example further includes a second connection transistor CT2 . A gate electrode of the second connection transistor CT2 is connected to the enable line ENL. A first electrode of the second connection transistor CT2 is connected to the first line pattern LP1. The second electrode of the second connection transistor CT2 is connected to the second line pattern LP1. When the second connection transistor CT2 is implemented as a P-type MOS transistor, the first electrode may be a source electrode and the second electrode may be a drain electrode. However, it is not limited thereto, and when the second connection transistor CT2 is implemented as an N-type MOS transistor, the first electrode may be a drain electrode and the second electrode may be a source electrode.

The second connection transistor CT2 is turned on by the enable signal EN in the lighting inspection period. The turned-on second connection transistor CT2 may connect the first line pattern LP1 and the second line pattern LP2. In the lighting inspection period, the first line pattern LP1 may supply the lighting inspection data APDAT to the second line pattern LP2. The second line pattern LP2 may supply the lighting test data APDAT to the first electrode of the lighting test transistor TAP.

The second connection transistor CT2 is turned off during the driving period. The turned-off second connection transistor CT2 may block the first line pattern LP1 and the second line pattern LP2. In the driving period, the first line pattern LP1 cannot supply a signal or voltage to the second line pattern LP2. The second line pattern LP2 does not supply a signal or voltage to the voltage lighting test transistor TAP.

When the second connection transistor CT2 is additionally disposed, the lighting inspection data APDAT in a floating state is transmitted in the driving period in the first line pattern LP1 constituting the lighting test data line APDATL. ) or to the first control transistor CT1. Accordingly, it is possible to prevent a phenomenon in which the lighting test data APDAT in a floating state is supplied to the pixel P through the lighting test transistor TAP in the driving period. In addition, it is possible to prevent a phenomenon in which the lighting test data APDAT in a floating state is supplied to the reference power supply voltage line VSSL through the first control transistor CT1 in the driving period and affects the reference power supply voltage VSS. .

10 is a plan view illustrating an outer area of an organic light emitting display device according to another example.

An organic light emitting display device according to another example includes a third bridge BR3 and a fourth bridge BR4 .

The third bridge BR3 connects the second connection transistor CT2 and the second line pattern LP2. One side of the third bridge BR3 is connected to the second line pattern LP2. The other side of the third bridge BR3 is connected to the first electrode of the second connection transistor CT2.

The fourth bridge BR4 connects the second connection transistor CT2 and the first line pattern LP1. One side of the fourth bridge BR4 is connected to the first line pattern LP1. The other side of the fourth bridge BR4 is connected to the second electrode of the second connection transistor CT2.

The second connection transistor CT2 is disposed on the non-display area. The second connection transistor CT2 is disposed between the pixel P and the inversion enable line IENL. Accordingly, the second connection transistor CT2 may be added without additionally increasing the width of the non-display area.

FIG. 11 is a cross-sectional view taken along line III-III′ of FIG. 10 . An organic light emitting display device according to another example includes a base layer 210, a buffer layer 220, a gate insulating layer 235, a third bridge 243, a second metal layer 250, a first interlayer insulating layer 260, It includes a two-layer insulating film 280, a planarization film 290, and an anode electrode 300. The structures and functions of the base layer 210, the buffer layer 220, the gate insulating layer 235, the first interlayer insulating film 260, the second interlayer insulating film 280, the planarization film 290, and the anode electrode 300 are Since it is the same as that described in connection with FIG. 6, the description thereof will be omitted below.

The third bridge 243 is disposed on the gate insulating layer 235 . The third bridge 243 is provided with the first metal layer 240 . That is, the third bridge 243 is formed using the same material on the same layer as the layer forming the gate electrodes and gate lines GL1 to GLp of the thin film transistor.

The second metal layer 250 is disposed on the second interlayer insulating layer 280 . The second metal layer 250 forms the first electrode 253 of the second connection transistor CT2 , an inversion enable line 254 , an enable line 255 , and a turn-on test data line 256 . The second metal layer 250 is a source/drain metal layer disposed on top of the first metal layer 240 . The second metal layer 250 may be formed of a metal or alloy having excellent electrical conductivity.

The fifth and sixth contact holes CNT5 and CNT6 are provided in the first and second interlayer insulating films 260 and 280 disposed between the first and second metal layers 240 and 250 . The fifth contact hole CNT5 is provided through the first and second interlayer insulating films 260 and 280 in the region where the first electrode 253 of the second connection transistor CT2 is provided. The fifth contact hole CNT5 connects the first electrode 253 of the second connection transistor CT2 and the third bridge 243. The sixth contact hole CNT6 is provided through the first and second interlayer insulating films 260 and 280 in the region where the lighting inspection data line 256 is provided. The sixth contact hole CNT6 connects the lighting inspection data line 256 and the third bridge 243 . The third bridge 243 connects the first electrode 253 of the second connection transistor CT2 and the lighting test data line 256 without making electrical contact with the inverted enable line 254 and the enable line 255. They can be electrically connected to each other.

In the same structure as above, the seventh and eighth contact holes CNT7 and CNT8 are provided in the first and second interlayer insulating films 260 and 280 disposed between the first and second metal layers 240 and 250 . The seventh contact hole CNT7 is provided through the first and second interlayer insulating films 260 and 280 in the region where the second electrode of the second connection transistor CT2 is provided. The seventh contact hole CNT7 connects the second electrode of the second connection transistor CT2 and the fourth bridge BR4. The eighth contact hole CNT8 is provided through the first and second interlayer insulating films 260 and 280 in the region where the lighting test data line APDATL is provided. The eighth contact hole CNT8 connects the lighting inspection data line APDATL and the fourth bridge BR4. The fourth bridge BR4 electrically connects the second electrode of the second connection transistor CT2 and the lighting test data line APDATL without making electrical contact with the inverted enable line IENL and the enable line ENL. can be connected

12 is a circuit diagram illustrating an outer area of an organic light emitting display device according to another example.

An organic light emitting diode display according to another example further includes a conductive pattern CP. In the organic light emitting diode display according to another example, the connection unit CON is implemented as the conductive pattern CP, and no additional line or component such as a transistor is added. Accordingly, the organic light emitting diode display according to another example may reduce manufacturing cost and simplify a design process.

The conductive pattern CP is disposed between the lighting test data line APDATL and the reference power supply voltage line VSSL. The conductive pattern CP connects the lighting inspection data line APDATL and the reference power supply voltage line VSSL. The conductive pattern CP may be implemented by a metal patterning method such as an Ag dotting pattern. The lighting test data line APDATL and the reference power supply voltage line VSSL connected by the conductive pattern CP become the reference power supply voltage line VSSL having a physically thicker thickness.

13 is a plan view illustrating an outer area of an organic light emitting display device according to another example.

The conductive pattern CP is disposed on an upper layer of the lighting inspection data line APDATL and the reference power supply voltage line VSSL. The conductive pattern CP connects the lighting inspection data line APDATL and the reference power supply voltage line VSSL.

FIG. 14 is a cross-sectional view taken along line IV-IV` of FIG. 13 . An organic light emitting diode display according to another example includes a base layer 210, a buffer layer 220, a gate insulating layer 235, a second metal layer 250, a first insulating interlayer 260, and a second insulating interlayer 280. , a planarization film 290 , and an upper metal layer 310 . Since the structure and function of the base layer 210, the buffer layer 220, the gate insulating layer 235, the first interlayer insulating film 260, and the second interlayer insulating film 280 are the same as those described in connection with FIG. 6, hereinafter In this case, the description thereof will be omitted.

The second metal layer 250 is disposed on the second interlayer insulating layer 280 . The second metal layer 250 forms a lighting test data line 256 and a reference power supply voltage line 257 . The second metal layer 250 is a source/drain metal layer. The second metal layer 250 may be formed of a metal or alloy having excellent electrical conductivity.

The planarization layer 290 is disposed on the second interlayer insulating layer 280 and the second metal layer 250 . The planarization layer 290 reduces the height difference of the upper surface. Accordingly, the planarization layer 290 can solve the deviation of the height in the Z-axis direction relative to the base layer 210 depending on the region.

The upper metal layer 310 is disposed on the planarization layer 290 . The upper metal layer 310 forms the conductive pattern CP. When the conductive pattern CP is formed as the upper metal layer 310 , the lighting inspection data line 256 and the reference power supply voltage line 257 may be connected after the process of forming the planarization film 290 .

A planarization layer 290 is disposed between the second metal layer 250 as a source/drain metal layer and the upper metal layer 310 . Accordingly, the upper metal layer 310 can be stably formed on the flat upper surface.

15 illustrates an enable signal (EN), a lighting test data (APDAT), an inverted enable signal (EN_I), and digital video data (DATA) in a lighting inspection area and a driving area of an organic light emitting diode display according to the present application. It is the waveform diagram shown. In the waveform diagram, the first logic level (L1) is a high (H) logic level, the second logic level (L2) is a low (L) logic level, and the third logic level is a floating (X) This is the logic level. The size of the second logic level is smaller than the size of the first logic level. The size of the third logic level has an arbitrary size between the size of the first logic level and the size of the second logic level.

Also, FIG. 15 illustrates a case in which the lighting check transistor TAP and the first and second control transistors CT1 and CT2 are implemented as P-type MOS transistors. The P-type MOS transistor is turned off when the first logic level L1 is supplied to the gate electrode and turned on when the second logic level L2 is supplied to the gate electrode. However, it is not necessarily limited thereto, and when the lighting check transistor TAP and the first and second control transistors CT1 and CT2 are implemented as N-type MOS transistors, the first and second logic levels L1 and CT2 as shown in FIG. The same driving may be performed by supplying waveforms in which the magnitude relationship of L2) is inverted.

The enable signal EN has a second logic level L2 in the lighting inspection period AP. The enable signal EN has a first logic level L1 in the driving period DR. The enable signal EN turns on the lighting inspection transistor TAP in the lighting inspection period AP. The lighting test transistor TAP may supply the lighting test data APDAT to the pixel P in response to the enable signal EN. The enable signal EN turns off the lighting check transistor TAP in the driving period DR. Accordingly, the lighting inspection transistor TAP can be turned off by using the enable signal EN in the driving period DR during image display after completion of the lighting inspection.

The lighting test data APDAT has first and second logic levels L1 and L2 alternately in the lighting test period AP. The lighting inspection data APDAT causes the pixel P to display the set image pattern in the lighting inspection period AP. The lighting test data APDAT has a third logic level L3 in the driving period DR.

Since the lighting test transistor TAP is turned off using the enable signal EN, the lighting test data APDAT can maintain the third logic level L3. That is, the organic light emitting diode display according to an example turns off the lighting test transistor TAP using the enable signal EN to maintain the lighting test data line APDATL in a floating state. Accordingly, it is possible to prevent a phenomenon in which the lighting inspection data APDAT is supplied to the pixel P in the driving period DR.

The inverted enable signal EN_I has a first logic level L1 in the lighting inspection period AP. The inversion enable signal EN_I has a second logic level L2 in the driving period DR. That is, the inverted enable signal EN_I has an inverted phase of the enable signal EN.

The inverted enable signal EN_I turns off the first connection transistor CT1 in the lighting inspection period AP. Accordingly, the inverted enable signal EN_I blocks the connection between the lit test data line APDATL and the reference power supply voltage line VSSL in the lit test period AP. Accordingly, it is possible to prevent a phenomenon in which the size of the lit test data APDAT is changed by the reference power supply voltage VSS in the lit test period AP.

The digital video data DATA has a third logic level L3 in the lighting inspection period AP. The digital video data DATA has first and second logic levels L1 and L2 alternately in the driving period DR. The digital video data DATA includes information allowing the pixel P to display an image according to a predetermined grayscale in the driving period DR.

The lighting test data APDAT supplied during the lighting test period AP of the organic light emitting display device according to an example is digital video data supplied during the driving period DR displaying an image after the lighting test is completed. It is different from (DATA).

The lighting inspection data APDAT is supplied from the lighting inspection data line APDATL during the lighting inspection period AP, and a set pattern is displayed to check whether the pixel is driven abnormally. On the other hand, the digital video data DATA is supplied to the plurality of data lines DL during the driving period DR and is supplied for each pixel P to display an image according to the grayscale set in the corresponding pixel P. make it possible Accordingly, as shown in FIG. 15, the lighting inspection data APDAT and the digital video data DATA are different in supply time, supply path, and function to be performed.

The inversion enable signal EN_I turns on the first connection transistor CT1 in the driving period DR. The organic light emitting diode display device according to an example turns on the first connection transistor CT1 by using the inversion enable signal EN_I during the driving period DR in which an image is displayed after completion of the lighting test.

The first connection transistor CT1 electrically connects the lighting test data line APDATL and the reference power supply voltage line VSSL during the driving period DR. During the driving period DR, the reference power supply voltage VSS may be supplied to the lit test data line APDATL, which was previously in a floating state. The reference power supply voltage VSS is supplied to the turned-on test data line APDATL, and the area or width of the line having the reference power supply voltage VSS may be increased. Accordingly, even if the reference power supply voltage line VSSL is electrically connected to the driving voltage line VDDL of the pixel P during the driving period DR, the amount of change in the reference power supply voltage VSS may be reduced.

In the present application, the physical size of the reference power supply voltage line is increased by electrically connecting the lighting inspection data line and the reference power supply voltage line. As the physical size of the reference power supply voltage line increases, even if the driving voltage line and the reference power supply voltage line are electrically connected in a period in which pixels emit light, an IR rising phenomenon in which the reference power supply voltage increases can be prevented.

Through the above description, those skilled in the art will know that various changes and modifications are possible without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: gate driver
120: data driver 130: timing controller
P: Pixel DT: Driving Transistor
EL: light emitting element Cst: storage capacitor
T1 to T6: 1st to 6th transistors TAP: lighting check transistor
ENL: enable line APDATL: lit test data line
VSSL: reference supply voltage line CON: connection
CT1, CT2: first and second connecting transistors
IENL: inversion enable line BR1 to BR4: first to fourth bridges
CNT1 to CNT8: first to eighth contact holes CP: conductive pattern
210: base layer 220: buffer layer
230: semiconductor layer 235: gate insulating layer
240: first metal layer 241 to 243: first to third bridges
250: second metal layer 260: first interlayer insulating film
270: third metal layer 280: second interlayer insulating film
290: planarization film 300: anode electrode
310: upper metal layer

Claims (14)

pixels displaying images;
a lighting test transistor connected to the pixel to perform a lighting test;
an enable line supplying an enable signal for turning on the lit test transistor;
a lighting inspection data line supplying lighting inspection data for performing the lighting inspection;
a reference power supply voltage line supplying a reference power supply voltage of the pixel; and
a connection unit electrically connecting the lighting test data line and the reference power supply voltage line;
a first connection transistor disposed between the turn-on test data line and the reference power supply voltage line; and
An inversion enable line supplying an inversion enable signal to a gate electrode of the first connection transistor;
The lighting test data line includes a first line pattern and a second line pattern spaced apart from each other,
and a second connection transistor turned on by the enable signal to connect the first line pattern and the second line pattern. delete According to claim 1,
a first bridge connected to one side of the first electrode of the first connection transistor; and
A second bridge having one side connected to the second electrode of the first connection transistor,
The other side of the first bridge is connected to the lighting test data line,
The other side of the second bridge is connected to the reference power supply voltage line. According to claim 3,
The first and second bridges are provided with a first metal layer,
The lighting test data line, the reference power supply voltage line, and first and second electrodes of the first connection transistor are provided with a second metal layer disposed on the first metal layer,
A first electrode of the first connection transistor and one side of the first bridge are connected through a first contact hole;
The lighting inspection data line and the other side of the first bridge are connected through a second contact hole;
A second electrode of the first connection transistor and one side of the second bridge are connected through a third contact hole;
The organic light emitting display device of claim 1 , wherein the reference power supply voltage line and the other side of the second bridge are connected through a fourth contact hole. According to claim 4,
The first metal layer is a gate metal layer,
The second metal layer is a source/drain metal layer,
The first to fourth contact holes are provided in first and second interlayer insulating films disposed between the first and second metal layers. delete According to claim 1,
a third bridge having one side connected to the second line pattern; and
A fourth bridge having one side connected to the first line pattern,
The first electrode of the second connection transistor is connected to the other side of the third bridge,
The second electrode of the second connection transistor is connected to the other side of the fourth bridge. According to claim 7,
The third and fourth bridges are provided with a first metal layer,
The first line pattern, the second line pattern, and the first and second electrodes of the second connection transistor are provided with a second metal layer disposed on the first metal layer,
The first electrode of the second connection transistor and one side of the third bridge are connected through a fifth contact hole;
The second line pattern and the other side of the third bridge are connected through a sixth contact hole;
The second electrode of the second connection transistor and the other side of the fourth bridge are connected through a seventh contact hole;
The organic light emitting display device of claim 1 , wherein the first line pattern and the other side of the fourth bridge are connected through an eighth contact hole. According to claim 8,
The first metal layer is a gate metal layer,
The second metal layer is a source/drain metal layer,
The fifth to eighth contact holes are provided in first and second interlayer insulating films disposed between the first and second metal layers. pixels displaying images;
a lighting test transistor connected to the pixel to perform a lighting test;
an enable line supplying an enable signal for turning on the lit test transistor;
a lighting inspection data line supplying lighting inspection data for performing the lighting inspection;
a reference power supply voltage line supplying a reference power supply voltage of the pixel; and
A connection portion electrically connecting the lighting test data line and the reference power supply voltage line;
The lighting test data line and the reference power supply voltage line are connected by a conductive pattern disposed on an upper layer of the lighting test data line and the reference power supply voltage line. According to claim 10,
The lighting inspection data line and the reference power supply voltage line are provided as source/drain metal layers,
The conductive pattern is provided as an upper metal layer,
An organic light emitting display device comprising a planarization layer disposed between the source/drain metal layer and the upper metal layer. According to claim 1 or 10,
Lighting test data supplied during the lighting test is different from digital video data supplied while displaying the image after completion of the lighting test. According to claim 1 or 10,
and turning off the lighting test transistor using the enable signal and maintaining the lighting test data line in a floating state while displaying the image after completion of the lighting test. According to claim 1,
and turning on the first connection transistor using the inversion enable signal while displaying the image after completion of the lighting test.

Images