KR102400339B1 - Semiconductor device and semiconductor device package - Google Patents

Abstract

The semiconductor device includes a first conductivity type semiconductor layer, an active layer disposed on the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer disposed on the active layer.
The first conductivity type semiconductor layer may include a 1-1 conductivity type semiconductor layer having a first recess concave in the first direction on its upper surface. The second conductivity type semiconductor layer may include a second recess disposed on an upper surface thereof, and the first recess and the second recess may overlap in a first direction.

Description

Semiconductor device and semiconductor device package

The embodiment relates to a semiconductor device and a semiconductor device package.

A semiconductor device containing a compound such as GaN or AlGaN has many advantages, such as having a wide and easily adjustable band gap energy, and thus can be used in various ways as a light emitting device, a light receiving device, and various diodes.

In particular, light emitting devices such as light emitting diodes or laser diodes using group 3-5 or group 2-6 compound semiconductor materials of semiconductors have developed red, green, and Various colors such as blue and ultraviolet light may be implemented. In the light emitting device, efficient white light can be realized by using a fluorescent material or combining colors. These light emitting devices have advantages of low power consumption, semi-permanent lifespan, fast response speed, safety, and environmental friendliness compared to conventional light sources such as fluorescent lamps and incandescent lamps.

For example, among light emitting devices, nitride semiconductors are receiving great attention in the field of optical devices and high-output electronic devices due to their high thermal stability and wide bandgap energy. In particular, a blue light emitting device, a green light emitting device, an ultraviolet (UV) light emitting device, and a red light emitting device using a nitride semiconductor have been commercialized and widely used.

Recently, as the demand for high-efficiency LEDs increases, luminous intensity improvement has become an issue, but satisfactory luminous intensity improvement has not yet been implemented.

The embodiment provides a semiconductor device and a semiconductor device package capable of increasing luminous intensity.

The embodiment provides a semiconductor device and a semiconductor device package capable of improving light efficiency.

The embodiment provides a semiconductor device and a semiconductor device package capable of improving light extraction efficiency.

The embodiment provides a semiconductor device and a semiconductor device package that do not require a separate additional process to improve light extraction efficiency.

A semiconductor device according to an embodiment includes a first conductivity type semiconductor layer; an active layer disposed on the first conductivity-type semiconductor layer; and a second conductivity-type semiconductor layer disposed on the active layer. The first conductivity type semiconductor layer may include a 1-1 conductivity type semiconductor layer having a first recess concave in the first direction on an upper surface thereof. The first direction may be a direction from the second conductivity type semiconductor layer to the first conductivity type semiconductor layer. The second conductivity type semiconductor layer may include a second recess disposed on an upper surface thereof. The first recess and the second recess may overlap in the first direction.

A semiconductor device package according to an embodiment includes a body having a cavity; first and second leadframes within the body; and the semiconductor device.

According to the embodiment, a recess is formed in the active layer and the p-type semiconductor layer is disposed in the recess, so that holes of the p-type semiconductor layer are easily injected into the active layer, and light from the active layer is easily transmitted to the outside through the recess of the active layer As a result, the operating voltage may be lowered, the luminous intensity may be increased, and the luminous efficiency may be improved.

According to the embodiment, when the second semiconductor layer is grown using MOCVD equipment, a recess is naturally formed in the p-type semiconductor layer disposed on the active layer by the recess of the semiconductor layer disposed under the active layer, so that the light of the active layer is Since it can be easily extracted to the outside, light extraction efficiency can be improved.

According to an embodiment, since the recess of the p-type semiconductor layer is naturally formed by an in-situ process, a separate additional process is not required, thereby simplifying the process and reducing the process cost.

1 shows a semiconductor device according to a first embodiment.
2 shows the third semiconductor layer in detail.
3 shows the fifth semiconductor layer in detail.
4 shows the luminous intensity according to the aluminum (Al) content of the fifth semiconductor layer.
5 shows a horizontal type semiconductor device.
6 illustrates a semiconductor device package according to an embodiment.

In the description of the embodiment, in the case where each element is described as being formed on "on or under", under) includes both elements in which two elements are in direct contact with each other or in which one or more other elements are disposed between the two elements indirectly. In addition, when expressed as "up (up) or down (on or under)", the meaning of the downward direction as well as the upward direction based on one configuration may be included.

The semiconductor device may include various electronic devices such as a light emitting device and a light receiving device, and both the light emitting device and the light receiving device may include a light emitting structure including at least a first semiconductor layer, an active layer, and a second semiconductor layer. The semiconductor device according to the embodiment may be a light emitting device. The light emitting device emits light by recombination of first carriers, that is, electrons, and second carriers, that is, holes, and the wavelength of this light is determined by the material's inherent bandgap energy. . Accordingly, the emitted light may vary depending on the composition of the material.

Instead of the light emitting device, it may be referred to as a semiconductor light emitting device.

Terms may correspond as follows between the claims and the following description.

That is, the first conductivity type semiconductor layer of the claims may include a first semiconductor layer 15 , a third semiconductor layer 17 , and a fourth semiconductor layer 19 . The 1-1 conductivity type semiconductor layer of the claims may be the third semiconductor layer 17 . The second conductivity type semiconductor layer of the claims may be the second semiconductor layer 25 , and the third conductivity type semiconductor layer of the claims may be the fifth semiconductor layer 23 .

(Semiconductor device structure)

1 shows a semiconductor device according to a first embodiment.

Referring to FIG. 1 , the semiconductor device according to the first embodiment includes a first semiconductor layer 15 , an active layer 21 disposed on the first semiconductor layer 15 , and a second semiconductor disposed on the active layer 21 . layer 25 may be included.

The first semiconductor layer 15 , the active layer 21 , and the second semiconductor layer 25 may constitute a light emitting structure. When an electric signal is supplied to the light emitting structure, light corresponding to the electric signal may be generated and emitted from the light emitting structure. The intensity of the light may be proportional to the intensity of the electric signal.

The first semiconductor layer 15 may be, for example, an n-type semiconductor layer, and the second semiconductor layer 25 may be a p-type semiconductor layer, but is not limited thereto. The n-type semiconductor layer may include, for example, electrons as a majority carrier. The p-type semiconductor layer may include holes as majority carriers, for example.

When an electric signal is supplied to the light emitting structure, electrons of the first semiconductor layer 15 and holes of the second semiconductor layer 25 may be injected into the active layer 21 . Holes and electrons recombine in the active layer 21 to emit light in a wavelength region corresponding to the band gap energy of the active layer 21 . The bandgap energy may be determined depending on the compound semiconductor material. For example, ultraviolet light to infrared light may be emitted depending on the compound semiconductor material of the active layer 21 .

One or more layers may be added under the light emitting structure, on the light emitting structure and/or in the light emitting structure to improve electrical and optical properties.

For example, the buffer layer 13 may be disposed under the first semiconductor layer 15 . For example, a third semiconductor layer 17 and a fourth semiconductor layer 19 may be disposed between the first semiconductor layer 15 and the active layer 21 . For example, the fifth semiconductor layer 23 may be disposed between the active layer 21 and the second semiconductor layer 25 .

The third semiconductor layer 17 may be a middle temperature (MT) layer. Here, the intermediate temperature may be a temperature for forming the third semiconductor layer 17 , and the growth temperature of the third semiconductor layer 17 may be lower than the growth temperature of the first semiconductor layer 15 or the active layer 21 . there is.

Growth rates in the vertical and horizontal directions are controlled by controlling the temperature during growth of the third semiconductor layer 17, controlling the indium (In) content, and controlling the thickness of each sub-semiconductor layer (see 17a and 17b in FIG. 2 ). Thus, a recess 18 may be formed, and for example, a side surface of the recess 18 may have a shape of a V-pit.

In this way, the recess 18 is formed so that the semiconductor layers 19, 21, 23, 25 formed on the recess 18 are grown in the vertical direction as well as in the vertical direction, so that the third semiconductor layer ( 17), dislocations proceeding in the upward direction are bent in the horizontal direction to block the vertical dislocations from proceeding, so that the film quality can be improved.

The width and/or size of the recess 18 may gradually increase from a lower portion to an upper portion of the third semiconductor layer 17 . The side of the recess 18 may have, but is not limited to, a straight face.

The fourth semiconductor layer 19 may be a strain relaxation layer or a current spreading layer (CSL). The fourth semiconductor layer 19 may rapidly spread the current along the horizontal direction. The fourth semiconductor layer 19 relieves stress to prevent defects such as cracks in the semiconductor device.

The fifth semiconductor layer 23 may be an electron blocking layer (EBL). The fifth semiconductor layer 23 is an active layer 21 in which electrons injected from the first semiconductor layer 15 into the active layer 21 are ) may be blocked from moving to the second semiconductor layer 25 .

Typically, the mobility of electrons may be 10 to 1000 times higher than the mobility of holes. Accordingly, compared to the probability of recombination of electrons injected from the first semiconductor layer 15 into the active layer 21 with holes injected from the second semiconductor layer 25 into the active layer 21 , the electrons passed through the active layer 21 to the second semiconductor Implantation into layer 25 may result in a high probability of non-luminescent recombination. As such, the electrons are not used for recombination in the active layer 21 and are injected into the second semiconductor layer 25 to achieve non-luminescent recombination. As the probability of non-luminescent recombination is increased, the light generation efficiency may be lowered, and consequently, the luminous intensity may be lowered.

Accordingly, since the fifth semiconductor layer 23 is disposed between the active layer 21 and the second semiconductor layer 25 , electrons injected from the first semiconductor layer 15 into the active layer 21 are no longer transferred to the second semiconductor layer. It is not moved to (25), so that the luminous intensity can be increased.

These semiconductor layers, that is, the buffer layer 13 , the first to fifth semiconductor layers 15 , 25 , 17 , 19 , and 23 , and the active layer 21 may be disposed on the substrate 11 . In other words, the buffer layer 13, the first semiconductor layer 15, the third semiconductor layer 17, the fourth semiconductor layer 19, the active layer 21, the fifth semiconductor layer 23, and the second semiconductor layer ( 25) may be sequentially grown on the substrate by a deposition process. That is, after the substrate is loaded into the chamber of the deposition equipment, the buffer layer 13 , the first semiconductor layer 15 , the third semiconductor layer 17 , the fourth semiconductor layer 19 , the active layer 21 , and the fifth semiconductor The layer 23 and the second semiconductor layer 25 may be sequentially grown. By growing in this way, the semiconductor device according to the first embodiment can be manufactured. Thereafter, the substrate may be taken out of the chamber of the deposition equipment.

As the deposition equipment, for example, MOCVD (Metal Organic Chemical Vapor Deposition) equipment, CVD equipment (Chemical Vapor Deposition), PECVD equipment (Plasma-Enhanced Chemical Vapor Deposition), MBE equipment (Molecular Beam Epitaxy), HVPE equipment (Hydride Vapor Phase Epitaxy) ) may be used, but is not limited thereto.

(Material properties of semiconductor devices)

The substrate includes a buffer layer 13 , a first semiconductor layer 15 , a third semiconductor layer 17 , a fourth semiconductor layer 19 , an active layer 21 , a fifth semiconductor layer 23 , and a second semiconductor layer 25 . ) while growing the buffer layer 13 , the first semiconductor layer 15 , the third semiconductor layer 17 , the fourth semiconductor layer 19 , the active layer 21 , the fifth semiconductor layer 23 and the second semiconductor It may serve to support the layer 25 .

To this end, the substrate may be formed of a material suitable for growth of a Group 3-5 or Group 2-6 compound semiconductor material. The substrate may be formed of, for example, a material having a lattice constant similar to that of at least the first semiconductor layer 15 and having thermal stability.

For example, the substrate may be a conductive substrate or an insulating substrate. For example, the substrate may be formed of at least one selected from the group consisting of sapphire (Al2O3), SiC, Si, GaAs, GaN, ZnO, GaP, InP, and Ge.

The buffer layer 13 may be disposed on the substrate. The buffer layer 13 may serve to alleviate a lattice constant difference between the substrate and the first semiconductor layer 15 . Since the lattice constant difference between the substrate and the first semiconductor layer 15 is alleviated by the lattice constant, the first semiconductor layer 15 , the third semiconductor layer 17 , the fourth semiconductor layer 19 , and the active layer 21 . , the fifth semiconductor layer 23 and the second semiconductor layer 25 may be stably grown without defects. The buffer layer 13 may include a Group 3-5 or Group 2-6 compound semiconductor material.

The first semiconductor layer 15 may be disposed on the buffer layer 13 . When the buffer layer 13 is omitted, the first semiconductor layer 15 may be disposed on the substrate.

The first semiconductor layer 15 may be formed of a compound semiconductor material of Al _x In _y Ga _(1-xy) N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), The present invention is not limited thereto. For example, the first semiconductor layer 15 may include at least one selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, InN, AlInN, GaAs, AlGaAs, GaAsP GaP, InP, GaInP, and AlGaInP. is not limited to

The first semiconductor layer 15 may have a thickness of about 1 μm to about 10 μm.

The first semiconductor layer 15 may include an n-type dopant such as Si, Ge, Sn, Se, or Te. The doping concentration of the first semiconductor layer 15 , for example, the silicon concentration, may be about 5×10 ¹⁸ cm ⁻³ to about 3×10 ¹⁹ cm ⁻³ . By this concentration range, the operating voltage and the epi quality may be improved.

The first semiconductor layer 15 may provide electrons to the active layer 21 .

The first semiconductor layer 15 may include C (carbon). The carbon (C ⁾ concentration of the first semiconductor layer 15 may be 4×10 ¹⁶ cm ⁻³ or less. The operating voltage may be improved by this concentration range.

The third semiconductor layer 17 may be disposed on the first semiconductor layer 15 , and the fourth semiconductor layer 19 may be disposed on the third semiconductor layer 17 .

Each of the third semiconductor layer 17 and the fourth semiconductor layer 19 is composed of Al _x In _y Ga _(1-xy) N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) It may be formed of a compound semiconductor material, but is not limited thereto.

Each of the third semiconductor layer 17 and the fourth semiconductor layer 19 may have a superlattice structure including a plurality of layers. For example, each of the third semiconductor layer 17 and the fourth semiconductor layer 19 may include an InGaN/GaN structure or an InGaN/AlGaN structure that is repeatedly stacked, but is not limited thereto.

The indium content of the third semiconductor layer 17 may be about 1% to about 3%. With this content range, the recess 18 such as a V-pit can be more easily formed and a film quality of a uniform thickness can be obtained.

When the fourth semiconductor layer 19 is used as a stress relief layer, the indium content may be about 3% to about 6%. With this content range, the current can be spread quickly,

When the fourth semiconductor layer 19 is used as the current diffusion layer, the indium content may be about 6% to about 12%. Stress is relieved by this content range, and defects such as cracks in the semiconductor device can be prevented.

Only one of the stress relieving layer and the current diffusion layer may be included in the fourth semiconductor layer 19 , or both the stress relief layer and the current diffusion layer may be included.

The thickness of the third semiconductor layer 17 may be about 130 nm to about 170 nm.

The third semiconductor layer 17 may include an n-type dopant such as Si, Ge, Sn, Se, or Te. A doping concentration of the third semiconductor layer 17 , for example, a silicon concentration, may be about 8×10 ¹⁷ cm ⁻³ to about 2×10 ¹⁸ cm ⁻³ . By this concentration range, the operating voltage and the epi quality may be improved.

The fourth semiconductor layer 19 may include an n-type dopant such as Si, Ge, Sn, Se, or Te. A doping concentration of the fourth semiconductor layer 19 , for example, a silicon concentration, may be about 1×10 ¹⁷ cm ⁻³ to about 1×10 ¹⁸ cm ⁻³ . By this concentration range, the operating voltage and the epi quality may be improved.

The third semiconductor layer 17 may include C. The carbon concentration of ^the third semiconductor layer 17 may be about 6×10 ¹⁶ cm ⁻³ or less. The operating voltage may be improved by this concentration range.

The fourth semiconductor layer 19 may include C. ^The carbon concentration of the fourth semiconductor layer 19 may be about 6×10 ¹⁶ cm ⁻³ or less. The operating voltage may be improved by this concentration range.

In the third semiconductor layer 17 , the ratio of the carbon concentration to the silicon concentration may be about 1:80 to about 1:200.

When the ratio of the carbon concentration to the silicon concentration is 1:80 or more, the resistance of C is canceled by Si, so that the operating voltage can be improved. When the ratio of the carbon concentration to the silicon concentration is 1:200 or less, the movement of electrons generated in the first semiconductor layer 15 is not hindered by Si, so that the luminous intensity may be increased.

Although not shown, it facilitates injection of electrons generated in the first semiconductor layer 15 between the third semiconductor layer 17 and the active layer 21 or between the fourth semiconductor layer 19 and the active layer 21 . An electron injection layer may be further disposed.

The active layer 21 may be disposed on the first semiconductor layer 15 , the third semiconductor layer 17 , or the fourth semiconductor layer 19 .

The active layer 21 may perform electroluminescence (EL) for converting an electric signal supplied between the first semiconductor layer 15 and the second semiconductor layer 25 into light. That is, the active layer 21 may generate light of a specific wavelength region in response to an electrical signal. Light of such a specific wavelength region is not generated by itself, but may be generated when an electric signal is applied between the first semiconductor layer 15 and the second semiconductor layer 25 .

The active layer 21 may include any one of a multiple quantum well structure (MQW), a quantum dot structure, or a quantum wire structure. In the active layer 21 , a well layer and a barrier layer may be repeatedly formed by making a pair of a well layer and a barrier layer.

Since the repetition period of the well layer and the barrier layer can be changed according to the characteristics of the semiconductor device, it is not limited thereto. For example, the active layer 21 may include, for example, 1 to 20 pairs of a well layer and a barrier layer, but is not limited thereto.

The active layer 21 may include, for example, a well layer and a barrier layer such as InGaN/InGaN, InGaN/GaN, or InGaN/AlGaN.

The indium content of the active layer 21 may be about 12% to about 16%. Light of the main emission peak wavelength, for example, light of a blue wavelength, may be generated by this content range.

The well layer may have a thickness of approximately 1 nm to approximately 10 nm, and the barrier layer may have a thickness of approximately 1 nm to approximately 20 nm.

The active layer 21 may not include a dopant.

The active layer 21 may include a p-type dopant such as Mg, Zn, Ca, Sr, or Ba. The doping concentration of the active layer 21, for example, a magnesium (Mg) concentration, may be about 1×10 ¹⁷ cm ⁻³ to about 1×10 ¹⁹ cm ⁻³ . The stress of the active layer 21 is relieved by the doping concentration in this range, so that the efficiency of light generated in the active layer 21 may be improved, the operating voltage may be improved, and the light output may be improved. Here, the operating voltage may be a forward voltage for allowing light to be emitted from the active layer 21 . That is, a positive voltage may be applied to the second semiconductor layer 25 and a negative voltage may be applied to the first semiconductor layer 15 .

The p-type dopant may be included in the well layer and/or the barrier layer of the active layer 21 .

The fifth semiconductor layer 23 may be disposed on the active layer 21 . The fifth semiconductor layer 23 may be formed of a compound semiconductor material of Al _x In _y Ga _(1-xy) N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), The present invention is not limited thereto.

Each of the fifth semiconductor layers 23 may have a superlattice structure including a plurality of layers. For example, each of the fifth semiconductor layers 23 may include an AlGaN/GaN structure that is repeatedly stacked, but is not limited thereto.

For example, the aluminum content of the fifth semiconductor layer 23 may be about 15% to about 24%. By this content range, the electron blocking performance may be improved and the injection efficiency for injecting the holes of the second semiconductor layer 25 into the active layer 21 may be improved.

The fifth semiconductor layer 23 may include a p-type dopant such as Mg, Zn, Ca, Sr, or Ba. The doping concentration of the fifth semiconductor layer 23, for example, the magnesium concentration, may be about 5×10 ¹⁸ cm ⁻³ to about 1×10 ²⁰ cm ⁻³ . By the doping concentration in this range, the operating voltage may be improved and the light output may be improved.

Although not shown, a hole injection layer for facilitating injection of holes generated in the second semiconductor layer 25 may be further disposed between the active layer 21 and the fifth semiconductor layer 23 . For example, the hole injection layer may include GaN, but is not limited thereto.

The second semiconductor layer 25 may be disposed on the fifth semiconductor layer 23 . When the fifth semiconductor layer 23 is omitted, the second semiconductor layer 25 may be disposed on the active layer 21 . The second semiconductor layer 25 may provide holes to the active layer 21 .

The second semiconductor layer 25 may be formed of a compound semiconductor material of Al _x In _y Ga _(1-xy) N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), The present invention is not limited thereto. For example, the second semiconductor layer 25 may include at least one selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, InN, AlInN, GaAs, AlGaAs, GaAsP GaP, InP, GaInP, and AlGaInP. is not limited to

The second semiconductor layer 25 may include a p-type dopant such as Mg, Zn, Ca, Sr, or Ba. The doping concentration of the second semiconductor layer 25, for example, the magnesium concentration, may be about 5×10 ¹⁸ cm ⁻³ to about 5×10 ²⁰ cm ⁻³ . By the doping concentration in this range, the operating voltage may be improved and the light output may be improved.

The second semiconductor layer 25 may have a roughness structure. The recess may include a plurality of concavo-convex patterns 22 . The concave-convex pattern 22 may have, for example, a negative hemispherical shape, but is not limited thereto. The negative hemispherical shape may be a shape dented downward from the surface of the second semiconductor layer 25 .

The uneven pattern 22 may have a curvature. The uneven pattern 22 may have an inflection point. At the inflection point, the concave-convex pattern 22 may have a lowest point. Accordingly, the inflection point may be the lowest point. The lowest point may be the lowest position of the concave-convex pattern 22 .

For example, the concave-convex pattern 22 may have a round surface in a downward direction from the surface of the second semiconductor layer 25 and may have a lowest point at an inflection point.

The concave-convex pattern 22 may be disposed to correspond to the recess 18 formed by the third semiconductor layer 17 . In other words, the concave-convex pattern 22 may not be disposed to correspond to the active layer 21 , but may be disposed to correspond to the recess 18 of the third semiconductor layer 17 .

Since the concave-convex pattern 22 is not disposed on the active layer 21 , light emitted from the active layer 21 may be emitted upward as it is. In addition, light emitted from the active layer 21 and incident into the recess 18 of the third semiconductor layer 17 is easily extracted to the outside by the concavo-convex pattern 22 disposed to correspond to the recess 18 . can be

The concave-convex pattern 22 may be formed in each of the recesses 18 of the third semiconductor layer 17 , but is not limited thereto. This is because the concave-convex pattern 22 is formed by the recess 18 of the third semiconductor layer 17 .

For example, when the second semiconductor layer 25 is grown using the MOCVD equipment, the temperature and thickness of the second semiconductor layer 25 are adjusted to correspond to the recess 18 of the third semiconductor layer 17 . A hemispherical concavo-convex pattern 22 may be formed.

In the related art, a concave-convex pattern may be formed on the second semiconductor layer to improve light extraction efficiency. The conventional concave-convex pattern may be formed by a dry etching process or a wet etching process. When the concave-convex pattern is formed by such an etching process, it is difficult to form the concave-convex pattern with a uniform density.

On the other hand, the concave-convex pattern 22 according to the embodiment may be naturally formed to correspond to the recess 18 formed by the third semiconductor layer 17 when the second semiconductor layer 25 is grown using MOCVD equipment. there is. That is, since the concave-convex pattern 22 is naturally formed on the second semiconductor layer 25 by the in-situ process, the concave-convex pattern 22 having a uniform density is possible.

As described above, since the concave-convex pattern 22 is naturally formed by the recess 18 formed in the third semiconductor layer 17 , a separate process for forming the concave-convex pattern 22 is not required. This can be shortened.

The density of the concave-convex pattern 22 may be about 1×10 ¹⁸ cm ^-3 to about 5×10 ¹⁸ cm ^-3 . The number of concave-convex patterns 22 may be determined by the number of recesses 18 of the third semiconductor layer 17 .

The number of the concave-convex patterns 22 may be equal to or less than the number of the recesses 18 of the third semiconductor layer 17 .

By having a recess including a plurality of concave-convex patterns 22 on the surface of the second semiconductor layer 25 , light emitted from the active layer 21 and incident to the second semiconductor layer 25 is easily extracted and light Extraction efficiency can be improved.

An inflection point of the concave-convex pattern 22 may be located in the active layer 21 . In other words, the inflection point of the concave-convex pattern 22 may be located on the same line as any point in the active layer 21 .

The inflection point of the concave-convex pattern 22 may be located lower than the last well layer of the active layer 21 . The last well layer of the active layer 21 may be a well layer closest to the fifth semiconductor layer 23 among a plurality of well layers included in the active layer 21 . Accordingly, the inflection point of the concave-convex pattern 22 may be located on the same line as the barrier layer or another well layer disposed at a lower position than the last well layer of the active layer 21 .

Since the inflection point of the concave-convex pattern 22 is located in the active layer 21 , the light of the active layer 21 is easily extracted to the outside by the concavo-convex pattern 22 formed on the surface of the second semiconductor layer 25 , so that the light extraction efficiency This can be further improved.

The width W2 of the concave-convex pattern 22 is the recess 18 of the third semiconductor layer 17 or the fourth semiconductor layer 19 , the active layer 21 , and the fifth semiconductor layer 23 formed thereon, respectively. is affected by the width of each of the recesses in That is, the width W2 of the concavo-convex pattern 22 may be determined by the width of these recesses.

In addition, the width W2 of the concave-convex pattern 22 may be determined by the process temperature or the thickness of the second semiconductor layer 25 when the second semiconductor layer 25 is grown.

For example, the width W2 of the concave-convex pattern 22 may be narrower than the width of the recess 18 of the third semiconductor layer 17 , but is not limited thereto.

For example, the width W2 of the concave-convex pattern 22 may be about 300 nm to about 400 nm. For example, the width W2 of the concave-convex pattern 22 may be 340 nm.

The second semiconductor layer 25 may be divided into a portion in which the uneven pattern 22 is formed and a portion in which the uneven pattern 22 is not formed. A portion in which the concave-convex pattern 22 is not formed is referred to as a first area, and a portion in which the concave-convex pattern 22 is formed is referred to as a second area.

Even if the concave-convex pattern 22 is not formed, the second semiconductor layer 25 may be formed under the concave-convex pattern 22 .

In this case, the first thickness S1 of the first region of the second semiconductor layer 25 may be about 5 nm to about 65 nm. When the first thickness S1 of the first region of the second semiconductor layer 25 is 5 nm or less, the thickness of the second semiconductor layer 25 may be too thin, and thus the film quality may be deteriorated. When the first thickness S1 of the first region of the second semiconductor layer 25 is 65 nm or more, the second semiconductor layer 25 corresponding to the recess 18 of the third semiconductor layer 17 is merged. ) is flattened so that the uneven pattern 22 is not formed.

Accordingly, when the first thickness S1 of the first region of the second semiconductor layer 25 is about 5 nm to about 65 nm, the concavo-convex pattern 22 corresponds to the recess 18 of the third semiconductor layer 17 . This can be easily formed.

The second thickness S2 of the second region of the second semiconductor layer 25 may be about 310 nm to about 510 nm. The second thickness S2 of the second region of the second semiconductor layer 25 may be defined as an interval between the lowest point of the recess of the fifth semiconductor layer 23 and the inflection point of the concave-convex pattern 22 . When the fifth semiconductor layer 23 is omitted, the second thickness S2 of the second region may be defined as the interval between the lowest point of the recess of the active layer 21 and the inflection point of the concave-convex pattern 22 .

Due to the limit of the width of the recess 18 formed by the third semiconductor layer 17 , the thickness ( The concave-convex pattern 22 cannot be formed so that the inflection point is located at S2) of 310 nm or less. Accordingly, a point 310 nm from the lowest point of the recess of the fifth semiconductor layer 23 may be a limit point at which the inflection point of the concave-convex pattern 22 may be positioned as the lowest point.

When the second thickness S2 of the second region of the second semiconductor layer 25 is 510 nm, the inflection point of the concave-convex pattern 22 is located on the same line as the surface of the second semiconductor layer 25 so that the concave-convex pattern ( 22) is not formed.

The ratio of the first thickness S1 of the first region of the second semiconductor layer 25 to the second thickness S2 of the second region of the second semiconductor layer 25 is about 1:4 to about 1: It could be 20. Preferably, the ratio of the first thickness S1 of the first region of the second semiconductor layer 25 to the second thickness S2 of the second region of the second semiconductor layer 25 may be 1:8.8. there is.

(Detailed structure of the third semiconductor layer)

2 shows the third semiconductor layer in detail.

Referring to FIG. 2 , the third semiconductor layer 17 may be configured in first to third pairs, but is not limited thereto. That is, three or more pairs of the third semiconductor layer 17 are possible.

Each of the first to third pairs may include a first sub-semiconductor layer 17a and a second sub-semiconductor layer 17b. Accordingly, the upper surface of the first pair of second sub-semiconductor layers 17b is in contact with the lower surface of the second pair of first sub-semiconductor layers 17a, and the upper surface of the second pair of second sub-semiconductor layers 17b is The third pair of the first sub-semiconductor layer 17a may be in contact with the lower surface thereof.

For example, the lower surface of the first pair of first sub-semiconductor layers 17a is in contact with the upper surface of the first semiconductor layer 15 , and the upper surface of the third pair of second sub-semiconductor layers 17b is the fourth semiconductor layer 19 . ), but is not limited thereto.

For example, the first sub-semiconductor layer 17a may be GaN. For example, the second sub-semiconductor layer 17b may be InGaN. That is, the first sub-semiconductor layer 17a may contain In, and the second sub-semiconductor layer 17b may not contain In. Accordingly, the third semiconductor layer 17 may include In periodically, for example, in pairs.

The third semiconductor layer 17 may be grown on the first semiconductor layer 15 at a temperature of about 830° C. to about 870° C. thereon.

For example, by periodically injecting In while trimethylgallium (TMG) gas and nitrogen (N2) gas are being injected into the chamber of the MOCVD equipment, the first sub-semiconductor layer 17a of each of the first to third pairs and A second sub-semiconductor layer 17b may be grown. When In is not implanted, the first sub-semiconductor layer 17a including GaN is grown by the TMG gas and nitrogen gas. A sub-semiconductor layer 17b may be grown.

For example, the thickness T1 of the first sub-semiconductor layer 17a may be about 15 nm to about 40 nm. For example, the thickness T2 of the second sub-semiconductor layer 17b may be about 2 nm to about 5 nm.

A ratio of the thickness of the second sub-semiconductor layer 17b to the thickness of the first sub-semiconductor layer 17a may be about 1:3 to about 1:8. In this range, the growth rate in the vertical direction and the horizontal direction of the third semiconductor layer 17 is controlled, so that the recess 18 such as a V-pit can be easily formed.

For example, the angle of the inclination of the inclined surface of the recess 18 with respect to the normal may be θ1. The angle θ1 of the inclination of the inclined surface of the recess 18 may be 5° or more. The luminous intensity can be increased at tilt angles of 5° or more.

When the ratio of the thickness of the second sub-semiconductor layer 17b to the thickness of the first sub-semiconductor layer 17a is less than 1:3 or exceeds 1:8, the arrangement density of the recesses 18 or the recesses 18 ), the inclination of the inclined surface is changed, and thus the optical output, operating voltage, and ESD (Electro Static Discharge) characteristics of the semiconductor device may be deteriorated. The batch density may be the distribution probability of the recesses 18 .

In the drawing, the recess 18 is illustrated as starting from the second sub-semiconductor layer 17b of the first pair, but the starting position of the recess 18 may be variously changed.

The recess 18 of the third semiconductor layer 17 may improve electrical and optical characteristics of the semiconductor device. However, when the recesses 18 are excessively disposed, that is, when the recess 18 disposed density is excessive, electrical and optical characteristics and reliability of the semiconductor device may be deteriorated. Accordingly, by controlling the arrangement density and size of the recesses 18, optical and electrical characteristics of the semiconductor device can be improved and reliability can be secured.

As shown in FIG. 2 , the width W1 or size of the recess 18 may increase from the lower part to the upper part of the third semiconductor layer 17 . In this case, the maximum width W1 of the recess 18 in the uppermost region of the second sub-semiconductor layer 17b of the third pair can be obtained.

The first semiconductor layer 15 may be grown, for example, at a temperature of approximately 1000°C to 1,100°C. In this case, the third semiconductor layer 17 may be grown at a temperature lower than that of the first semiconductor layer 15 , that is, at a temperature of about 830°C to about 870°C. Also, the first and second sub-semiconductor layers 17a and 17b included in each pair of the third semiconductor layer 17 may be grown to have different thicknesses. In addition, In may be selectively contained in the first and second sub-semiconductor layers 17a and 17b of each pair of the third semiconductor layer 17 . Accordingly, as the first sub-semiconductor layer 17a and the second sub-semiconductor layer 17b of the third semiconductor layer 17 are periodically grown through temperature control, thickness control, and indium content control, The recess 18 can be formed easily and precisely.

(Detailed structure of the fifth semiconductor layer)

3 shows the fifth semiconductor layer in detail.

Referring to FIG. 3 , the fifth semiconductor layer 23 may be configured in first to third pairs, but is not limited thereto.

Each of the first to third pairs may include a first sub-semiconductor layer 23a and a second sub-semiconductor layer 23b, 23c, and 23d. Accordingly, the upper surface of the first pair of second sub-semiconductor layers 23b is in contact with the lower surface of the second pair of first sub-semiconductor layers 23a, and the upper surface of the second pair of second sub-semiconductor layers 23c is The third pair of the first sub-semiconductor layer 23a may be in contact with the lower surface thereof.

For example, the lower surface of the first pair of first sub-semiconductor layers 23a is in contact with the upper surface of the active layer 21 , and the upper surface of the third pair of second sub-semiconductor layers 23d is the lower surface of the second semiconductor layer 25 . may be in contact with, but is not limited thereto.

For example, the first sub-semiconductor layer 23a may be GaN, and the second sub-semiconductor layers 23b, 23c, and 23d may be AlGaN.

The aluminum content of the second sub-semiconductor layers 23b, 23c, and 23d of each of the first to third pairs may be different.

For example, the first pair of second sub-semiconductor layers 23b includes AlxGa1-xN/GaN, the second pair of second sub-semiconductor layers 23c include AlyGa1-yN, and the third pair of second The sub-semiconductor layer 23d may include AlzGa1-zN. In this case, x, y, and z satisfy the relationship between Equations 1 and 2 below.

[Equation 1]

y=x-0.03,

[Equation 2]

z=y-0.03

x may be 0.21 to 0.24.

For example, when x is 0.24, the aluminum content of the first pair of second sub-semiconductor layers 23b may be 24%, and the aluminum content of the second pair of second sub-semiconductor layers 23c may be 21%. and the aluminum content of the third pair of second sub-semiconductor layers 23d may be 18%.

For example, when x is 0.21, the aluminum content of the first pair of second sub-semiconductor layers 23b is 21%, the aluminum content of the second pair of second sub-semiconductor layers 23c is 18%, 3 pairs The aluminum content of the second sub-semiconductor layer 23d may be 15%.

Accordingly, the aluminum content of the second sub-semiconductor layers 23b , 23c , and 23d of each of the first to third pairs of the fifth semiconductor layer 23 may be adjusted within a range of about 15% to about 24%. By this content range, the electron blocking performance may be improved and the injection efficiency for injecting the holes of the second semiconductor layer 25 into the active layer 21 may be improved.

The luminous intensity (Po) of the semiconductor device varies according to the aluminum content, which is shown in FIG. 4 .

4 shows the luminous intensity according to the aluminum content of the fifth semiconductor layer.

Referring to FIG. 4 , it can be seen that the luminous intensity Po is highest when the aluminum content is 24%, and the luminous intensity Po decreases when the aluminum content is decreased or increased based on 24%.

The aluminum content of the first pair of second sub-semiconductor layers 23b is about 21% to about 24%, and the aluminum content of the second pair of second subsemiconductor layers 23c is about 18% to about 21%, The aluminum content of the three pairs of the second sub-semiconductor layers 23d may be about 15% to about 18%. As described above, the aluminum content of the second sub-semiconductor layers 23c and 23d of each of the second pair and the third pair may be determined by Equations 1 and 2.

When the aluminum content is less than 21%, electrons overflow from the active layer 21 to the second semiconductor layer 25 and light loss may occur due to leakage current. When the aluminum content exceeds 24%, holes injected from the second semiconductor layer 25 are not easily injected into the active layer 21 , and thus the operating voltage may increase.

Meanwhile, the operating characteristics of the conventional semiconductor device having no concavo-convex pattern on the second semiconductor layer and the semiconductor device according to the embodiment having the second semiconductor layer 25 including the concave-convex pattern 22 are shown in Table 1 below.

An integrating sphere may be used as the photometer. For example, the integrating sphere is a spherical device having a hollow inside, and may be a device that receives light into the hollow and measures its properties.

characteristic wavelength integrating sphere (65mA) integrating sphere (150mA) V _f3 (V) P ₀ (mW) Wd (nm) P ₀ (mW) P ₀ (mW) conventionally 2.853 135.79 453.0 102.9 223.9 Example 2.880 143.20 450.8 104.3 226.8

As shown in Table 1, conventionally, when applied at 2.853V (Vf3), the luminous intensity (Po) of 135.79mW is output, whereas in the embodiment, when applied as 2.885V (Vf3), the luminous intensity (Po) of 143.20mW is can be output. That is, a higher luminous intensity can be obtained in the embodiment compared to the conventional one.

As a result of measuring the light intensity by the integrating sphere (65 mA), the conventional light intensity of 102.9 mW is output, whereas in the embodiment, the light intensity of 104.3 mW can be output. In addition, as a result of the luminous intensity measurement by the integrating sphere (150mA), the luminous intensity of 223.9 mW is outputted in the prior art, whereas the luminous intensity of 226.8 mW is output in the embodiment. Therefore, even in the result of photometric measurement by the integrating sphere, higher luminous intensity can be obtained in the embodiment than in the related art.

(Horizontal type semiconductor device and flip type semiconductor device)

5 shows a horizontal type semiconductor device.

The horizontal type semiconductor device may be manufactured by adding a subsequent process to the semiconductor device according to the first embodiment shown in FIG. 1 .

Referring to FIG. 5 , when the semiconductor device according to the first embodiment shown in FIG. 1 is provided, mesa etching may be performed to remove a portion of the light emitting structure. That is, the second semiconductor layer 25 , the fifth semiconductor layer 23 , the active layer 21 , the fourth semiconductor layer 19 , the third semiconductor layer 17 and the first semiconductor layer 15 are formed by mesa etching. Each edge region may be removed. The upper part of the first semiconductor layer 15 may be removed and the lower part may not be removed.

Subsequently, the first electrode 27 may be disposed on the first semiconductor layer 15 etched by mesa-etching, and the second electrode 29 may be disposed on the second semiconductor layer 25 . The first electrode 27 and the second electrode 29 may be formed of a metal material having excellent conductivity. Each of the first electrode 27 and the second electrode 29 may include at least one or more layers.

The upper surface of the first electrode 27 is disposed to be positioned lower than the active layer 21 of the light emitting structure, so that when light generated from the active layer 21 of the light emitting structure is emitted to the side of the active layer 21 , the first electrode 27 ) may not be reflected by

This and the moon, the upper surface of the first electrode 27 is arranged to be positioned higher than the active layer 21 of the light emitting structure, so that when the light generated in the active layer 21 of the light emitting structure is emitted from the side of the active layer 21, It may be reflected by the side surface of the first electrode 27 .

As described above, since the recess 18 is formed in the third semiconductor layer 17 , the fourth semiconductor layer 19 and the active layer 21 correspond to the recess 18 of the third semiconductor layer 17 . and a recess may be formed in each of the fifth semiconductor layers 23 .

In addition, the concave-convex pattern 22 may be formed in the second semiconductor layer 25 to correspond to the recess 18 of the third semiconductor layer 17 .

An electrode layer 26 may be formed on the second semiconductor layer 25 . The electrode layer 26 may be formed using sputtering equipment, but is not limited thereto.

For example, in a horizontal semiconductor device, a transparent electrode layer may be disposed as the electrode layer 26 on the second semiconductor layer 25 .

The transparent electrode layer may also have a concave-convex pattern corresponding to the concave-convex pattern 22 of the second semiconductor layer 25 . The density of the concavo-convex pattern of the transparent electrode layer may be the same as the density of the concavo-convex pattern 22 of the second semiconductor layer 25 , but is not limited thereto.

When the transparent electrode layer is formed on the second semiconductor layer 25 , the second electrode 29 may be disposed on the transparent electrode layer.

The transparent electrode layer may include a transparent conductive material. The transparent electrode layer may be formed of a material having excellent ohmic characteristics with the second semiconductor layer 25 and excellent current spreading characteristics. For example, the transparent electrode layer is ITO, IZO (In-ZnO), GZO (Ga-ZnO), AZO (Al-ZnO), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), IrOx, RuOx, RuOx / It may include at least one selected from the group consisting of ITO, Ni/IrOx/Au, and Ni/IrOx/Au/ITO, but is not limited thereto.

After the transparent electrode layer is disposed on the second semiconductor layer 25 , mesa etching may be performed, or after the mesa etching is performed, the transparent electrode layer may be disposed on the second semiconductor layer 25 .

The second electrode 29 is formed on the transparent electrode layer after the transparent electrode layer is disposed on the second semiconductor layer 25 or the transparent electrode layer after the transparent electrode layer is disposed on the second semiconductor layer 25 and mesa etching is performed. may be placed on the

On the other hand, when the horizontal type semiconductor device shown in FIG. 5 is turned over 180 degrees and is adopted for a semiconductor device package, it may be used as a flip type semiconductor device.

In this case, a reflective electrode layer as the electrode layer 26 may be disposed on the second semiconductor layer 25 . The reflective electrode layer may be formed of a material composed of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf, and a selective combination thereof.

The reflective electrode layer may also have an uneven pattern corresponding to the uneven pattern 22 of the second semiconductor layer 25 . The density of the concavo-convex pattern of the reflective electrode layer may be the same as the density of the concavo-convex pattern 22 of the second semiconductor layer 25 , but is not limited thereto.

Light emitted from the active layer 21 and traveling in a downward direction may be diffusely reflected by the concave-convex pattern of the reflective electrode layer and reflected upward, so that more light may be emitted upward, thereby improving optical efficiency. .

6 illustrates a semiconductor device package according to an embodiment.

As shown in FIG. 6 , the semiconductor device package according to the embodiment includes a body 311 having a cavity 315 , a first lead frame 321 and a second lead frame 323 disposed in the body 311 . ), the semiconductor device 100 , wires 331 , and a molding member 341 .

The body 311 may include a conductive material or an insulating material. The body 311 may be formed of at least one of a resin material, a silicon material, a metal material, photo sensitive glass (PSG), sapphire (Al2O3), and a printed circuit board (PCB). The resin material may be polyphthalamide (PPA: Polyphthalamide) or epoxy.

The body 311 has a cavity 315 having an open top and a side and a bottom. The cavity 315 may include a cup structure or a recess structure concave from the upper surface of the body 311 , but is not limited thereto.

The first leadframe 321 is disposed in a first area of the bottom area of the cavity 315 , and the second leadframe 323 is disposed in a second area of the bottom area of the cavity 315 . The first leadframe 321 and the second leadframe 323 may be spaced apart from each other in the cavity 315 .

The first and second leadframes 321 and 323 are made of a metal material, for example, titanium (Ti), copper (Cu), nickel (Ni), gold (Au), chromium (Cr), or tantalum (Ta). , platinum (Pt), tin (Sn), silver (Ag), may include at least one of phosphorus (P). The first and second leadframes 321 and 323 may be formed of a single metal layer or a multi-layered metal layer.

The semiconductor device 100 may be disposed on at least one of the first and second lead frames 321 and 223 . The semiconductor device 100 is, for example, disposed on the first leadframe 321 and connected to the first and second leadframes 321 and 223 with a wire 331 .

The semiconductor device 100 may selectively emit light in a range from a visible ray band to an ultraviolet ray band, and may be selected from, for example, a red LED chip, a blue LED chip, a green LED chip, and a yellow green LED chip. The semiconductor device 100 may include a group 3-5 or group 2-6 compound semiconductor. The semiconductor device 100 may employ the technical features of FIGS. 1 to 8 .

A molding member 341 may be disposed in the cavity 315 of the body 311 . The molding member 341 may include a light-transmitting resin layer such as silicone or epoxy. The molding member 341 may be formed in a single layer or in multiple layers. The molding member 341 may include a phosphor for changing the wavelength of light emitted from the semiconductor device 100 , and the phosphor excites some of the light emitted from the semiconductor device 100 and emits light of a different wavelength. will do The phosphor may be selectively formed from among YAG, TAG, Silicate, Nitride, and Oxy-nitride-based materials. The phosphor may include at least one of a red phosphor, a yellow phosphor, and a green phosphor, but is not limited thereto. The surface of the molding member 341 may be formed in a flat shape, a concave shape, a convex shape, or the like, but is not limited thereto.

A lens may be further formed on the upper portion of the body 311, c. It may include a structure of a concave and/or convex lens, and may control light distribution of light emitted by the semiconductor device 100 .

A protection device may be disposed in the semiconductor device package. The protection device may be implemented as a thyristor, a Zener diode, or a transient voltage suppression (TVS).

Meanwhile, the semiconductor device package according to the embodiment may be applied to a light source device.

In addition, the light source device may include a display device, a lighting device, a head lamp, etc. according to an industrial field.

As an example of the light source device, the display device includes a bottom cover, a reflecting plate disposed on the bottom cover, a light emitting module that emits light and includes a light emitting device, and is disposed in front of the reflecting plate and guides light emitted from the light emitting module to the front A light guide plate, an optical sheet including prism sheets disposed in front of the light guide plate, a display panel disposed in front of the optical sheet, an image signal output circuit connected to the display panel and supplying an image signal to the display panel; It may include a color filter disposed in front. Here, the bottom cover, the reflector, the light emitting module, the light guide plate, and the optical sheet may form a backlight unit. Also, the display device may have a structure in which light emitting devices emitting red, green, and blue light are respectively disposed without including a color filter.

As another example of the light source device, the head lamp is a light emitting module including a semiconductor device package disposed on a substrate, a reflector that reflects light emitted from the light emitting module in a predetermined direction, for example, forward, and is reflected by the reflector It may include a lens that refracts light forward, and a shade that blocks or reflects a portion of light reflected by the reflector and directed to the lens to form a light distribution pattern desired by a designer.

A lighting device, which is another example of the light source device, may include a cover, a light source module, a heat sink, a power supply unit, an inner case, and a socket. In addition, the light source device according to the embodiment may further include any one or more of a member and a holder. The light source module may include a semiconductor device package according to an embodiment.

Features, structures, effects, etc. described in the above embodiments are included in at least one embodiment, and are not necessarily limited to only one embodiment. Furthermore, features, structures, effects, etc. illustrated in each embodiment can be combined or modified for other embodiments by those of ordinary skill in the art to which the embodiments belong. Accordingly, the contents related to such combinations and variations should be interpreted as being included in the scope of the embodiments.

In the above, the embodiment has been mainly described, but this is only an example and does not limit the embodiment, and those of ordinary skill in the art to which the embodiment belongs are provided with several examples not illustrated above within the range that does not deviate from the essential characteristics of the embodiment. It can be seen that the transformation and application of branches are possible. For example, each component specifically shown in the embodiment can be implemented by modification. And the differences related to these modifications and applications should be interpreted as being included in the scope of the embodiments set forth in the appended claims.

10: semiconductor device
11: Substrate
13: buffer layer
15, 17, 19, 23, 25: semiconductor layer
17a, 17b, 23a, 23b, 23c, 23d: sub-semiconductor layer
18: recess
21: active layer
22: uneven pattern
26: electrode layer
27, 29: electrode

Claims (12)

a first conductivity type semiconductor layer;
a second conductivity type semiconductor layer;
an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, the active layer recombination of the first carrier of the first conductivity type semiconductor layer and the second carrier of the second conductivity type semiconductor layer; and
An electron blocking layer disposed between the active layer and the second conductivity type semiconductor layer,
The first conductivity type semiconductor layer includes a 1-1 conductivity type semiconductor layer having a first recess concave in a first direction on an upper surface thereof;
The first direction is a direction from the second conductivity type semiconductor layer to the first conductivity type semiconductor layer,
The second conductivity type semiconductor layer includes a second recess disposed on the uppermost surface of the second conductivity type semiconductor layer,
the first recess and the second recess overlap in the first direction;
A lowest point of the second recess is disposed lower than a top surface of the active layer. According to claim 1,
The second recess includes a concave-convex pattern having a hemispherical shape having a curvature,
The concave-convex pattern has a round surface and an inflection point along the inside from the surface of the second conductivity type semiconductor layer,
The inflection point is a semiconductor device positioned at the lowest point of the concave-convex pattern. 3. The method of claim 2,
The second conductivity type semiconductor layer has a first region in which the concave-convex pattern is not formed and a second region in which the concavo-convex pattern is formed,
A ratio of the first thickness of the first region to the second thickness of the second region is 1:4 to 1:20,
the active layer includes a third recess overlapping the first recess and the second recess in the first direction;
The second thickness of the second region is an interval between the lowest point of the third recess of the active layer and the inflection point of the concave-convex pattern,
The concave-convex pattern is a semiconductor device positioned in the active layer. 4. The method of claim 3,
The active layer includes a plurality of well layers and a plurality of barrier layers,
The concave-convex pattern is positioned lower than a last well layer closest to the second conductivity-type semiconductor layer among the plurality of well layers. delete delete delete delete delete delete delete delete

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