KR102378031B1 - Current Differential Relay and Sampling Synchronization Method - Google Patents

Abstract

In the current differential relay 53A, the voltage calculating unit 74, based on the current data I1 and the voltage data V1 of the first terminal, a specific point on the line connecting the first terminal and the second terminal of the power transmission line The voltage at is calculated as the first specific point voltage, and the voltage at the specific point is calculated as the second specific point voltage based on the current data Is1 and the voltage data Vs1 of the second terminal. Here, the voltage calculating unit 74 is configured for each of the first line connecting the first terminal and the specific point and the second line connecting the second terminal and the specific point, when the entire power transmission line is a single π-type circuit. The first specific point voltage and the second specific point voltage are calculated by simulating as an L-type circuit that is a part of the ?-type circuit or as a single T-type circuit or as a plurality of T-type circuits connected in series. The phase difference calculating unit 75 calculates a phase difference between the first specific point voltage and the second specific point voltage. The synchronization processing unit 73 adjusts the sampling time based on the time corresponding to the phase difference.

Description

Current Differential Relay and Sampling Synchronization Method

The present disclosure relates to a current differential relay for protecting a power transmission line, and a sampling synchronization method for detecting current values and voltage values at both ends of a power transmission line by the current differential relay or the like.

Current differential relays for protecting the power transmission line are provided at both ends of the protection section of the power transmission line. Each current differential relay receives a current value from a current transformer provided at its own end, and transmits the received current value to each other via a transmission path. Then, each current differential relay detects a failure in the power transmission line based on the difference between the current values at both ends of the power transmission line. At that time, in order to accurately determine a failure, it is necessary to synchronize the sampling timing of the current at both ends of the power transmission line.

A sampling synchronization method that has been conventionally used and has become mainstream is disclosed, for example, in Japanese Patent Application Laid-Open No. 62-262615 (Patent Document 1). In this method, when each current differential relay transmits the current data of its own end to the other end, the transmission timing information is incorporated into the transmission data. Then, each current differential relay measures the time from transmitting the transmission timing information to the opposite end until receiving the transmission timing information of the opposite end. Each current differential relay transmits the measured time to each other, and adjusts the sampling timing so that this time becomes equal to each other.

In order to perform sampling synchronization accurately by this method, the condition that the transmission time from the own end to the opposite end and the transfer time from the opposite end to the own end are equal is essential. However, when transmission is performed using a general-purpose communication device, there may be a difference of several 100 microseconds in the transmission times in these two directions. For this reason, an error occurs in the sampling synchronization, and this synchronization error becomes a factor of error in the calculation of the current differential relay.

Therefore, when particularly precision is required, such as a failure point expression device that identifies a failure point in a transmission line serving as a protection section, for example, it is described in Japanese Patent Application Laid-Open No. 4-17509 (Patent Document 2). A sampling synchronization method as described above has been proposed. Specifically, the fault point expression device by this method acquires the detection values of the voltage and current at both ends of a power transmission line. And a fault point expression apparatus calculates the terminal voltage of the other end by subtracting the voltage drop of the power transmission line by the terminal current of the one end from the terminal voltage of one end of a power transmission line. Based on the phase difference between the calculated terminal voltage of the other end and the actually acquired terminal voltage of the other end, a fault point expression apparatus performs sampling synchronization at both ends of a power transmission line.

Patent Document 1: Japanese Patent Application Laid-Open No. 62-262615 Patent Document 2: Japanese Patent Laid-Open No. 4-17509

The inventor of the present application studied the error factor of the sampling synchronization method disclosed in Patent Document 2 and the like described above. As a result, it has been found that, in the sampling synchronization method according to this document, the problem is that the influence of the charging current from the power transmission line to the earth based on the earth capacitance of the transmission line is not considered. In particular, since the charging current cannot be neglected when the transmission line is composed of an underground cable or when the line length is long in the overhead line, the error increases in the sampling synchronization ignoring the charging current. Such a problem has not been generally considered until now.

The present disclosure has taken into account the above problems, and an object thereof is to provide a sampling synchronization processing method for accurately realizing sampling synchronization at both ends of a power transmission line, and a current differential relay incorporating the sampling synchronization processing method.

A current differential relay according to an embodiment is provided at a first terminal of a power transmission line. The current differential relay includes an analog/digital conversion unit, a receiver, a voltage calculating unit, a phase difference calculating unit, and a synchronization processing unit. The analog/digital converter generates current data and voltage data by sampling the current and voltage of the first terminal of the power transmission line. The receiver receives the current data and voltage data of the second terminal from the second current differential relay provided at the second terminal of the power transmission line. The voltage calculating unit calculates a voltage at a specific point between the first terminal and the second terminal of the power transmission line as a first specific point voltage based on the current data and voltage data of the first terminal, and the current data of the second terminal and Based on the voltage data, the voltage at this specific point is calculated as the second specific point voltage. The phase difference calculating unit calculates a phase difference between the first specific point voltage and the second specific point voltage. The synchronization processing unit adjusts the sampling time of the current and voltage of the first terminal based on the time corresponding to the phase difference. Here, the voltage calculating unit is a π-type circuit when the entire power transmission line is a single π-type circuit for each of the first line connecting the first terminal and the specific point and the second line connecting the second terminal and the specific point. The first specific point voltage and the second specific point voltage are calculated by simulating as an L-type circuit that is a part of the circuit, as a single T-type circuit, or as a plurality of T-type circuits connected in series.

According to the above-described embodiment, each of the first line and the second line is an L-type circuit that is a part of the ?-type circuit when the entire power transmission line is a single ?-type circuit, or as a single T-type circuit, or By simulating as a plurality of T-circuits connected in series, the influence of the ground capacitance of the power transmission line is taken into account in the calculation, so that sampling synchronization at both ends of the power transmission line can be performed accurately.

1 is a schematic diagram of a power transmission line having a rear power supply at both ends.
Fig. 2 is a block diagram showing an example of a hardware configuration of each current differential relay of Fig. 1;
3 is an equivalent circuit diagram of a normal circuit when there is no failure in the power transmission system of FIG.
FIG. 4 is a view for explaining a charging current in the normal circuit of FIG. 3 .
Fig. 5 is a vector diagram showing an example of the phase difference between the A-stage voltage V1 and the B-stage voltage Vs1;
6 is a diagram for explaining a sampling synchronization method;
Fig. 7 is an equivalent circuit diagram of a normal circuit of a power transmission system simulated by a π-type circuit.
FIG. 8 is a diagram for explaining a charging current in the normal circuit of FIG. 7;
Fig. 9 is a block diagram showing a functional configuration of the current differential relay according to the first embodiment;
Fig. 10 is a flowchart showing a procedure of sampling synchronization processing according to the first embodiment;
11 is a vector diagram showing an example of a phase difference between midpoint voltages Vf and Vfs.
Fig. 12 is a flowchart showing another sampling synchronization procedure;
Fig. 13 is a diagram for explaining the procedure of step S711 in Fig. 12 in more detail;
Fig. 14 is a flowchart showing another sampling synchronization procedure;
Fig. 15 is an equivalent circuit diagram of a normal circuit of a power transmission system to which sampling synchronization processing according to a modification of the first embodiment is applied;
Fig. 16 is an equivalent circuit diagram of a normal circuit of a power transmission system to which sampling synchronization processing according to the second embodiment is applied;
Fig. 17 is a flowchart showing the procedure of sampling synchronization processing according to the second embodiment;
Fig. 18 is an equivalent circuit diagram of a normal circuit of a power transmission system when a transmission line is simulated in a two-stage T-type circuit;
Fig. 19 is a flowchart showing the sampling synchronization procedure of the power transmission system simulated by the equivalent circuit of Fig. 18;
Fig. 20 is an equivalent circuit diagram of a normal circuit of a power transmission system to which sampling synchronization processing according to the third embodiment is applied;
Fig. 21 is a flowchart showing the sampling synchronization procedure of the power transmission system simulated by the equivalent circuit of Fig. 20;
Fig. 22 is an equivalent circuit diagram of a normal circuit of a power transmission system in a case where the intermediate point from each terminal is simulated by a two-stage T-type circuit.
Fig. 23 is a flowchart showing the sampling synchronization procedure of the power transmission system simulated by the equivalent circuit of Fig. 22;
Fig. 24 is a schematic diagram of a three-terminal power transmission line having a rear power supply at each terminal;
Fig. 25 is an equivalent circuit diagram of the normal circuit of the power transmission system of Fig. 24;
Fig. 26 is a flowchart showing a procedure for synchronizing the sample timing of terminal A with the sample timing of terminal B;
Fig. 27 is a flowchart showing a procedure for synchronizing the sample timing of the C terminal with the sample timing of the B terminal;
Fig. 28 is a schematic diagram of a four-terminal power transmission line having a rear power supply at each terminal;
Fig. 29 is a flowchart showing an example of a procedure of sampling synchronization processing in the power transmission system of Fig. 28;

Hereinafter, each embodiment is described in detail with reference to drawings. In addition, the same reference code|symbol is attached|subjected to the same or corresponding part, and the description is not repeated.

Embodiment 1.

<Common Configuration and Prerequisites>

First, the structure common to each embodiment and the matter used as a premise are demonstrated, and then the characteristic of Embodiment 1 is demonstrated.

[Schematic diagram of a power transmission line with a background power at both ends]

1 is a system diagram of a power transmission line having a rear power supply at both ends. Referring to FIG. 1 , a rear power source 52A is provided at end A (also referred to as a first end) of a power transmission line 50 , and a B end (also referred to as a second end) of the power transmission line 50 . A rear power supply 52B is provided. In addition, although the transmission line 50 is a three-phase transmission line, in FIG. 1, it is shown as one line for ease of illustration.

A current transformer (CT: Current Transformer) (CT1) is provided at the A terminal of the power transmission line 50, and a voltage transformer (VT: Voltage Transformer) (VT1) is provided in the A bus (51A) of the A terminal. Similarly, the current transformer CT2 is provided at the B stage of the power transmission line 50 , and the voltage transformer VT2 is provided in the B stage bus 51B. In addition, on the upper portion of the power transmission line 50 between the A and B terminals, a circuit breaker (CB: Circuit Breaker) 68A is provided close to the A terminal, and a breaker 68B is provided close to the B terminal.

In this specification, the current transformers CT1 and CT2 are referred to as current transformers CT when generically or unspecified. When referring to voltage transformers VT1 and VT2 as a generic name or when showing an unspecified thing, it describes as voltage transformer VT. In addition, electric current and voltage are collectively referred to as electricity quantity in some cases.

Current differential relays 53A and 53B are further provided at terminals A and B of the power transmission line 50 , respectively. Incidentally, in this specification, when a current differential relay provided in any one terminal is indicated, it is described as a current differential relay 53 . In addition, the current differential relays 53A and 53B provided in each terminal of the power transmission line 50 are collectively referred to as a current differential relay system in some cases.

Each of the current differential relays 53A and 53B acquires a signal representing a three-phase alternating current flowing through the self-end of the power transmission line 50 from the current transformer CT of its own end, and A signal representing the three-phase AC voltage of the self-end is acquired from the voltage transformer (VT) of the self-end. Each of the current differential relays 53A and 53B generates current data and voltage data by sampling the acquired current and voltage of its own end and performing A/D conversion. Each current differential relay transmits current data and voltage data of its own end to the current differential relay of the opposite end via the communication path 54 . In this case, the communication path 54 may be wired or wireless. The current differential relays 53A and 53B calculate the difference current between both ends of the power transmission line 50 from the acquired current data of the own end and the opposite end, and based on the calculated difference current, the protection inside the current transformers CT1 and CT2 It is determined whether or not a failure has occurred in the power transmission line 50 within the section.

In order to accurately calculate the differential current at both ends of the power transmission line 50 in the above, the current differential relays 53A and 53B at both ends of the power transmission line 50 synchronize the timing of sampling the current values from the current transformers CT1 and CT2, respectively. There is a need. For this reason, the current differential relays 53A and 53B perform synchronous processing. The most basic synchronization processing is as follows.

Specifically, each current differential relay 53 transmits the sampling data of current and voltage of its own end to the opposite end at regular intervals (eg, 30° cycle of the electric angle of the alternating current quantity). The timing signal is embroidered into the transmitted data. Each current differential relay 53 measures the time interval between the transmission time of the timing signal to the opposite end and the reception time of the timing signal from the opposite end. Then, each current differential relay 53 transmits the measured time interval to each other. Each current differential relay 53 has a sampling timing and timing signal of an electric quantity so that the time interval T1 between the transmission time and the reception time of the timing signal measured at the own end and the time interval T2 received from the opposite end become equal. Adjust the timing to transmit

Actually, the above timing adjustment may be performed only on either one of the current differential relays 53A and 53B at both ends of the power transmission line 50 . For example, a predetermined one (slave) of the current differential relays 53A and 53B performs timing adjustment based on information indicating the above-described time interval received from the other (master).

In order to accurately perform the basic synchronization process described above, the transmission time through the communication path 54 from the A end to the B end of the power transmission line 50 and the transmission time through the communication path 54 from the B end to the A stage are mutually exclusive. There is a prerequisite for equality. If these transmission times are different, the sampling synchronization error becomes 1/2 of the difference of the respective transmission times. In the case of using a general-purpose communication device, even if the length of the communication path from stage A to stage B and the length of the communication path from stage B to A are the same, the difference in transmission time is at most several 100 µs. There are cases.

Therefore, the current differential relay 53 of the present disclosure performs sampling synchronization processing using the voltage data and current data of both ends of the power transmission line 50 . Specifically, the current differential relay 53 calculates the voltage of a specific point on the power transmission line 50 using the voltage data and current data of the A stage, and uses the voltage data and the current data of the B stage to the specific point. Calculate the voltage of The current differential relay 53 performs sampling synchronization of both ends of the power transmission line 50 based on the calculated phase difference of the positive voltages. The above-described specific point may be stage B. In this case, the current differential relay 53 calculates the voltage at stage B using the voltage data and current data at stage A, and actually detects the calculated voltage at stage B. Sampling synchronization of both ends of the power transmission line 50 is performed based on the phase difference of the voltage of one B stage.

Hereinafter, this sampling synchronization method is called a sampling synchronization method based on a voltage phase difference. The sampling synchronization processing based on the voltage phase difference may be used to supplement the synchronization processing based on the time interval between the transmission time and the reception time of the timing signal described above, or may be used instead of the synchronization processing described above. A basic way of thinking of sampling synchronization processing based on this voltage phase difference will be described later with reference to Figs.

[An example of hardware configuration of current differential relay]

FIG. 2 is a block diagram showing an example of a hardware configuration of each current differential relay in FIG. 1 . The current differential relay 53 in Fig. 2 has the same configuration as a so-called digital relay device. Specifically, referring to FIG. 2, the current differential relay 53 includes an input conversion unit 100, an A/D (analog/digital) conversion unit 110, an arithmetic processing unit 120, and an I/O ( Input and Output) unit 130 is provided.

The input conversion unit 100 includes auxiliary transformers 101_1, 101_2, ... for each input channel. The input converter 100 receives a current signal from the current transformer CT and a voltage signal from the voltage transformer VT of FIG. 1 . Each auxiliary transformer 101 converts the current signal from the current transformer CT and the voltage signal from the voltage transformer VT to a voltage level suitable for signal processing in the A/D converter 110 and the arithmetic processing unit 120 . converted to a signal of

The A/D converter 110 includes an analog filter (AF: Analog Filter) (111_1, 111_2, …), a sample hold circuit (S/H: Sample Hold Circuit) (112_1, 112_2, …), and a multiplexer ( MPX: Multiplexer) 113 and an A/D converter 114 are included. The analog filter 111 and the sample and hold circuit 112 are provided for each channel of the input signal.

Each analog filter 111 is a low-pass filter provided in order to remove a return error at the time of A/D conversion. Each sample and hold circuit 112 samples and holds a signal that has passed through the corresponding analog filter 111 at a prescribed sampling frequency. The sampling frequency is 4800 Hz, for example. The multiplexer 113 sequentially selects the voltage signals held in the sample and hold circuits 112_1, 112_2, .... The A/D converter 114 converts the signal selected by the multiplexer 113 into a digital value.

The arithmetic processing unit 120 includes a central processing unit (CPU) 121 , a random access memory (RAM) 122 , a read only memory (ROM) 123 , and a bus 124 connecting them. . The CPU 121 controls the overall operation of the current differential relay 53 . The RAM 122 and the ROM 123 are used as main memory of the CPU 121 . The ROM 123 can store a program and set values for signal processing, etc. by using a nonvolatile memory such as a flash memory.

In addition, the arithmetic processing part 120 should just be comprised by any one circuit, and it is not limited to the example of FIG. For example, the arithmetic processing unit 120 may include a plurality of CPUs. In addition, the arithmetic processing unit 120 may be configured by at least one ASIC (Application Specific Integrated Circuit) or by at least one FPGA (Field Programmable Gate Array) instead of a processor such as a CPU. . Alternatively, the arithmetic processing unit 120 may be configured by a combination of any one of a processor, an ASIC, and an FPGA.

The I/O unit 130 includes a transceiver (TX/RX) 131 and a digital input (D/I: Digital Input) circuit 132 and a digital output (D/O: Digital Output) circuit 133 . includes The transceiver 131 includes a transmitter 131_1 and a receiver 131_2, and communicates with the transceiver 131 provided in the current differential relay 53 of the opposite end through the communication path 54 of FIG. 1 . The digital input circuit 132 and the digital output circuit 133 are interface circuits for communication between the CPU 121 and an external device. For example, the digital output circuit 133 outputs a trip signal to the circuit breaker 68A or 68B on the self-end side shown in FIG.

[Sampling synchronization method based on voltage phase difference]

(equivalent circuit by normal circuit)

In the case of performing the sampling synchronization processing based on the voltage phase difference in a state where there is no failure in the power transmission line 50, the synchronization processing may be performed using the voltage data and current data of any one of the three phases. In the present disclosure, in consideration of detection errors of currents and voltages, sampling synchronization processing is performed using the stationary currents and stationary voltages of the symmetric coordinate method for the purpose of leveling the detection errors.

3 is an equivalent circuit diagram of a normal circuit in the case where there is no failure in the power transmission system of FIG. 1 . Referring to FIG. 3 , the normal voltage of the A terminal is V1, and the normal current of the A terminal is I1. Similarly, the steady-state voltage of the B-stage is Vs1, and the steady-state current of the B-stage is Is1.

As is well known, the normal voltage (V1) is obtained by using the three-phase voltages (Va, Vb, Vc) of terminal A,

V1 = (Va+α·Vb+α ² ·Vc)/3 … (One)

is displayed as The normal current I1 is obtained by using the three-phase currents Ia, Ib, Ic of A stage,

I1=(Ia+α·Ib+α ² ·Ic)/3 … (2)

is displayed as However, if the imaginary unit is j,

α=(-1+j·√3)/2 … (3)

this is accomplished The same is true for stage B. In addition, in this specification, the multiplication symbol is represented by "·", "*", or "x".

Let the normal impedance of the power transmission line 50 be Z1, and let the earth capacitance of the power transmission line 50 be C (it may simply be described as the earth capacitance C). The charging current Ic corresponds to the current flowing through the earth capacitance C. In addition, the resistance, the inductive resistance, and the capacity of the power transmission line 50 are expressed as distributed constants, which are expressed as concentrated constants for simplicity. Hereinafter, for the sake of simplicity, the normal voltage, the normal current, the normal impedance, etc. are only described as voltage, current, and impedance in some cases.

(Charging current of transmission line)

FIG. 4 is a diagram for explaining a charging current in the normal circuit of FIG. 3 . In Fig. 4, the position of the stage A is indicated by x=0, and the position of the stage B is indicated by x=1. That is, the length of the power transmission line 50 is standardized as 1.

Fig. 4(A) shows the voltage change on the power transmission line when there is a voltage difference between the self-end voltage V1 and the opposite-end voltage Vs1. Originally, the voltages V1 and Vs1 should be shown as vectors (ie, voltage amplitude and phase), but as in the graph 60, they are simply illustrated so as to have a difference in scalar (ie, voltage amplitude only). In reality, there is a case where there is no difference in amplitude and there is a phase difference between the voltages V1 and Vs1 in many cases.

A graph 61 of FIG. 4B shows the change of the load current on the power transmission line. As described above, a load current flows due to the difference in voltage vectors at both ends of the power transmission line 50 . The load current at the A stage is I1, and the load current at the B stage is Is1. In addition, the direction of the load current Is1 from the B stage to the A stage is positive.

The charging current Ic(x) to a point x on the transmission line depends on the voltage V(x) of the transmission line at the point x. The relation is that the capacitance per unit length of the transmission line is C,

Ic(x)=jωC V(x) … (4)

is displayed as At stage A, that is, at x = 0,

Ic(0)=jωC·V1 … (5)

is established, and in stage B, that is, x = 1,

Ic(1)=jωC·Vs … (6)

this is accomplished Accordingly, the total amount of the charging current Ic of the power transmission line 50 is expressed by the following formula (7). Here, x represents a position on the power transmission line, and the A end of the power transmission line 50 is set to x=0, and the B end of the power transmission line 50 is set to x=1.

[Formula 1]

(Sampling synchronization based on voltage phase difference when there is no load current)

When there is no load current, the A-stage voltage V1 and the B-stage voltage Vs1 become equal (refer to the graph 62 of Fig. 4A). In this case, the phase difference between the A-stage voltage V1 and the B-stage voltage Vs1 is at a negligible level, but in reality, a deviation occurs in the timing of sampling at both ends of the power transmission line 50, so the A-stage voltage A phase difference φ occurs between (V1) and the B-stage voltage (Vs1).

5 is a vector diagram showing an example of the phase difference between the A-stage voltage V1 and the B-stage voltage Vs1. In the vector diagram of FIG. 5 , the B-stage voltage Vs1 precedes the A-stage voltage V1 by the phase difference φ. Therefore, for sampling synchronization, it is necessary to advance the sampling time of stage B by the time t corresponding to the phase difference φ, or delay the sampling time of stage A by the time t corresponding to the phase difference φ. there is. The time t is, if the unit of the phase difference φ is degrees,

t=(φ/360°)*time of 1 cycle … (8)

is displayed as If the AC frequency is f, the time of one cycle is 1/f [sec].

[Combination of two sampling synchronization methods]

Next, a method of combining the above-described sampling synchronization method based on the voltage phase difference with the sampling synchronization method based on the time interval between the transmission time and the reception time of the above-described timing signal will be described.

6 is a timing diagram for explaining a sampling synchronization method. 5, it is assumed that the B-stage voltage Vs1 precedes the A-stage voltage V1 by a phase difference ?. Let the time corresponding to the phase difference phi be t.

Referring to FIG. 6A , the timing signal transmitted from terminal A at time t1 is received from terminal B at time t4, and the timing signal transmitted from terminal B at time t2 is time t3. It is said to have been received from stage A. In this case, the time interval T1 (that is, from time t1 to time t3) between the transmission time and reception time of the timing signal in stage A is the transmission time and reception time of the timing signal in stage B. is said to be equal to the time interval T2 (ie, from time t2 to time t4). However, the timing of sampling in stage B is delayed by time t from the timing of sampling in stage A.

In the above case, the signal transmission time from stage B to stage A becomes T1-t, and the signal transmission time from stage A to stage B becomes T1+t. Therefore, that the sampling synchronization is achieved by correcting the sampling timing at the B stage to advance by the time t of the above equation (8) means the transmission from the stage B to the stage A through the communication path 54 in FIG. This means that the time is shorter than the transmission time from stage A to stage B by 2xt.

Referring to FIG. 6B, the time interval between the transmission time and the reception time of the timing signal in stage A is T3, and the time interval between the transmission time and reception time of the timing signal in stage B is T4. In this case, the current differential relay 53 of either stage A or stage B (for example, the slave side) operates so that the time interval T3 is longer than the time interval T4 by 2xt. Adjusts the sampling timing and the timing of transmitting the timing signal. Thereby, sampling synchronization at stage A and stage B can be realized.

Specifically, as shown in Fig. 6(B), it is assumed that timing signals are transmitted to the opposite end from stage A and stage B at time t11. Therefore, the timing signal transmitted from the A stage is received by the B stage at a time t13 when the time t13 when the timing signal transmitted from the B stage is received at the A stage t12 has elapsed.

As a result, even if there is a difference in the transmission time of the communication path 54 up and down (that is, from the own end to the other end and from the other end to the other end), the amount of electricity at a more correct timing by sampling synchronization processing based on the voltage phase difference sampling is possible. As a result, the protection characteristics of the transmission line by the current differential relay are improved.

As shown by the graph 60 of FIG. 4A, when the load current is influenced, a voltage difference occurs between the A-stage voltage V1 and the B-stage voltage Vs1. A sampling synchronization method applicable even in this case will be described below with reference to Figs. 7 to 14 as the first embodiment.

In addition, when there is no system failure in the transmission line and the load current flowing through the transmission line is negligibly small, only the charging current flows through the current transformers CT1 and CT2 provided in the A and B stages. Therefore, the threshold of current detection in the current differential relay 53 is set in advance so that this charging current is not detected (that is, slightly larger than the size of the charging current). And, when the load current cannot be detected (that is, below the threshold), the phase difference is calculated from the voltages at both ends of the power transmission line 50, and a time corresponding to the phase difference (Equation (8) above) is used. , it is possible to almost accurately detect the vertical difference in the transmission time of the communication path 54 . Therefore, when the current values at both ends of the power transmission line 50 do not exceed the threshold value, using the time t corresponding to the phase difference measured in advance by the above method, the transmission time of up and down the power line 50 is 2× Assuming that there is a difference of t, timing synchronization processing based on the time interval between the transmission time and the reception time of the timing signal can be executed.

<Sampling synchronization method according to the first embodiment>

In the first embodiment, by simulating the power transmission line 50 as a π-type circuit, it is assumed that the charging current flows in each terminal by half, and using the terminal current compensating for the charging current, at the midpoint of the power transmission line 50 How to calculate the voltage of A midpoint is more generally referred to as a specific point. In the case of Embodiment 1, the voltage at the midpoint calculated using the current and voltage of the A stage (also referred to as the first specific point voltage) and the voltage at the midpoint calculated using the current and the voltage at the B stage (the second The phase difference of the specific point voltage) is obtained, and the sampling timing is corrected from the time corresponding to the phase difference.

In this way, by taking the charging current into the calculation, it is possible to further reduce the sampling synchronization error even when there is an influence of the load current. Hereinafter, it will be described in detail with reference to the drawings.

[Equivalent circuit of transmission line]

Fig. 7 is an equivalent circuit diagram of a normal circuit of a power transmission system simulated by a ?-type circuit. In addition, simulating the entire power transmission line as a π-type circuit is to simulate the first line from the A stage to the midpoint 57 including the earth capacitance (C/2) as an L-shaped circuit, and from the B stage to the earth capacitance ( It can be considered that the second line up to the midpoint 57 including C/2) is simulated by another L-type circuit.

Referring to FIG. 7 , the normal voltage of the A terminal is V1, and the normal current of the A terminal is I1. Similarly, the steady-state voltage of the B-stage is Vs1, and the steady-state current of the B-stage is Is1.

Let C be the total amount of the ground capacity in the entire power transmission line 50 . In the ?-type circuit, a capacitor having a size of 1/2 of the ground capacitance C is connected to the A terminal, and a capacitor having a size of 1/2 of the ground capacitance C is connected to the B terminal. As a result, the charging current Ic flows through the A terminal, and the charging current Ics flows through the B terminal.

Let the normal impedance of the entire power transmission line 50 be Z1. So, the line impedance from the A terminal to the midpoint 57 of the power transmission line 50 is represented by Z1/2, and the line impedance from the B terminal to the midpoint 57 of the power transmission line 50 is represented by Z1/2. do.

Let Vf be the voltage at the midpoint 57 calculated from the current I1 and voltage V1 of the A stage, and the voltage at the midpoint 57 calculated from the current Is1 and the voltage Vs1 in the B stage Vsf. Further, the position of the stage A is set to x=0, the position of the stage B is set to x=1, and the position of the intermediate point is set to x=1/2.

[About charging current]

FIG. 8 is a diagram for explaining a charging current in the normal circuit of FIG. 7 . Fig. 8(A) shows the voltage change on the power transmission line when there is a voltage difference between the self-end voltage V1 and the opposite-end voltage Vs1. The graph 64 schematically shows the case where the voltages V1 and Vs1 are expressed as vectors (that is, expressed by voltage amplitude and phase), and there is a phase difference from the amplitude. The graph 63 is simply illustrated so that there is a difference in the scalar (that is, only the voltage amplitude).

A graph 65 of FIG. 8B shows the change of the load current on the power transmission line. A load current obtained by subtracting the charging current Ic from the terminal current I1 flows in the terminal A, and a load current obtained by subtracting the charging current Ics from the terminal current Is1 flows in the B terminal.

[Functional configuration example of current differential relay]

Fig. 9 is a block diagram showing the functional configuration of the current differential relay according to the first embodiment. 9 shows the functional configuration of the current differential relay 53A of stage A, the same is true of the current differential relay 53B of stage B. In addition, the functional block diagram of FIG. 9 is also applied to other embodiment mentioned later.

Functionally, the arithmetic processing unit 120 of the current differential relay 53A includes a self-end data accumulation unit 70, a transmission data processing unit 71, a reception data processing unit 72, a synchronization processing unit 73, It includes a voltage calculating unit 74 , a phase difference calculating unit 75 , and a relay calculating unit 76 . These functions are realized by executing the program by the CPU 121 of the arithmetic processing unit 120 .

Referring to FIG. 9 , the signal representing the current and voltage of the self-end received by the input conversion unit 100 is converted into a digital value by the A/D conversion unit 110 and is stored in the self-end data accumulation unit 70 . are housed Thereafter, the data is processed as transmission data by the transmission data processing unit 71 in order to be transmitted to the opposite end relay. Transmission data is transmitted to the receiver (RX131_2) of the relay at the opposite end by the transmitter (TX131_1). On the other hand, the reception data from the transmitter 131_1 of the opposite terminal relay received by the receiver RX131_2 (that is, the current data and voltage data of the opposite terminal) is the reception data processing unit 72, the opposite terminal data for calculation. is processed with

In order to synchronize the sampling time of the data acquired by the relay of both ends of a power transmission line, the synchronization processing part 73 performs a sampling synchronization process with respect to the self-end data and the opposite-end data for calculation. Specifically, synchronization processing is performed based on the time interval between the transmission time and the reception time of the above-described timing signal.

For the calculation in the voltage calculating section 74, the data of the own end and the data of the opposite end after the above-described synchronization processing are used. Specifically, the voltage calculating unit 74 uses the current I1 and the voltage V1 of the self-end to the voltage Vf of a specific point on the power transmission line 50 (the intermediate point 57 in the case of the first embodiment). and calculates the voltage (Vsf) at a specific point using the current (Is1) and the voltage (Vs1) of the opposite end. In this calculation, the impedance Z1 of the power transmission line 50 and the earth capacitance C of the power transmission line 50 are used.

The phase difference calculating part 75 calculates the phase difference phi between the voltage Vf of the specific point calculated based on the self-end data, and the voltage Vsf of the specific point calculated based on the opposite-end data. The phase difference calculating part 75 further calculates|requires the time t corresponding to the calculated phase difference phi, and feeds back information of this time t to the synchronization processing part 73. Alternatively, the phase difference calculating unit 75 calculates the difference between the transmission time from the own end to the opposite end and the transfer time from the opposite end to the own end (that is, 2 × t when T1 = T2 in Fig. 6(A)) to the synchronization processing unit ( 73) may be fed back.

The synchronization processing unit 73 performs sampling synchronization processing on the self-end data and the opposite-end data for calculation based on the transmission time difference detected by the phase difference calculation unit 75 . Specifically, as described in Fig. 6B, the time interval between the transmission time and the reception time of the timing signal in stage A is T3, and the time interval between the transmission time and reception time of the timing signal in stage B is set to T3. At T4, the sampling timing is adjusted so that the time interval T3 and the time interval T4 differ by the transmission time difference. Alternatively, the synchronization processing unit 73, not based on the transmission time difference, sets the sampling time by the time t corresponding to the phase difference φ (that is, so that the time corresponding to the current phase difference φ becomes 0). It may be corrected.

In addition, the synchronization processing unit 73, when the opposite terminal relay is the master (when it is a slave), the time t corresponding to the phase difference φ obtained by the phase difference calculating unit 75 is 0, A Controls the sampling timing in the /D converter 110 . Thereby, the sampling timing of the own end is synchronized with the sampling timing of the opposite end.

The relay arithmetic unit 76 uses the data of the current Is1 of the opposite end and the data of the self-end current I1 synchronized with the data of the current Is1 of the opposite end, and based on the difference between these data, the transmission line ( 50), it is determined whether there is a failure in the protection section.

Any well-known method can be used for the calculation of the phase difference in the phase difference calculating part 75 mentioned above.

For example, the sampling interval of the voltages Vf and Vsf is set to every 30°, the current values of the voltages Vf and Vsf are Vf[m] and Vsf[m], respectively, and the value 90° before the present time is Vf [m-3] and Vsf[m-3]. Then, the cosine and sine of the phase difference φ between the voltage Vf[m] and the voltage Vsf[m] use the amplitude |Vf| of the voltage Vf and the amplitude |Vsf| of the voltage Vsf So,

|Vf|×|Vsf|×cosφ=Vf[m]×Vsf[m]+Vf[m-3]×Vsf[m-3] … (9)

|Vf|×|Vsf|×sinφ=Vf[m-3]×Vsf[m]-Vf[m]×Vsf[m-3] … (10)

is displayed as

[Sampling Synchronous Sequence - Part 1]

10 is a flowchart showing the procedure of sampling synchronization processing according to the first embodiment. Hereinafter, the procedure of the sampling synchronization process will be described in more detail mainly with reference to Figs. 7, 9, and 10. Figs. In the following description, stage A is referred to as a rose end, and stage B is referred to as an opposite end.

First, the A/D converter 110 of FIG. 9 generates current data I1 and voltage data V1 by sampling the current and voltage of its own end (step S101).

Next, the voltage calculating unit 74 calculates the charging current Ic using the self-end voltage V1 (step S102). Assuming that the imaginary unit is j and each frequency of the AC voltage of the power transmission line 50 is ω, the charging current Ic is

Ic=jω(C/2)*V1 … (11)

is displayed as Here, C is the total amount of land capacity of the transmission line, and Ic is the charging current from the self-end of the line to the midpoint 57 (that is, in 1/2 of the entire line).

Then, the voltage calculating unit 74 calculates the midpoint voltage Vf by using the value I1-Ic obtained by subtracting the charging current Ic from the self-end current I1 and the self-end voltage V1. do (step S103). Specifically, the midpoint voltage (Vf) is,

Vf=V1-(Z1/2)*(I1-Ic) … (12)

is displayed as The second term on the right side of the above equation (12) represents the voltage drop by the power transmission line 50 from the self-end to the midpoint 57.

Next, the receiver 131_2 receives the sampling values of the current and voltage of the opposite end (that is, the current data Is1 and the voltage data Vs1) (step S104). The received current data Is1 and voltage data Vs1 are received by the reception data processing unit 72 . Note that step S104 may be executed before step S102. Note that steps S102 and S103 described above may be executed in parallel with steps S105 and S106.

Next, the voltage calculating unit 74 calculates the charging current Ics using the opposite terminal voltage Vs1 (step S105). Specifically, the charging current (Ics) is,

Ics=jω(C/2)*Vs1 … (13)

and represents the charging current in the line from the opposite end to the midpoint 57 (that is, in 1/2 of the entire line).

Next, the voltage calculating unit 74 uses the value Is1-Ics obtained by subtracting the charging current Ics from the opposite-end current Is1 and the opposite-end voltage Vs1 to obtain a midpoint voltage Vsf is calculated (step S106). Specifically, the midpoint voltage (Vsf) is,

Vsf=Vs1-(Z1/2)*(Is1-Ics) … (14)

is displayed as The second term on the right side of the above equation (14) represents the voltage drop by the power transmission line 50 from the opposite end to the midpoint 57.

Next, the phase difference calculating part 75 calculates the phase difference phi of the midpoint voltages Vs and Vsf (step S107). Further, the phase difference calculating unit 75 calculates a delay time (or a preceding time) corresponding to the calculated phase difference ? and outputs it to the synchronization processing unit 73 . The synchronization processing unit 73 corrects the sampling time only by the delay time or the preceding time (step S108). That is, the synchronization processing unit 73 controls the sampling time of the current and voltage at the self-end so that the time t corresponding to the phase difference phi becomes zero.

The midpoint voltage Vf calculated in equation (12) and the midpoint voltage Vsf calculated in equation (14) are the same voltage vector when sampling synchronization at both ends of the power transmission line 50 is achieved. indicates. When sampling synchronization is not taken, a phase difference occurs in the midpoint voltages Vs and Vsf. Therefore, the sampling timing can be synchronized by measuring the phase difference and performing synchronization correction for a time corresponding to the phase difference.

11 is a vector diagram showing an example of the phase difference between the midpoint voltages Vf and Vfs. In Fig. 11, the phase of the midpoint voltage Vf calculated from the self-end voltage V1 and the self-end current I1 is the midpoint voltage Vsf calculated from the opposite-end voltage Vs1 and the opposite end current Is1. It shows an aspect that precedes the phase by φ. Therefore, the timing of sampling at the own end precedes the timing of sampling at the opposite end by the phase angle ?. Therefore, in the sampling synchronization process, the time t corresponding to the phase difference φ for the sampling time of the self-end, that is,

t=(φ/360°)×1 cycle time … (15)

It is corrected in the delay direction as much as If the AC frequency is f, the time of one cycle is 1/f [sec]. The cycle time of one cycle is expressed as 1/f when the AC frequency is f.

By performing the sampling synchronization process in the above-described order, sampling synchronization with less influence of the load current due to the voltage difference between the ends of the power transmission line 50 becomes possible. Thereby, the protection characteristic of the power transmission line by a current differential relay is improved.

[Sampling Synchronization Sequence - Part 2]

The sampling synchronization processing based on the voltage phase difference cannot be applied when the phases of the voltage and current at the A and B terminals are affected by a failure or the like on the power transmission line. In addition, if at least one of the circuit breakers 68A and 68B provided in the power transmission line 50 between the A and B terminals or a disconnector (not shown) is in an open state, etc. , the sampling synchronization processing based on the voltage phase difference described above cannot be applied. Incidentally, the sampling synchronization processing based on the voltage phase difference is premised on that the absolute value of the voltage phase difference to be measured is less than 180 degrees, and therefore cannot be applied when the deviation of the timing to be synchronized is too large.

In such a case, as described with reference to Figs. 6A and 6B, the sampling synchronization process can be executed by combining the sampling synchronization method based on the time interval between the transmission time and the reception time of the timing signal. Hereinafter, it will be described in detail with reference to FIGS. 1, 9 and 12 . In addition, the following procedure is similarly applicable also to other embodiment mentioned later.

12 is a flowchart showing another sampling synchronization procedure. In the initial state, a failure does not occur in the power transmission line 50, and the circuit breaker and disconnector provided between the terminals are assumed to be in the closed state.

First, in step S701, the transmitter 131_1 of the current differential relay 53A of stage A transmits a timing signal together with current data and voltage data of its own stage to the current differential relay 53B of stage B. Similarly, the transmitter 131_1 of the current differential relay 53B of stage B transmits a timing signal together with current data and voltage data of its own stage to the current differential relay 53A of stage A.

In the next step S702, the receiver 131_2 of the current differential relay 53A of the A stage receives the timing signal together with the current data and the voltage data from the other end. Similarly, the receiver 131_2 of the current differential relay 53B of stage B receives a timing signal together with current data and voltage data from the other end.

In addition, each of the current differential relays 53A and 53B calculates a time interval between the transmission time of the timing signal from its own end and the reception time of the timing signal from the opposite end. The current differential relays 53A and 53B transmit the calculated time intervals between the transmission time and the reception time of the timing signal opposite to each other. The calculation of this time interval and transmission of the calculation result may be performed, for example, about once per cycle of the power system.

In the next step S703, the synchronization processing unit 73 of the current differential relay 53A in the A stage is configured to determine the time interval T1 between the transmission time and the reception time of the timing signal at the own end side, the transmission time of the timing signal at the opposite end side, and The sampling time of the current and voltage in the A/D conversion unit 110 of the current differential relay 53A of stage A is controlled so that the time interval T2 of the reception time becomes equal.

As a result, when it is determined that synchronization is achieved, that is, when the time interval T1 and the time interval T2 are equal (YES in step S704), in the next step S705, the current differential relay 53A of stage A The phase difference calculating unit 75 of , as described in steps S101 to S107 of FIG. 10 described above, is a specific point voltage Vs based on current data and voltage data of its own stage, and a specific point voltage Vs based on current data and voltage data of the other stage. Calculate the phase difference (φ) of the point voltage (Vsf). Here, the specific point is an intermediate point between the A and B ends. Then, the synchronization processing unit 73 stores the time t corresponding to the phase difference φ as a specific time interval Ts in a memory (for example, the RAM 122 or ROM 123 in FIG. 2 ). do. 6(A) and (B), twice the specific time interval Ts is the transmission time of the communication path from stage A to stage B and the transmission time of the communication path from stage B to stage A. equivalent to the car.

After that, as in the case of steps S701 and S702, first, in step S706, the transmitter 131_1 of the current differential relay 53A of stage A transmits the timing signal together with the current data and voltage data of the stage B to the current of stage B. It transmits to the differential relay 53B. Similarly, the transmitter 131_1 of the current differential relay 53B of stage B transmits a timing signal together with current data and voltage data of its own stage to the current differential relay 53A of stage A.

In the next step S707, the receiver 131_2 of the current differential relay 53A in the A stage receives the timing signal together with the current data and the voltage data from the other end. Similarly, the receiver 131_2 of the current differential relay 53B of stage B receives a timing signal together with current data and voltage data from the other end.

In addition, each of the current differential relays 53A and 53B calculates a time interval between the transmission time of the timing signal from its own end and the reception time of the timing signal from the opposite end. The current differential relays 53A and 53B transmit the calculated time intervals between the transmission time and the reception time of the timing signal opposite to each other. The calculation of this time interval and transmission of the calculation result may be performed, for example, about once per cycle.

Synchronization processing is executed in the following steps S708 to S711. The execution frequency of this synchronization process may be, for example, about once every several cycles.

Specifically, in step S708, the synchronization processing unit 73 of the current differential relay 53A of the A stage is configured with the time interval T1 between the transmission time and the reception time of the timing signal at the own end side, the transmission time of the timing signal at the opposite end side, and The current and voltage in the A/D conversion unit 110 of the current differential relay 53A of stage A so that the time interval T2 of the reception time differs by twice the specific time interval Ts obtained in step S705. control the sampling time of

For example, in step S705 described above, the specific point voltage Vsf based on the current data and voltage data of stage B is higher than the specific point voltage Vs based on the current data and voltage data of stage A, the phase difference ( It is said that it precedes by φ). In this case, as described with reference to Fig. 6(A), the transmission time through the communication path 54 from the A stage to the B stage is 2x longer than the transmission time through the communication path 54 from the B stage to the A stage. Only Ts is long. Accordingly, the sampling timing at stage A is controlled so that the time interval T1 is shorter than the time interval T2 by 2×Ts.

Conversely, in step S705 described above, the specific point voltage Vsf based on the current data and voltage data of stage B is higher than the specific point voltage Vs based on the current data and voltage data of stage A, the phase difference φ ) is said to be delayed. In this case, the transmission time from the stage A to the stage B through the communication path 54 is shorter than the transmission time from the stage B to the stage A through the communication path 54 by 2xTs. Accordingly, the sampling timing at stage A is controlled so that the time interval T1 is longer than the time interval T2 by 2×Ts.

When it is determined by execution of step S708 that synchronization is achieved, that is, when the difference between the time interval T1 and the time interval T2 is equal to 2 x Ts (YES in step S709), and the power transmission line fails If this does not occur and the circuit breaker or the like between both ends of the power transmission line is not opened (NO in step S710), the flow advances to step S711 for correcting the above-described specific time interval Ts. The reason for performing the correction of the specific time interval Ts in this way is due to the influence of measurement errors, jitter, wander, and fluctuations in device characteristics (eg clock fluctuations) This is because there is a possibility that the transmission time difference (2 x Ts) obtained in S705 may fluctuate. For other reasons, if an abnormality occurs in the transmission path between the current differential relay 53A of stage A and the current differential relay 53B of stage B, the transmission route may be changed, and this transmission route switching is This is because there is a possibility accompanying a change in the transmission time difference.

In step S711, the phase difference calculating unit 75 of the current differential relay 53A of the A stage is a specific point voltage Vs based on the current data and voltage data of its own stage, and the specific point based on the current data and voltage data of the other stage. Calculate the phase difference (φ) of the voltage (Vsf). Here, the specific point is an intermediate point between the A and B ends. Then, the synchronization processing unit 73 corrects the specific time interval Ts by adding or subtracting the time t′ corresponding to the phase difference φ to the current specific time interval Ts. A more detailed correction method will be described later with reference to FIG. 14 .

Thereafter, steps S706 to S711 are repeated. Accordingly, step S708 is executed using the specific time interval Ts corrected in step S711. In addition, in the case where a failure does not occur in the power transmission line and the circuit breaker between both ends of the power transmission line is not opened (NO in step S710), step S711 is repeatedly executed, so that the specific time interval Ts is continuously corrected.

On the other hand, if a failure occurs in the power transmission line or the circuit breaker between both ends of the transmission line is open (YES in step S710), step S711 for correcting the specific time interval Ts is not executed, and the transmission line is faulty. The synchronization process of step S708 is continued using the corrected specific time interval Ts immediately before generation or immediately before opening of the circuit breaker or the like.

Here, the failure of the power transmission line 50 may be detected by the current differential relays 53A and 53B, or may be detected by another method. For example, a sudden change in terminal current may be detected by a current change width relay, or a failure detection signal may be received from another protection relay. In addition, the open/close state of the circuit breakers 68A and 68B and disconnectors not shown is determined by the current differential relays 53A and 53B receiving a signal indicating the opening/closing state output from these circuit breakers 68A and 68B and the disconnector. You may make it detectable.

According to the above procedure shown in Fig. 12, even when a power transmission line has a failure or a circuit breaker provided between both ends of the power transmission line is opened, sampling synchronization processing with higher accuracy than the prior art can be realized. In addition, in the above description, it has been described that the current differential relay 53A of stage A is the slave side, and the current differential relay 53A of stage A adjusts the sampling timing of its own stage. Conversely, the current differential relay 53B of stage B may adjust the sampling timing of its own stage.

FIG. 13 is a diagram for explaining the procedure of step S711 in FIG. 12 in more detail. Figs. 13(A) to (D) are based on Figs. 6(A) and (B).

First, referring to FIG. 6(A), the time interval T1 between the transmission time t1 and the reception time t3 of the timing signal in stage A, the transmission time t2 of the timing signal in stage B, It is assumed that the time interval T2 of the reception time t4 is equal. At this time, when the specific point voltage (Vs) based on the voltage data and current data at the A terminal is compared with the specific point voltage (Vsf) based on the voltage data and the current data at the B terminal, the specific point voltage (Vsf) is It is said that the phase difference φ precedes the specific point voltage Vs. In this case, assuming that the time corresponding to the phase difference ? is t, the transmission time from stage A to stage B through the communication path is longer than the transmission time from stage B to stage A by 2xt. In this specification, t (ie, 1/2 of the transmission time difference) in this case is referred to as a specific time interval Ts.

Therefore, in the case of Fig. 6(A), as shown in Fig. 6(B), the time interval T1 between the transmission time and the reception time of the timing signal in stage A (corresponding to T3 in Fig. 6(B)). A value obtained by adding 2×Ts (corresponding to 2×t in FIG. 6(B)) to the time interval T2 between the transmission time and reception time of the timing signal in stage B (to T4 in FIG. 6(B)) Sampling synchronization can be realized by controlling the sampling timing at stage A or stage B so that the corresponding) becomes equal. However, even if corrected so that T1+2×Ts=T2, due to measurement errors, jitter, wander, fluctuations in device characteristics (eg clock fluctuations, etc.), and signal fluctuations, etc. In a normal case, perfect sampling synchronization is not continuously realized. In addition, if an abnormality occurs in the communication path between the transmission device at stage A and the transmission device at stage B, the transmission route may be switched. Therefore, the precision of sampling synchronization is increased by continuously correcting the specific time interval Ts. Hereinafter, it will be described in detail with reference to Figs. 13(A) to (D).

Referring to FIG. 13A , as in the case of FIG. 6B , it is assumed that the sampling timing at stage A or stage B is adjusted so that T1+2×Ts=T2. In this case, when the specific point voltage (Vs) based on the voltage data and current data at the A terminal is compared with the specific point voltage (Vsf) based on the voltage data and the current data at the B terminal, the specific point voltage ( It is assumed that Vsf) precedes the specific point voltage Vs by the phase difference ?. Assuming that the time corresponding to the phase difference ? is t', this means that the sampling timing of stage B is delayed by t' from the sampling timing of stage A.

Therefore, as shown in Fig. 13B, sampling synchronization can be realized by controlling the sampling timing at stage A or stage B so that T1+2xTs+2xt'=T2. In other words, by correcting the specific time interval Ts to add the time t' (that is, by correcting Ts'=Ts+t' when the specific time interval after correction is Ts'), sampling synchronization can be realized. can

Referring to FIG. 13(C) , as in the case of FIG. 6(B), it is assumed that the sampling timing at stage A or stage B is adjusted so that T1+2×Ts=T2. In this case, the specific point voltage (Vs) based on the voltage data and current data at the A stage is compared with the specific point voltage (Vsf) based on the voltage data and the current data at the B stage. ), it is assumed that the specific point voltage Vsf is delayed by the phase difference φ from the specific point voltage Vs. If the time corresponding to the phase difference phi is t', this means that the sampling timing of stage B is earlier than the sampling timing of stage A by t'.

Therefore, as shown in Fig. 13(D), sampling synchronization can be realized by controlling the sampling timing at stage A or stage B so that T1+2 x Ts-2 x t' = T2. In other words, by correcting the specific time interval Ts to subtract the time t' (that is, by correcting Ts'=Ts-t' when the specific time interval after correction is Ts'), sampling synchronization can be realized. can

In the case of the opposite phase relationship to the above example, it is easily understood by those skilled in the art that if stage A and stage B are exchanged in the above description, the above description holds almost as it is.

[Sampling Synchronous Sequence - Part 3]

14 is a flowchart showing still another sampling synchronization procedure. The sampling synchronization procedure of Fig. 14 shows a modification of the sampling synchronization procedure of Fig. 12, and is characterized in that only synchronization processing based on the voltage phase difference is performed in the normal time of the power transmission line.

Referring to FIG. 14 , in an initial state, a failure does not occur in the power transmission line 50, and a circuit breaker provided between terminals is said to be in a closed state.

First, in step S801, the transmitter 131_1 of the current differential relay 53A of stage A transmits a timing signal together with current data and voltage data of its own stage to the current differential relay 53B of stage B. Similarly, the transmitter 131_1 of the current differential relay 53B of stage B transmits a timing signal together with current data and voltage data of its own stage to the current differential relay 53A of stage A.

In the next step S802, the receiver 131_2 of the current differential relay 53A of the A stage receives the timing signal together with the current data and the voltage data from the other end. Similarly, the receiver 131_2 of the current differential relay 53B of stage B receives a timing signal together with current data and voltage data from the other end.

In addition, each of the current differential relays 53A and 53B calculates a time interval between the transmission time of the timing signal from its own end and the reception time of the timing signal from the opposite end. The current differential relays 53A and 53B transmit the calculated timing signal transmission/reception time intervals to each other. The calculation of this time interval and transmission of the calculation result may be performed, for example, about once per cycle.

In the next step S803, the synchronization processing unit 73 of the current differential relay 53A of the stage A determines the time interval T1 between the transmission time and the reception time of the timing signal at the own end side, the transmission time of the timing signal at the opposite end side, and The sampling time of the current and voltage in the A/D conversion unit 110 of the current differential relay 53A of stage A is controlled so that the time interval T2 of the reception time becomes equal.

As a result, when the time interval T1 and the time interval T2 are equal (YES in step S804), in the next step S805, the synchronization processing unit 73 of the current differential relay 53A in the A stage is As described in Steps S101 to S107 of 10, the phase difference (φ) between the specific point voltage (Vs) based on the current data and voltage data of the own end and the specific point voltage (Vsf) based on the current data and voltage data of the other end Calculate. Here, the specific point is an intermediate point between the A and B ends. Then, the synchronization processing unit 73 stores the time corresponding to the phase difference ? as a specific time interval Ts in a memory (for example, the RAM 122 or ROM 123 in FIG. 2 ).

Thereafter, in step S806, the synchronization processing unit 73 controls the sampling timing of the current and voltage at the self-end side so that the time t corresponding to the phase difference φ between the specific point voltages Vs and Vsf becomes 0. . When the power transmission line 50 is normal, the sampling synchronization process based on this voltage phase difference is repeated.

Next, it is assumed that a failure of the power transmission line 50 is detected or the circuit breakers 68A, 68B, etc. between the A and B terminals are open (YES in step S807). When a power line failure or an open circuit breaker between both ends occurs (YES in step S807), the synchronization processing unit 73 cannot continue the timing synchronization processing based on the voltage phase difference, so the time interval between the transmission time and the reception time of the timing signal Switches to timing synchronization processing based on

Specifically, in step S808, the transmitter 131_1 of the current differential relay 53A of stage A transmits a timing signal together with current data and voltage data of its own stage to the current differential relay 53B of stage B. Similarly, the transmitter 131_1 of the current differential relay 53B of stage B transmits a timing signal together with current data and voltage data of its own stage to the current differential relay 53A of stage A.

In the next step S809, the receiver 131_2 of the current differential relay 53A of the A stage receives the timing signal together with the current data and the voltage data from the other end. Similarly, the receiver 131_2 of the current differential relay 53B of stage B receives a timing signal together with current data and voltage data from the other end. Similar to step S802, each of the current differential relays 53A, 53B calculates a time interval between the transmission time of the timing signal from its own end and the reception time of the timing signal from the opposite end. The current differential relays 53A and 53B transmit the calculated timing signal transmission/reception time intervals to each other.

In the next step S810, the synchronization processing unit 73 of the current differential relay 53A in the A stage is configured to determine the time interval T1 between the transmission time and the reception time of the timing signal at the own end side, the transmission time of the timing signal at the opposite end side, and Current and voltage in the A/D conversion unit 110 of the current differential relay 53A of stage A so that the time interval T2 of the reception time differs by twice the specific time interval Ts obtained in step S805 control the sampling time of

As described above, even when a power transmission line failure or an open circuit breaker between both ends occurs, sampling synchronization processing with higher precision than in the prior art can be realized. In addition, in the above description, it has been described that the current differential relay 53A of stage A is the slave side, and the current differential relay 53A of stage A adjusts the sampling timing of its own stage. Conversely, the current differential relay 53B of stage B may adjust the sampling timing of its own stage.

<Modification of Embodiment 1>

In the above, the intermediate point 57 on the power transmission line 50 was taken as a specific point, and the voltage at that specific point was calculated from each terminal voltage and terminal current. Any point on (50) can be set as the specific point (67). Hereinafter, it will be described with reference to the drawings. In addition, it is preferable to make the specific point 67 into an intermediate point from the viewpoint of calculation precision.

Fig. 15 is an equivalent circuit diagram of a normal circuit of a power transmission system to which sampling synchronization processing according to a modification of the first embodiment is applied. Since the equivalent circuit diagram of Fig. 15 is a modification of the equivalent circuit diagram of Fig. 7, parts common to those of Fig. 7 are denoted by the same reference numerals and explanations will not be repeated. In addition, let the position of the specific point 67 on the power transmission line 50 be x=m (0<=m<=1). In addition, in the following description, A stage is called a self-end, and B stage is called an opposite end.

Since the power transmission line 50 is simulated as a π-type circuit, the ground capacity is arranged at both ends of the power transmission line. Accordingly, each of the site capacity arranged at the own end and the site capacity arranged at the opposite end becomes 1/2 of the total capacity C of the power transmission line 50 regardless of the length from the own end to the specific point 67 . Therefore, the charging current (Ic) flowing through the terminal is

Ic=jω(C/2)*V1 … (16)

is displayed as The voltage Vf at the specific point 67 can be calculated using the value I1-Ic obtained by subtracting the charging current Ic from the self-end current I1 and the self-end voltage V1. The voltage Vf at the specific point 67 is,

Vf=V1-Z1*m*(I1-Ic) … (17)

is displayed as The second term on the right side of the above equation (17) represents the voltage drop by the power transmission line 50 from the self-end to the specific point 67.

Similarly, assuming that the opposite end has 1/2 of C of the entire line capacity, the charging current (Ics) flowing through the opposite end is,

Ics=jω(C/2)*Vs1 … (18)

is displayed as The voltage at the specific point 67 can be calculated using the value Is1-Ics obtained by subtracting the charging current Ics from the opposite-end current Is1 and the opposite-end voltage Vs1. Specifically, the midpoint voltage (Vsf) is,

Vsf=Vs1-Z1*(1-m)*(Is1-Ics) … (19)

is displayed as The second term on the right side of the above equation (19) represents the voltage drop by the power transmission line 50 from the opposite end to the specific point 67.

Therefore, at the time t corresponding to the phase difference φ between the voltage Vf at the specific point 67 expressed by the above equation (17) and the voltage Vsf at the specific point 67 expressed by the above equation (19) Based on this, it is possible to perform synchronous processing of the sampling timing.

Embodiment 2.

In Embodiment 1, the power transmission line is simulated as a π-type circuit, the charging current is calculated using the terminal voltage of the power transmission line when there is no system failure, and the charging current is compensated for by using the compensated terminal current and the terminal voltage. The voltage was calculated. Then, the phase difference (φ) between the midpoint voltage (Vf) based on the voltage and current of the A stage and the midpoint voltage (Vsf) based on the voltage and current of the B stage is calculated and corresponds to the calculated phase difference (φ) The sampling time was corrected based on the time (t).

In Embodiment 2, a power transmission line circuit is simulated as a T-type circuit. The T-type circuit is a model in which a capacitor corresponding to the earth capacitance C for generating a charging current is provided at the midpoint of the power transmission line, and the capacitor is sandwiched by 1/2 of the line impedance of the power transmission line. The point of the capacitor to which the capacitor is connected is not limited to the intermediate point, and any point between the A and B terminals may be used, but the intermediate point is preferable in terms of precision.

In the second embodiment, the voltage at the B-stage as a specific point is further calculated based on the current and the voltage at the A-stage, and the phase difference between the calculated B-stage voltage and the actual B-stage voltage is calculated. By simulating the transmission line as a T-type circuit, the voltage drop due to the load current flowing through the transmission line and the charging current due to the ground capacity can be taken into the calculation, so that sampling synchronization with higher precision than before can be realized.

[When the transmission line is simulated as a single T-type circuit]

Fig. 16 is an equivalent circuit diagram of a normal circuit of a power transmission system to which sampling synchronization processing according to the second embodiment is applied. Referring to FIG. 16 , the normal voltage of the A terminal is V1, and the normal current of the A terminal is I1. Similarly, the steady-state voltage of the B-stage is Vs1, and the steady-state current of the B-stage is Is1.

Let C be the total amount of land capacity in the entire power transmission line 50 . In the T-type circuit, a capacitor corresponding to the earth capacitance C is connected to the intermediate point 57 . Note that the point of the capacitor to which the capacitor is connected is not limited to the midpoint, and may be any point between the A and B ends, but the midpoint is preferable for the sake of precision.

In addition, if the normal impedance of the entire power transmission line 50 is Z1, the line impedance from the A terminal to the midpoint 57 of the power transmission line 50 is represented by Z1/2, and the line impedance from the B terminal to the midpoint of the transmission line 50 is Z1. Line impedance up to (57) is denoted by Z1/2. The T-type circuit 80 is constituted by the capacitor corresponding to the above-described earth capacitance C and the two line impedances Z1/2.

17 is a flowchart showing the procedure of sampling synchronization processing according to the second embodiment. Hereinafter, the procedure of the sampling synchronization process will be mainly described with reference to Figs. 9, 16, and 17. Figs. In the following description, stage A is referred to as a rose end, and stage B is referred to as an opposite end.

First, the A/D converter 110 of FIG. 9 generates current data I1 and voltage data V1 by sampling the current and voltage of its own end (step S201). The receiver 131_2 receives the current data Is1 and the voltage data Vs1 which are sampling values of the current and voltage of the opposite end (step S202). In addition, when only the phase difference of the voltages of both ends is calculated and the current data Is1 of the opposite end is not required, only the voltage data Vs1 may be received.

Next, the voltage calculating part 74 calculates the voltage Vt of the midpoint 57 (also called a capacitor point) using the self-end voltage V1 and the self-end current I1 (step S203). Specifically, the voltage (Vt) is,

Vt=V1-(Z1/2)*I1 … (20)

is displayed as The second term on the right side of the above equation (20) represents the voltage drop by the power transmission line 50 from the self-end to the midpoint 57.

Next, the voltage calculating part 74 calculates the charging current Ict using the voltage Vt of a capacitor|condenser point (step S204). Specifically, the charging current Ict is,

Ict=jωC*Vt … (21)

is displayed as

Next, the voltage calculating unit 74 uses the value I1-Ict obtained by subtracting the charging current Ict from the self-end current I1 and the voltage Vt of the capacitor point, and the opposite terminal voltage Vs1' ) is calculated (step S205). Specifically, the opposite terminal voltage (Vs1') is,

Vs1'=Vt-(Z1/2)*(I1-Ict) … (22)

is displayed as The second term on the right side of the above equation (22) represents the voltage drop by the power transmission line 50 from the midpoint 57 to the opposite end. That is, the synchronization processing unit 73 controls the sampling time of the current and voltage at the self-end so that the time t corresponding to the phase difference phi becomes zero. Also, the sampling synchronization method described with reference to Fig. 14 can be applied to the case of the present embodiment.

Next, the phase difference calculating part 75 calculates the phase difference phi between the actually detected opposite terminal voltage Vs1 and the calculated opposite terminal voltage Vs1' (step S206). The phase difference calculating unit 75 calculates a delay time (or a preceding time) corresponding to the above-described phase difference ? and outputs it to the synchronization processing unit 73 . The synchronization processing unit 73 corrects the sampling time only by the delay time or the preceding time (step S207).

As described above, by simulating the power transmission line as a T-type circuit, the charging current due to the ground capacity as well as the voltage drop due to the load current flowing through the transmission line can be taken into the calculation. can be realized In addition, by increasing the number of stages of the T-type circuit, it is possible to increase the accuracy of sampling synchronization.

[When the transmission line is simulated as a two-stage T-type circuit]

Fig. 18 is an equivalent circuit diagram of a normal circuit of a power transmission system when a power transmission line is simulated in a two-stage T-type circuit.

Referring to FIG. 18, the T-type circuit 81 of the first stage includes a capacitor having a ground capacity of C/2 provided at the first capacitor point 56, which is a point of x=1/4 of the power transmission line, and the capacitor point. It includes line impedance of the magnitude of Z1/4 connected to both sides, respectively. The T-type circuit 82 of the second stage is connected to a capacitor having a ground capacitance of C/2 provided at the second capacitor point 58 which is a point of x=3/4 of the power transmission line, and to both sides of the capacitor point, respectively. Includes line impedance of the magnitude of Z1/4. Let the voltage at the first capacitor point 56 be Vt, and the charging current at the first capacitor point 56 be Ict. Let the voltage at the second capacitor point 58 be Vt', and the charging current at the second capacitor point 58 be Ict'. Note that the line lengths of the two-stage T-type circuit do not have to be the same. When the line lengths of the two-stage T-type circuit are different, it is sufficient that the earth capacity proportional to the line length of each T-type circuit is located at the midpoint of each line.

Fig. 19 is a flowchart showing the sampling synchronization procedure of the power transmission system simulated by the equivalent circuit of Fig. 18; Hereinafter, the procedure of the sampling synchronization process will be mainly described with reference to FIGS. 9, 18 and 19 . In the following description, stage A is referred to as a rose end, and stage B is referred to as an opposite end.

The A/D converter 110 of FIG. 9 generates the current data I1 and the voltage data V1 by sampling the current and voltage of its own end (step S301). The receiver 131_2 receives the current data Is1 and the voltage data Vs1, which are sampling values of the current and voltage of the opposite end (step S302). In addition, when only the phase difference of the voltages of both ends is calculated and the current data Is1 of the opposite end is not required, only the voltage data Vs1 may be received.

Next, the voltage calculating part 74 calculates the voltage Vt of the 1st capacitor point (x=1/4) using the self-end voltage V1 and the self-end current I1 (step S303). Specifically, the voltage (Vt) is,

Vt=V1-(Z1/4)*I1 … (23)

is displayed as The second term on the right side of the above expression (23) represents the voltage drop by the power transmission line 50 from the self-end to the first condenser point 56 .

Next, the voltage calculating part 74 calculates the charging current Ict at the 1st capacitor|condenser point 56 using the voltage Vt of the above expression (23) (step S304). Specifically, the charging current Ict is,

Ict=jω(C/2)*Vt … (24)

is displayed as

Next, the voltage calculating unit 74 uses the value I1-Ict obtained by subtracting the charging current Ict from the self-end current I1 and the voltage Vt of the first capacitor point 56, The voltage Vt' of the second capacitor point 58 (x=3/4) is calculated (step S305). Specifically, the voltage (Vt') is,

Vt'=Vt-((Z1/4)+(Z1/4))*(I1-Ict)

=Vt-(Z1/2)*(I1-Ict) … (25)

is displayed as The second manuscript on the right side of the above formula (25) shows the voltage drop in the power transmission line 50 between the first capacitor point 56 and the second capacitor point 58 .

Next, the voltage calculating unit 74 calculates the charging current Ict' at the second capacitor point 58 by using the voltage Vt' of the equation (25) (step S306). Specifically, the charging current Ict' is,

Ict'=jω(C/2)*Vt' … (26)

is displayed as

Next, the voltage calculating unit 74 calculates a value (I1-Ict-Ict') obtained by subtracting the charging currents Ict and Ict' from the self-end current I1, and the voltage at the second capacitor point (Vt') is used to calculate the voltage Vs1' at the opposite end (step S307). Specifically, the voltage (Vs1') of the opposite end is,

Vs1'=Vt'-(Z1/4)*(I1-Ict-Ict') ... (27)

is displayed as The second term on the right side of the above expression (27) represents the voltage drop by the power transmission line 50 from the second capacitor point 58 to the opposite end.

Next, the phase difference calculating part 75 calculates the phase difference phi between the actually detected opposite terminal voltage Vs1 and the calculated opposite terminal voltage Vs1' (step S308). Further, the phase difference calculating unit 75 calculates a delay time (or a preceding time) corresponding to the above-described phase difference ? and outputs it to the synchronization processing unit 73 . The synchronization processing unit 73 corrects the sampling time by the delay time or the preceding time (step S309). That is, the synchronization processing unit 73 controls the sampling time of the current and voltage at the self-end so that the time t corresponding to the phase difference phi becomes zero. Also, the sampling synchronization method described with reference to Fig. 14 can be applied to the case of the present embodiment.

In this way, by increasing the number of stages of the T-type circuit, it is possible to approximate the distributed constant line simulating the actual power transmission line, so that the accuracy of sampling synchronization can be further improved. Further, in the second embodiment, since the charging current can be compensated based on the voltage difference between the ends of the power transmission line 50, it is possible to continuously correct the sampling synchronization in a state where there is no failure in the power transmission line. When a system failure occurs, sampling synchronization processing is performed using the result of the latest synchronization processing in a state in which there is no system failure (that is, by holding the predecessor).

[Modification of Embodiment 2]

In the above, the voltage calculating unit 71 of the current differential relay 53A uses the current data I1 and the voltage data V1 of the self-end of the power transmission line to calculate the voltage Vs1' of the opposite end, and the phase difference calculating unit ( 72) calculated the phase difference φ between the calculation result and the actual voltage value Vs1 at the opposite end. Conversely, the voltage calculating unit 71 of the current differential relay 53A uses the current data Is1 and the voltage data Vs1 of the opposite end of the transmission line to calculate the voltage V1' of its own end, and the phase difference calculating unit (72) may be made to calculate the phase difference (phi) between the calculation result and the actual voltage value (V1) of the self-end of a power transmission line. Even in this way, since the sampling timing of the self-end can be adjusted based on the time t corresponding to the phase difference ?, sampling synchronization can be performed more accurately than before.

Embodiment 3.

In the second embodiment, the voltage at the B stage is calculated using the current and voltage at the A stage, and the calculated voltage at the B stage is compared with the actually detected voltage at the B stage. In the third embodiment, as described with reference to FIGS. 7 and 10 of the first embodiment, the midpoint voltage Vf is calculated using the current and voltage of the A stage, and the intermediate point voltage Vf is calculated using the current and the voltage of the B stage. Calculate the point voltage (Vsf). Then, sampling synchronization processing is performed based on the calculated phase difference between the calculated midpoint voltages Vf and Vsf.

Further, it is not limited to the midpoint, and may be a specific point arbitrarily determined between the A and B terminals. In this case, the midpoint voltage Vf is called the first specific point voltage Vf, and the midpoint voltage Vsf is is referred to as a second specific point voltage (Vsf). In addition, the power transmission line 50 is simulated as a two-stage T-type circuit similarly to FIG. 18 of Embodiment 2. FIG. Thereby, the precision can be raised compared with the case of Embodiment 1.

Fig. 20 is an equivalent circuit diagram of a normal circuit of a power transmission system to which the sampling synchronization processing according to the third embodiment is applied. The equivalent circuit diagram of FIG. 20 corresponds to the equivalent circuit diagram of FIG. 18 , and the power transmission line 50 is simulated by two-stage T-type circuits 81 and 82 . Let the voltage at the first capacitor point 56 be Vt, and the charging current at the first capacitor point 56 be Ict. Let the voltage at the second capacitor point 58 be Vts, and the charging current at the second capacitor point 58 be Icts. In addition, the voltage at the midpoint 57 based on the current I1 and voltage V1 in the A stage is Vf, and the midpoint 57 based on the current Is1 and the voltage Vs1 in the B stage. Let the voltage at Vsf be Vsf.

Fig. 21 is a flowchart showing the sampling synchronization procedure of the power transmission system simulated by the equivalent circuit of Fig. 20; Hereinafter, the procedure of the sampling synchronization process will be mainly described with reference to Figs. 9, 20 and 21 . In the following description, stage A is referred to as a rose end, and stage B is referred to as an opposite end.

First, the A/D converter 110 of FIG. 9 generates current data I1 and voltage data V1 by sampling the current and voltage of its own end (step S401).

Next, the voltage calculating part 74 calculates the voltage Vt of the 1st capacitor point (x=1/4) using the self-end voltage V1 and the self-end current I1 (step S402). Specifically, the voltage (Vt) is,

Vt=V1-(Z1/4)*I1 … (28)

is displayed as The second term on the right side of the equation (28) indicates the voltage drop by the power transmission line 50 from the A terminal to the first capacitor point 56.

Next, the voltage calculating part 74 calculates the charging current Ict at the 1st capacitor|condenser point 56 using the voltage Vt of the above expression (28) (step S403). Specifically, the charging current Ict is,

Ict=jω(C/2)*Vt … (29)

is displayed as

Next, the voltage calculating unit 74 uses the value I1-Ict obtained by subtracting the charging current Ict from the self-end current I1 and the voltage Vt of the first capacitor point 56, The midpoint voltage Vf is calculated (step S404). Specifically, the midpoint voltage (Vf) is,

Vf=Vt-(Z1/4)*(I1-Ict) … (30)

is displayed as The second term on the right side of the above equation (30) represents the voltage drop by the power transmission line 50 from the first capacitor point 56 to the midpoint 57.

Next, the receiver 131_2 receives the sampling values of the current and voltage of the opposite end (that is, the current data Is1 and the voltage data Vs1) (step S405). The received current data Is1 and voltage data Vs1 are received by the reception data processing unit 72 . Note that step S405 may be executed before step S402. Note that steps S402 to S404 may be executed in parallel with steps S406 to S408.

Next, the voltage calculating part 74 calculates the voltage Vts of the 2nd capacitor point (x=3/4) using the opposite-end voltage Vs1 and the opposite-end current Is1 (step S406). ). Specifically, the voltage (Vts) is,

Vts= Vs1-(Z1/4)*Is1 … (31)

is displayed as The second term on the right side of the equation (31) represents the voltage drop by the power transmission line 50 from the B stage to the second capacitor point 58.

Next, the voltage calculating unit 74 calculates the charging current Icts at the second capacitor point 58 using the voltage Vts of the above equation (31) (step S407). Specifically, the charging current (Icts) is,

Icts=jω(C/2)*Vts … (32)

is displayed as

Then, the voltage calculating unit 74 uses the value Is1-Icts obtained by subtracting the charging current Icts from the opposite end current Is1 and the voltage Vts at the second capacitor point 58 . , the midpoint voltage Vsf is calculated (step S408). Specifically, the midpoint voltage (Vsf) is,

Vsf=Vts-(Z1/4)*(Is1-Icts) … (33)

is displayed as The second term on the right side of the equation (33) represents the voltage drop by the power transmission line 50 from the second capacitor point 58 to the midpoint 57.

Next, the phase difference calculating part 75 calculates the phase difference phi of the midpoint voltages Vs and Vsf (step S409). Further, the phase difference calculating unit 75 calculates a delay time (or a preceding time) corresponding to the calculated phase difference ? and outputs it to the synchronization processing unit 73 . The synchronization processing unit 73 corrects the sampling time only by the delay time or the preceding time (step S410). That is, the synchronization processing unit 73 controls the sampling time of the current and voltage at the self-end so that the time t corresponding to the phase difference phi becomes zero. In addition, the sampling synchronization method described with reference to FIG. 14 can be applied to the case of the present embodiment.

In the first embodiment, when the load current increases, there is a possibility that the error becomes non-negligible. there is. In addition, if the line from each terminal to the midpoint 57 is constituted by a two-stage T-type circuit, the equivalent circuit becomes closer to a distributed constant, and thus the accuracy of sampling synchronization can be further improved.

22 : is an equivalent circuit diagram by the normal circuit of a power transmission system in the case where the T-type circuit of two stages is simulated from each terminal to an intermediate point.

Referring to FIG. 22, in the transmission line from the A terminal to the midpoint 57, the T-type circuit 83 of the first stage is provided at the first condenser point 91, which is the point of x = 1/8 of the transmission line. It includes a capacitor having a ground capacitance of C/4, and a line impedance of Z1/8 connected to both sides of the capacitor point, respectively. The T-type circuit 84 of the second stage is connected to a capacitor having a ground capacitance of C/4 provided at the second capacitor point 93 which is a point of x=3/8 of the power transmission line, and to both sides of the capacitor point, respectively. Includes line impedance of the magnitude of Z1/8. Let the voltage at the first capacitor point 91 be Vp, and the charging current at the first capacitor point 91 be Icp. Let the voltage at the second capacitor point 93 be Vp', and the charging current at the second capacitor point 93 be Icp'.

Similarly, in the transmission line from the B stage to the midpoint 57, the T-type circuit 86 of the first stage has a ground capacitance provided at the third condenser point 96, which is a point of x = 7/8 of the transmission line, is C It includes a capacitor of /4, and a line impedance of a magnitude of Z1/8 connected to both sides of the capacitor point, respectively. The T-type circuit 85 of the second stage is connected to a capacitor having a ground capacity of C/4 provided at the fourth capacitor point 94 which is a point of x=5/8 of the power transmission line, and to both sides of the capacitor point, respectively. Includes line impedance of the magnitude of Z1/8. Let the voltage at the third capacitor point 96 be Vps, and the charging current at the third capacitor point 96 be Icps. Let the voltage at the fourth capacitor point 94 be Vps', and the charging current at the fourth capacitor point 94 be Icps'.

Fig. 23 is a flowchart showing the sampling synchronization procedure of the power transmission system simulated by the equivalent circuit of Fig. 22; Hereinafter, the procedure of the sampling synchronization process will be mainly described with reference to Figs. 9, 22, and 23 . In the following description, stage A is referred to as a rose end, and stage B is referred to as an opposite end.

First, the A/D converter 110 of FIG. 9 generates current data I1 and voltage data V1 by sampling the current and voltage of its own end (step S501).

Next, the voltage calculating unit 74 calculates the voltage Vp of the first capacitor point 91 (x = 1/8) using the self-end voltage V1 and the self-end current I1 (step S502). Specifically, the voltage (Vp) is,

Vp=V1-(Z1/8)*I1 … (34)

is displayed as The second term on the right side of the above equation (34) indicates the voltage drop by the power transmission line 50 from the A terminal to the first capacitor point 91.

Next, the voltage calculating part 74 calculates the charging current Icp at the 1st capacitor|condenser point 91 using the voltage Vp of the above formula (34) (step S503). Specifically, the charging current (Icp) is,

Icp=jω(C/4)*Vp … (35)

is displayed as

Next, the voltage calculating unit 74 uses the value I1-Icp obtained by subtracting the charging current Icp from the self-end current I1 and the voltage Vp at the first capacitor point 91 , , the voltage Vp' of the second capacitor point 93 (x=3/8) is calculated (step S504). Specifically, the voltage (Vp') is,

Vp'=Vp-(Z1/4)*(I1-Icp) ... (36)

is displayed as The second term on the right side of the above equation (36) represents the voltage drop by the power transmission line 50 from the first capacitor point 91 to the second capacitor point 93.

Next, the voltage calculating unit 74 calculates the charging current Icp' at the second capacitor point 93 by using the voltage Vp' of the equation (36) (step S505). Specifically, the charging current (Icp') is,

Icp'=jω(C/4)*Vp' … (37)

is displayed as

Next, the voltage calculating unit 74 calculates a value (I1-Icp-Icp') obtained by subtracting the charging currents (Icp and Icp') from the self-end current I1, and the voltage at the second capacitor point (Vp') is used to calculate the midpoint voltage Vf (step S506). Specifically, the midpoint voltage (Vf) is,

Vf=Vp'-(Z1/8)*(I1-Icp-Icp') … (38)

is displayed as The second term on the right side of the equation (38) indicates the voltage drop by the power transmission line 50 from the second capacitor point 93 to the midpoint 57.

Next, the receiver 131_2 receives the sampling values of the current and voltage of the opposite end (that is, the current data Is1 and the voltage data Vs1) (step S507). The received current data Is1 and voltage data Vs1 are received by the reception data processing unit 72 . Note that step S507 may be executed before step S502. Note that steps S502 to S506 may be executed in parallel with steps S508 to S512.

Next, the voltage calculating unit 74 calculates the voltage Vps at the third capacitor point (x=7/8) using the opposite-end voltage Vs1 and the opposite-end current Is1 (step S508). ). Specifically, the voltage (Vps) is,

Vps=Vs1-(Z1/8)*Is1 … (39)

is displayed as The second term on the right side of the above equation (39) represents the voltage drop by the power transmission line 50 from the B stage to the third capacitor point 96.

Next, the voltage calculating unit 74 calculates the charging current Icps at the third capacitor point 96 using the voltage Vps of the above expression (39) (step S509). Specifically, the charging current (Icps) is,

Icps=jω(C/4)*Vps … (40)

is displayed as

Then, the voltage calculating unit 74 uses the value Is1-Icps obtained by subtracting the charging current Icps from the opposite end current Is1 and the voltage Vps at the third capacitor point 96 . Thus, the voltage Vps' at the fourth capacitor point 94 (x=5/8) is calculated (step S510). Specifically, the voltage (Vps') is,

Vps'=Vps-(Z1/4)*(Is1-Icps) … (41)

is displayed as The second term on the right side of the above expression (41) represents the voltage drop by the power transmission line 50 from the third capacitor point 96 to the fourth capacitor point 94.

Next, the voltage calculating unit 74 calculates the charging current Icps' at the fourth capacitor point 94 using the voltage Vps' of the equation (41) (step S511). Specifically, the charging current (Icps') is,

Icps'=jω(C/4)*Vps' … (42)

is displayed as

Next, the voltage calculating unit 74 calculates a value (Is1-Icps-Icps') obtained by subtracting the charging currents Icps and Icps' from the opposite end current Is1, and the voltage at the fourth capacitor point 94. Using (Vps'), the midpoint voltage Vsf is calculated (step S512). Specifically, the midpoint voltage (Vsf) is,

Vsf=Vps'-(Z1/8)*(Is1-Icps-Icps') … (43)

is displayed as The second term on the right side of the equation (43) represents the voltage drop by the power transmission line 50 from the fourth capacitor point 94 to the midpoint 57.

Next, the phase difference calculating part 75 calculates the phase difference phi of the midpoint voltages Vs and Vsf (step S513). Further, the phase difference calculating unit 75 calculates a delay time (or a preceding time) corresponding to the calculated phase difference ? and outputs it to the synchronization processing unit 73 . The synchronization processing unit 73 corrects the sampling time by the delay time or the preceding time (step S514). That is, the synchronization processing unit 73 controls the sampling time of the current and voltage at the self-end so that the time t corresponding to the phase difference phi becomes zero. Also, the sampling synchronization method described with reference to Fig. 14 can be applied to the case of the present embodiment.

As described above, by increasing the number of stages of the T-type circuit, the equivalent circuit of the power transmission line 50 becomes closer by the distributed constant circuit, so that the accuracy of sampling synchronization can be further improved. In addition, it is possible to continuously correct the sampling synchronization under the condition that there is no system failure. In addition, even if the line from each terminal to the midpoint is simulated by a T-type circuit of three or more stages, the sampling synchronization process can be performed in the same manner as above.

Embodiment 4.

In Embodiments 1 to 3, the case where the power transmission line has two terminals has been described, but in the fourth embodiment, the case where the power transmission line has three or more terminals will be described.

[In case of 3-terminal transmission line]

Fig. 24 is a schematic diagram of a three-terminal power transmission line having a rear power supply at each terminal. In the power transmission line of FIG. 24 , terminal A is connected through a junction 200 and a power transmission line 201 , terminal B is connected through a junction 200 and a power transmission line 202 , and terminal C is connected between a junction 200 and a power transmission line It is connected through 203. Rear power supplies 52A, 52B, and 52C are connected to terminals A, B, and C of the transmission line, respectively.

A current transformer CT1 is provided in stage A, and a voltage transformer VT1 is provided in the bus 51A of stage A. The current transformer CT2 is provided in the B stage, and the voltage transformer VT2 is provided in the B stage bus 51B. A current transformer CT3 is provided in the C stage, and a voltage transformer VT3 is provided in the bus 51C of the C stage.

In addition, current differential relays 53A, 53B, and 53C are provided in the A stages, B stages, and C stages, respectively. Each current differential relay 53 is connected to a voltage transformer VT and a current transformer CT of its own stage. In addition, these current differential relays 53A, 53B, 53C are interconnected via communication paths 54, 54B, 54C, and the detected current data and voltage data of their own ends are exchanged with each other.

Fig. 25 is an equivalent circuit diagram of the normal circuit of the power transmission system of Fig. 24; Each of the power transmission lines 201, 202, and 203 is simulated by T-type circuits 204, 205, and 206, respectively.

In the T-type circuit 204 , a capacitor having a size of the ground capacitance CA of the power transmission line 201 is provided at an intermediate point (also referred to as a first capacitor point) 211 of the power transmission line 201 . On both sides of the midpoint 211 , impedances that are half of the normal impedance ZA1 of the power transmission line 201 are respectively connected.

Similarly, in the T-type circuit 205 , a capacitor having the size of the earth capacitance CB of the power transmission line 202 is provided at the midpoint (also referred to as a second capacitor point) 212 of the power transmission line 202 . On both sides of the midpoint 212 , impedances that are half of the normal impedance ZB1 of the power transmission line 202 are respectively connected.

Similarly, in the T-type circuit 206 , a capacitor having a size of the ground capacitance CC of the power transmission line 203 is provided at the midpoint (also referred to as a third capacitor point) 213 of the power transmission line 203 . On both sides of the midpoint 213 , impedances that are half of the normal impedance ZC1 of the power transmission line 203 are respectively connected.

In a specific sampling synchronization process, the sample timing of one of the three terminals is synchronized with the sample timing of the other two terminals. Hereinafter, a case in which the sample timings of the A and C terminals are synchronized with the sample timing of the B terminal will be described.

26 is a flowchart showing a procedure for synchronizing the sample timing of the A terminal to the sample timing of the B terminal. The specific procedure is the same as in the case of FIG. 21 of the third embodiment. In FIG. 21, the midpoint voltages Vf and Vsf are respectively calculated based on the respective currents and voltages of the A and B stages, but in the case of FIG. 26, instead of the midpoint 57, the junction 200 The voltages (Vf, Vsf) at are calculated.

24, 25, and 26, first, the A / D conversion unit 110 of the current differential relay 53A, by sampling the current and voltage of the self-end (stage A) current data (I1) and Voltage data V1 is generated (step S401A).

Next, the voltage calculating unit 74 of the current differential relay 53A calculates the voltage VA of the first capacitor point 211 using the self-end voltage V1 and the self-end current I1 (step S402A).

Next, the voltage calculating unit 74 of the current differential relay 53A calculates the charging current IAc using the voltage VA of the first capacitor point 211 (step S403A).

Next, the voltage calculating unit 74 of the current differential relay 53A calculates a value (I1-IAc) obtained by subtracting the charging current (IAc) from the self-end current (I1) and the voltage at the first capacitor point (211) ( VA) to calculate the junction voltage Vf (step S404A).

Next, the receiver 131_2 of the current differential relay 53A transmits the sampling values of the current and voltage of the opposite end (stage B) through the communication path 54 (that is, the current data Is1 and the voltage data Vs1) ) is received (step S405A). The received current data Is1 and voltage data Vs1 are received by the reception data processing unit 72 . Note that step S405A may be executed before step S402A. Note that steps S402A to S404A may be executed in parallel with steps S406A to S408A.

Next, the voltage calculating part 74 of the current differential relay 53A calculates the voltage VB of the second capacitor point 212 using the opposite terminal voltage Vs1 and the opposite terminal current Is1. (Step S406A).

Next, the voltage calculating unit 74 of the current differential relay 53A calculates the charging current IBc using the voltage VB of the second capacitor point 212 (step S407A).

Next, the voltage calculating unit 74 of the current differential relay 53A calculates a value Is1-IBc obtained by subtracting the charging current IBc from the opposite end current Is1, and the voltage at the second capacitor point 212 . Using (VB), the junction voltage Vsf is calculated (step S408A).

Next, the phase difference calculating part 75 of the current differential relay 53A calculates the phase difference phi of the junction voltages Vs and Vsf (step S409A). Further, the phase difference calculating unit 75 of the current differential relay 53A obtains a delay time (or a preceding time) corresponding to the phase difference φ, and outputs it to the synchronization processing unit 73 . The synchronization processing unit 73 corrects the sampling time only by the delay time or the preceding time (step S410A). That is, the synchronization processing unit 73 controls the sampling time of the current and voltage at the self-end so that the time t corresponding to the phase difference phi becomes zero. Thereby, the sample timing of the A terminal can be synchronized with the sample timing of the B terminal. Also, the sampling synchronization method described with reference to FIG. 14 can be applied to the above case.

27 is a flowchart showing a procedure for synchronizing the sample timing of the C terminal with the sample timing of the B terminal. The specific procedure is the same as in the case of FIG. 21 of the third embodiment. However, in the case of FIG. 27 , the voltages Vrf and Vsf at the branch point 200 are calculated instead of the intermediate point 57 .

24, 25, and 27, first, the A/D conversion unit 110 of the current differential relay 53C, by sampling the current and voltage of the self-end (stage C), the current data (Ir1) and Voltage data Vr1 is generated (step S401C).

Next, the voltage calculating unit 74 of the current differential relay 53C uses the self-end voltage Vr1 and the self-end current Ir1 to calculate the voltage VC at the third capacitor point 213 (step S402C).

Next, the voltage calculating unit 74 of the current differential relay 53C calculates the charging current ICc using the voltage VC of the third capacitor point 213 (step S403C).

Next, the voltage calculating unit 74 of the current differential relay 53C calculates a value (Ir1-ICc) obtained by subtracting the charging current ICc from the self-end current Ir1, and the voltage at the third capacitor point 213 ( VC) to calculate the junction voltage Vrf (step S404C).

Next, the receiver 131_2 of the current differential relay 53C transmits, via the communication path 54C, the sampling values of the current and voltage of the opposite end (stage B) (that is, the current data Is1 and the voltage data Vs1 ). )) is received (step S405C). The received current data Is1 and voltage data Vs1 are received by the reception data processing unit 72 . Note that step S405C may be executed before step S402C. Note that steps S402C to S404C may be executed in parallel with steps S406C to S408C.

Next, the voltage calculating unit 74 of the current differential relay 53C calculates the voltage VB of the second capacitor point 212 using the opposite terminal voltage Vs1 and the opposite terminal current Is1. (Step S406C).

Next, the voltage calculating unit 74 of the current differential relay 53C calculates the charging current IBc using the voltage VB of the second capacitor point 212 (step S407C).

Next, the voltage calculating unit 74 of the current differential relay 53C calculates a value Is1-IBc obtained by subtracting the charging current IBc from the opposite end current Is1, and the voltage at the second capacitor point 212 . Using (VB), the junction voltage Vsf is calculated (step S408C).

Next, the phase difference calculating part 75 of the current differential relay 53C calculates the phase difference phi of the branch voltages Vrf and Vsf (step S409C). Further, the phase difference calculating unit 75 of the current differential relay 53C obtains a delay time (or a preceding time) corresponding to the phase difference φ, and outputs it to the synchronization processing unit 73 . The synchronization processing unit 73 corrects the sampling time by the delay time or the preceding time (step S410C). That is, the synchronization processing unit 73 controls the sampling time of the current and the voltage at the self-end so that the time t corresponding to the phase difference phi becomes zero. Thereby, the sample timing of the C terminal can be synchronized with the sample timing of the B terminal. Also, the sampling synchronization method described with reference to FIG. 14 can be applied to the above case.

In addition, a three-terminal power transmission line can also be simulated using a ?-type circuit. In this case, similarly to the case of two terminals, the point from each terminal to the branching point is simulated as an L-type circuit which is a part of the ?-type circuit.

[In the case of a 4-terminal transmission line]

Fig. 28 is a schematic diagram of a four-terminal power transmission line having a rear power supply at each terminal. In the power transmission line of FIG. 28 , terminal A is connected to a junction g and a power transmission line 221 , and terminal D is connected to a junction g and a transmission line 224 . Terminal B is connected to the branch point f and the transmission line 222 , and terminal C is connected to the branch point f and the transmission line 223 . The branch point (g) and the branch point (f) are connected through the power transmission line (220). Rear power supplies 52A, 52B, 52C, and 52D are connected to terminals A, B, C, and D of the transmission line, respectively.

A current transformer CT1 is provided in stage A, and a voltage transformer VT1 is provided in the bus 51A of stage A. The current transformer CT2 is provided in the B stage, and the voltage transformer VT2 is provided in the B stage bus 51B. A current transformer CT3 is provided in the C stage, and a voltage transformer VT3 is provided in the bus 51C of the C stage. A current transformer CT4 is provided in stage D, and a voltage transformer VT4 is provided in the bus 51D of stage D.

In addition, current differential relays 53A, 53B, 53C, and 53D are provided in stages A, B, C, and D, respectively. Each current differential relay 53 is connected to a voltage transformer VT and a current transformer CT of its own stage. Moreover, these current differential relays 53A, 53B, 53C are interconnected via a communication path (not shown), and the detected current data and voltage data of their own end are mutually exchanged.

Hereinafter, the procedure in the case of synchronizing the sample timings of stages A, C, and D with the timing of sampling of stage B in the above configuration will be described.

29 is a flowchart showing an example of a procedure of sampling synchronization processing in the power transmission system of FIG. 28 . In the procedure of FIG. 29, the sampling timing of the other terminal is synchronized with the sampling timing of stage B in FIG.

First, the D-stage current differential relay 53D calculates the voltage Vg at the junction g based on the A-stage voltage V1 and the A-stage current I1 (step S601). Further, the current differential relay 53D calculates the voltage Vqg at the branch point g based on the D-stage voltage Vq1 and the D-stage current Iq1 (step S602). These specific calculation methods are the same as those described in Embodiments 1 and 3.

Next, the current differential relay 53D calculates the phase difference ?1 between the voltage Vg and the voltage Vqg at the branch point g (step S603). The current differential relay 53D corrects the sampling time of the D stage by the delay time (or the preceding time) corresponding to the phase difference φ1 (that is, the sampling time of the D stage is synchronized with the sampling time of the A stage) ( step S604).

Next, the current differential relay 53A generates a combined current (Ig+Iqg) of the current Ig flowing from the A terminal to the branching point g and the current Iqg flowing from the D terminal into the branching point g. calculation (step S605).

Next, the current differential relay 53A calculates the voltage Vgf at the branch point f based on the voltage Vg at the branch point g and the combined current Ig+Iqg (step S606). Further, the current differential relay 53A calculates the voltage Vsf at the branch point f based on the B-stage voltage Vs1 and the B-stage current Is1 (step S607).

Next, the current differential relay 53A calculates the phase difference ?2 between the voltage Vgf and the voltage Vsf at the branch point f (step S608).

Next, the current differential relay 53A corrects the sampling time of stage A by the delay time (or the preceding time) corresponding to the phase difference φ2 (that is, the sampling time of stage A is synchronized with the sampling time of stage B) do). Further, the D-stage current differential relay 53D corrects the D-stage sampling time by the delay time (or the preceding time) corresponding to the phase difference φ2 (that is, the D-stage sampling time is the B-stage sampling time). ) (above, step S609). Therefore, the final sampling time of stage D is corrected by the time corresponding to the phase difference (φ1+φ2).

Next, the C-stage current differential relay 53C calculates the voltage Vrf at the junction f based on the C-stage voltage Vr1 and the C-stage current Ir1 (step S610). Further, the C-stage current differential relay 53C calculates the voltage Vsf at the branch point f based on the B-stage voltage Vs1 and the B-stage current Is1 (step S611).

Next, the current differential relay 53C calculates the phase difference ?3 between the voltage Vsf and the voltage Vrf at the branch point f (step S612). Then, the current differential relay 53C corrects the sampling time of stage C by the delay time (or the preceding time) corresponding to the calculated phase difference φ3 (that is, the sampling time of stage C is set to the sampling time of stage B) synchronize) (step S613). As described above, the sampling synchronization process is completed.

In this way, the terminal (B stage) where the current differential relay 53B of the master to be synchronized is installed and the current differential relay 53C of the C stage connected through one branch point f, each terminal (B stage, C stage) The voltage at the branch point f is calculated based on the current and voltage data of step), respectively. Then, the current differential relay 53C may correct the sample timing based on the calculated phase difference of each branch voltage.

On the other hand, the current differential relays 53A and 53D of terminals A and D connected through two or more branch points f and g to the terminal (stage B) where the current differential relay 53B of the master to be synchronized is installed, First, it is necessary to calculate the combined current at a branch point (f) directly connected to stage B and another branch point (g). For this reason, a step of synchronizing the sampling timing of the other with the sampling timing of one of these current differential relays 53A, 53D is required.

It should be considered that embodiment disclosed this time is an illustration and is not restrictive in every point. The scope of the present invention is indicated by the claims rather than the above description, and it is intended that all modifications within the meaning and scope equivalent to the claims are included.

50, 201 to 203, 220 to 223: transmission line 52A to 52D: rear power
53, 53A∼53D: Current differential relay 54, 54B, 54C: Communication path
56, 91, 211: first capacitor point 57: midpoint
58, 93, 212: second condenser point 96, 213: third condenser point
94: fourth capacitor point 67: specific point
76: relay calculation unit 74: voltage calculation unit
75: phase difference calculating unit 73: synchronization processing unit
80 to 86, 204 to 206: T-type circuit 100: input conversion unit
110: A/D conversion unit 120: arithmetic processing unit
130: I/O unit 131: transceiver
132: digital input circuit 133: digital output circuit
200, f, g: Junction C, CA, CB: Site capacity
CT, CT1 to CT4: Current transformer VT, VT1 to VT4: Voltage transformer
Ts: specific time interval

Claims (16)

A current differential relay provided at the first terminal (stage A) of the transmission line,
an analog/digital converter for generating current data and voltage data by sampling the current and voltage of the first terminal of the transmission line;
a receiver for receiving current data and voltage data of the second terminal from a second current differential relay provided at a second terminal (stage B) of the power transmission line;
Based on the current data and voltage data of the first terminal, a voltage at a specific point between the first terminal and the second terminal of the power transmission line is calculated as a first specific point voltage, and the current data of the second terminal and a voltage calculating unit that calculates the voltage at the specific point as a second specific point voltage based on the voltage data;
a phase difference calculating unit for calculating a phase difference between the first specific point voltage and the second specific point voltage;
a synchronization processing unit for adjusting sampling times of the current and voltage of the first terminal based on the time corresponding to the phase difference;
The voltage calculating unit is configured to set each of a first line connecting the first terminal and the specific point and a second line connecting the second terminal and the specific point to a single π-type circuit for the entire power transmission line. By simulating as an L-type circuit formed from the first terminal or the second terminal that is part of the ?-type circuit of A current differential relay for calculating the first specific point voltage and the second specific point voltage. According to claim 1,
Each of the first line and the second line is an L-type circuit formed from the first terminal or the second terminal that is a part of the π-type circuit when the entire power transmission line is a single π-type circuit to the specific point. is simulated as
The voltage calculating unit calculates a charging current of the first line based on the voltage of the first terminal, and subtracts the charging current of the first line from the current of the first terminal, and the first line calculating the voltage drop of , and calculating the first specific point voltage by subtracting the voltage drop of the first line from the voltage of the first terminal,
The voltage calculating unit calculates a charging current of the second line based on the voltage of the second terminal, and subtracts the charging current of the second line from the current of the second terminal, and the second line and calculating the voltage drop of the second terminal by subtracting the voltage drop of the second line from the voltage of the second terminal to calculate the second specific point voltage. According to claim 1,
the first line is simulated as a single first T-circuit, the second line is simulated as a single second T-circuit;
The voltage calculating unit is configured to calculate the voltage at the capacitor point of the first T-type circuit by subtracting a voltage drop from the first terminal to the capacitor point of the first T-type circuit from the voltage of the first terminal. A current obtained by calculating, calculating the charging current of the first line based on the voltage at the capacitor point of the first T-type circuit, and subtracting the charging current of the first line from the current of the first terminal and calculating the first specific point voltage based on the voltage at the capacitor point of the first T-type circuit,
The voltage calculating unit is configured to calculate the voltage at the capacitor point of the second T-type circuit by subtracting a voltage drop from the second terminal to the capacitor point of the second T-type circuit from the voltage of the second terminal. The current obtained by calculating the charging current of the second line based on the voltage at the capacitor point of the second T-type circuit and subtracting the charging current of the second line from the current of the second terminal and calculating the second specific point voltage based on the voltage at the capacitor point of the second T-type circuit. A current differential relay provided at a first terminal of a power transmission line, comprising:
an analog/digital converter for generating current data and voltage data by sampling the current and voltage of the first terminal of the transmission line;
a receiver for receiving current data and voltage data of the second terminal from a second current differential relay provided at the second terminal of the power transmission line;
By simulating a line connecting the first terminal and the second terminal as a single T-type circuit or a plurality of T-type circuits connected in series, the voltage of the second terminal from the current data and voltage data of the first terminal a voltage calculator to calculate
a phase difference calculating unit for calculating a phase difference between the voltage of the second terminal calculated by the voltage calculating unit and the actual voltage of the second terminal;
and a synchronization processing unit for adjusting sampling times of the current and voltage of the first terminal based on the time corresponding to the phase difference. 5. The method of claim 4,
The line connecting the first terminal and the second terminal is simulated as a single T-type circuit,
The voltage calculating unit calculates a voltage at the capacitor point of the T-type circuit by subtracting a voltage drop from the first terminal to the capacitor point of the T-type circuit from the voltage of the first terminal, Based on the current obtained by calculating the charging current of the line based on the voltage at the condenser point of the circuit and subtracting the charging current of the line from the current at the first terminal and the voltage at the condenser point of the T-type circuit to calculate the voltage of the second terminal. A current differential relay provided at a first terminal of a power transmission line, comprising:
an analog/digital converter for generating current data and voltage data by sampling the current and voltage of the first terminal of the transmission line;
a receiver for receiving current data and voltage data of the second terminal from a second current differential relay provided at the second terminal of the power transmission line;
The voltage of the first terminal from the current data and voltage data of the second terminal by simulating the line connecting the first terminal and the second terminal as a single T-type circuit or a plurality of T-type circuits connected in series a voltage calculator to calculate
a phase difference calculating unit for calculating a phase difference between the voltage of the first terminal calculated by the voltage calculating unit and the actual voltage of the first terminal;
and a synchronization processing unit for adjusting sampling times of the current and voltage of the first terminal based on the time corresponding to the phase difference. 7. The method according to any one of claims 1 to 6,
the current differential relay further comprises a transmitter for transmitting a first timing signal together with the current data and voltage data of the first terminal to the second current differential relay;
The receiver receives a second timing signal from the second current differential relay together with the current data and voltage data of the second terminal,
The synchronization processing unit,
a first time interval from when the transmitter transmits the first timing signal until the receiver receives the second timing signal, and the second current differential relay transmits the second timing signal. a first step of controlling the sampling times of the current and voltage of the first terminal so that a second time interval from transmission to reception of the first timing signal becomes equal;
a second step of storing, as a third time interval, a time corresponding to the phase difference calculated by the phase difference calculating unit when the first time interval and the second time interval are equal;
and perform a third step of controlling sampling times of the current and voltage of the first terminal such that the first time interval and the second time interval differ by twice the third time interval. Current differential relay featuring. 8. The method of claim 7,
The synchronization processing unit is configured to use a time corresponding to the phase difference calculated by the phase difference calculating unit when the first time interval and the second time interval differ by twice the third time interval, and a fourth step of correcting the time interval of
In the third step, the third time interval corrected by the fourth step is used. 9. The method of claim 8,
The synchronization processing unit is configured to continuously correct the third time interval by repeatedly executing the fourth step when the power transmission line is normal,
The synchronization processing unit is configured to execute the third step using the third time interval corrected immediately before occurrence of the failure of the power line without executing the fourth step when the power line fails Current differential relay featuring. 8. The method of claim 7,
The synchronization processing unit, after executing the first step and the second step when the power transmission line is normal, such that the time corresponding to the phase difference calculated by the phase difference calculating unit becomes 0, the current of the first terminal and configured to execute a fifth step of controlling the sampling time of the voltage;
The synchronous processing unit is configured to execute the third step instead of the fifth step when the power transmission line fails. generating current data and voltage data by sampling the current and voltage of the first terminal (stage A) of the power transmission line;
generating current data and voltage data by sampling the current and voltage of the second terminal (stage B) of the power transmission line;
calculating a voltage at a specific point between the first terminal and the second terminal of the power transmission line as a first specific point voltage from the current data and voltage data of the first terminal;
calculating the voltage at the specific point as a second specific point voltage from the current data and voltage data of the second terminal;
In the step of calculating the first specific point voltage and the second specific point voltage, each of a first line connecting the first terminal and the specific point and a second line connecting the second terminal and the specific point is an L-type circuit formed from the first terminal or the second terminal that is a part of the π-type circuit when the entire power transmission line is a single π-type circuit to the specific point, or as a single T-type circuit, or Simulated as a plurality of T-type circuits connected in series,
In addition, calculating a phase difference between the first specific point voltage and the second specific point voltage as a first phase difference;
and adjusting the sampling times of the current and voltage of the first terminal based on the time corresponding to the first phase difference. 12. The method of claim 11,
The power transmission line also includes a third terminal (C end) connected to the specific point through a third line,
The sampling synchronization method further comprises:
generating current data and voltage data by sampling the current and voltage of the third terminal;
By simulating the third line as a single L-type circuit or as a single T-type circuit or as a plurality of T-type circuits connected in series from the third terminal which is part of a ?-type circuit to the specific point, the third calculating the voltage of the specific point as a third specific point voltage from the current data and voltage data of the terminal;
calculating a phase difference between the second specific point voltage and the third specific point voltage as a second phase difference;
and adjusting the sampling times of the current and voltage of the third terminal based on the time corresponding to the second phase difference. 13. The method of claim 11 or 12,
The sampling synchronization method is
transmitting a first timing signal together with current data and voltage data of the first terminal from a first transceiver provided at the first terminal to a second transceiver provided at the second terminal;
sending a second timing signal from the second transceiver to the first transceiver together with the current data and voltage data of the second terminal;
The step of adjusting the sampling time of the current and voltage of the first terminal comprises:
a first time interval from when the first transceiver transmits the first timing signal until it receives the second timing signal, the second transceiver transmits the second timing signal; then a first step of controlling the sampling times of the current and voltage of the first terminal so that a second time interval until receiving the first timing signal becomes equal;
a second step of storing a time corresponding to the first phase difference as a third time interval when the first time interval and the second time interval are equal;
and a third step of controlling sampling times of the current and voltage of the first terminal so that the first time interval and the second time interval differ by twice the third time interval. sampling synchronization method. 14. The method of claim 13,
The step of adjusting the sampling time of the current and voltage of the first terminal further comprises:
correcting the third time interval using a time corresponding to the first phase difference calculated when the first time interval and the second time interval differ by twice the third time interval a fourth step;
In the third step, the third time interval corrected by the fourth step is used. 15. The method of claim 14,
In the step of adjusting the sampling time of the current and voltage of the first terminal,
When the power transmission line is normal, the third time interval is continuously corrected by repeatedly executing the fourth step,
The sampling synchronization method according to claim 1, wherein, in the case of a failure of the power line, the fourth step is not executed, but the third step is executed using the third time interval corrected immediately before occurrence of the failure of the power line. 14. The method of claim 13,
In the step of adjusting the sampling time of the current and voltage of the first terminal,
When the power transmission line is normal, after the first step and the second step are executed, the first step for controlling the sampling time of the current and the voltage of the first terminal so that the time corresponding to the first phase difference becomes 0 Step 5 is executed,
The sampling synchronization method according to claim 1, wherein the third step is executed instead of the fifth step when the power transmission line is abnormal.

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