JP2735359B2 - Sampling synchronizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a sampling synchronizer that synchronizes the sampling timing of the electric quantity of each terminal of two or more transmission lines.

(Prior art) As a method of synchronizing the sampling timing of each terminal, a PC is connected between both terminals due to recent development of transmission technology.
There is a method of connecting by M transmission, transmitting and receiving a synchronization signal, and creating a simultaneous reference signal at both ends. This method has already been put to practical use in current-operated relays in which transmission lines are protected by digital relays. However, this method has disadvantages that the transmission device is complicated and a large-capacity transmission line is required. (For example, Japanese Patent Publication No. 57-50262) (Problems to be Solved by the Invention) As described above, the sampling synchronization method of the terminal voltage and current data of the transmission line requires a large-capacity transmission line. However, there is a disadvantage that the apparatus becomes complicated.

The present invention has been made in view of the above circumstances, and has as its object to provide a sampling synchronizer that simplifies a transmission device and does not require a large-capacity transmission line.

[Configuration of the Invention] (Means for Solving the Problems) In order to achieve the above object, a sampling synchronizer according to the present invention includes a terminal device installed at each terminal of a transmission line,
The terminal synchronizes the sampling synchronization of the input voltage and current data. The terminal device samples the voltage and current and inputs the data, transmits the voltage and current data to the central processing unit, and transmits a signal from the central processing unit to its own terminal. And a means for correcting the sampling timing of its own terminal. The central processing unit receives the voltage and current data transmitted from each terminal, and transmits the data from each terminal. Means for calculating a branch point voltage for each terminal device from the obtained voltage and current data, and calculating a phase shift between the voltage and current data of each terminal based on the branch point voltage calculated for each terminal data And a means for transmitting the phase shift to each terminal device.

(Operation) In the present invention, the central processing unit calculates the branch point voltage from the voltage and current data of each terminal, and calculates the phase difference between the branch point voltages obtained from the voltage and current data of each terminal. By transmitting the phase difference, that is, the sampling timing shift to each terminal device, and correcting the sampling timing shift in each terminal device, the sampling synchronization of each terminal can be synchronized.

(Example) Hereinafter, an example is described with reference to drawings.

FIG. 1 shows an example in which a sampling synchronizer according to the present invention is applied to a four-terminal transmission line.

 Hereinafter, a four-terminal system will be described as an example.

The voltages and currents of the terminals A to D of the transmission line 1 are stored in the data processing units 7a, 7b, 7c, and 7c of the terminal devices 6a, 6b, 6c, and 6d installed at the terminals.
7d and transmitted from the data transmission units 8a, 8b, 8c, 8d to the transmission line 12
The data is transmitted to the central processing unit 9 via a, 12b, 12c, and 12d.
In the central processing unit 9, the data of each terminal is received by the transmission / reception unit 10, and the arithmetic unit 11 calculates the sampling phase shift of each terminal based on the data, and then the transmission / reception unit 10 transmits the transmission lines 12a, 12b,
The sampling phase shift of each terminal is transmitted to each terminal device by 12c and 12d. Each terminal device corrects its own sampling timing by the amount of the sampling deviation sent from the central processing unit.

In FIG. 1, A, B, C and D are terminal names, J ₁ and J ₂ are branch points,
l _X is the line length of each section, and Z _X is the impedance per unit length.

First, the outline of the present invention will be described. In FIG. 1, the branch point voltage V _J1 is represented by using the quantity of electricity at the terminals related to the branch point. However, _{a, b:} the between the terminal and the branch point: the terminals of the bus voltage _{a, b:} line current _a of the terminals, _b: impedance l _a per unit length between the terminal and the branch point, l _b Distance.

That is, if the voltage and current of each terminal and the impedance to the branch point are known, the synchronization deviation of each terminal can be obtained using the fact that the branch point voltage obtained from the electric quantity of each terminal is equal. The terminal device corrects its own sampling timing by the amount of the synchronization deviation, so that the sampling of the voltage and current data of each terminal can be synchronized. At the time of an accident between the terminal and the branch point, the expression (1) is not satisfied, so that sampling synchronization is always performed, and at the time of the accident, the sampling synchronization control is locked.

In FIG. 1, the terminals A and B are synchronized using the normal value of the branch point voltage _J1 , and the terminals C and D are synchronized with the branch point voltage _J2.
Will be synchronized using the normal value of.

Normally _J1 and _J2 are not in phase There is a relationship. Therefore, _e is obtained from the quantity of electricity at each terminal by the following equation. From equation (1), equation (2) , The phase shift between the data at the A and B ends and the data at the C and D ends can be obtained, and the mutual phase shift between all the terminals can be obtained. By sending the deviation of the sampling phase of each terminal from the reference value to each terminal,
Sampling synchronization can be taken at each terminal.

Next, the configuration and internal processing of the terminal device and the central processing unit will be described with reference to the drawings.

FIG. 2 is a functional block diagram of the terminal device and the central processing unit.

The voltage and current of the power system 101 are input to the terminal device 103 via the instrument transformer 102. The instantaneous value of the electric quantity is sampled at a constant sampling timing in the data processing means 104 and converted into a digital quantity. The data converted into the digital amount is transmitted to the central processing unit 107 via the transmission means 105 at regular intervals.

The central processing unit 107 receives the data from each terminal device 103 via the transmission unit 108, calculates the sampling synchronization shift between the terminal devices in the arithmetic unit 109, and transmits the shift to each terminal device 103. In the terminal device, the sampling synchronization control means 106 corrects its own sampling timing based on the deviation value from the central processing unit.

By synchronizing the sampling of each terminal device,
The present device can be applied to a fault point locating device, an oscilloscope, and the like.

For example, when a fault occurs in a transmission line, the fault point locating device 110 receives voltage and current data from each terminal device 103 via the transmission device 108 and locates a fault point by the following equation. In the system of FIG. FIG. 3 is a flowchart for calculating the sampling timing shift of each terminal, and the calculation processing of the sampling timing shift in the central processing unit will be described using this flowchart.

In step S201, a branch point voltage viewed from each terminal is obtained.

In Figure 1, the voltage of the branch point J ₁ as seen from the A end _{Ja = a - a a l a} B voltage branch point J ₂ as viewed from the end _Jb = _b - _{b b} l _b sampling synchronization of the terminals _J1a
And _J1b are out of phase. Therefore, in step S202, a phase difference due to a synchronization shift between the A end and the B end is obtained using the branch point voltage.

Voltage branch point J ₁ as viewed from the end A at the sampling time point m is _{Jam = {a - a a}} m = | Ja | branch point voltage seen from the A end of sinθ sampling time n is _Jbn = _{{b -} b b _{Ｎ n} = | _Jb | sin (θ + φ) where φ is the phase difference due to the synchronization shift. This φ can be obtained as follows. For example, when the sampling interval is 30 °, V _Jam −V _Jbn−3 −V _Jam−3 V _Jbn = | _Ja | sin θ | _Jb | sin (θ + φ−90 °) − | _Ja | sin (θ−90 °) _Jb | sin (θ + φ) = − | _Ja | sinθ | _Jb | cos (θ + φ) + | _Ja | cosθ | _Jb | sin (θ + φ) = − | _Ja || _Jb | sin (θ−θ−φ) = | _Ja || _Jb | _sinφ …… (9) V _Jam −V _Jbn + V _Jam-3 V _Jbn-3 = | _Ja | sinθ | _Jb | sin (θ + φ) − | _Ja | sin (θ−90 °) | _Jb | sin (θ + φ−90 °) = | _Ja | sin θ | _Jb | sin (θ + φ) + | _Ja | cos θ | _Jb | cos (θ + φ) = | _Ja || _Jb | cos (θ−θ−φ) = | _Ja | | _Jb | cosφ …… (10) From equations (9) and (10) Becomes

In step S203, the phase of the current at the B end is corrected by the amount of the synchronization shift between the A end and the B end. For example, assuming that the sampling timing at the end A is a reference, the current data at the end B is converted to the phase angle φ
Just delay Like

In step S204, the phase difference due to the synchronization shift between the C end and the D end is determined by the same method as in step S202.

Sampling point voltage branch point J ₂ as viewed from the C-terminal of the _{m Jcm = {c - c c} } m = | Jc | sinθ ...... (13) the voltage of the branching point J ₂ as viewed from the D end of the sampling time point n the _{Jdn = {d - d d}} n = | Jd | a sin (theta + phi ') phase difference due ... (14) sync φ' (9), (10 ), (11)
It is obtained by the same calculation as the equation.

In step S205, similarly to the equation (12), the current data at the D end is corrected and delayed by the phase angle φ 'based on the C end.

In step S206, the data obtained by correcting the B-end current by the synchronization deviation φ with the A-end is used to obtain the equation _e = _A + _b .
Find the current between J ₁ and J ₂ .

In step S207, data obtained by correcting the D-end current by the synchronization deviation φ 'with the C-end is used, and the equation of' _e = _c + _d is used.
Find the current between J ₁ and J ₂ .

Because of the out-of-sync A end and C end _{e = | e | sinωt ... (} 15) 'e = |' e | is expressed as sin (ωt + φ ").

By obtaining the _'e and _{"synchronization} error _e phi",
Finally, a phase difference due to mutual synchronization deviation between the A end, the B end, the C end, and the D end can be obtained.

In step S208, similarly to equations (9), (10), and (11), Φ ″ is obtained in the following manner.
The deviation of the sampling phase from the end, the C end, and the D end is obtained as follows.

With reference to the A-end, the phase shifts of the data at the B, C, and D ends are delayed by B-end; φ, respectively. C-end; delayed by φ ″, D-end; delayed by φ ′ + φ ″.

Then, the central processing unit 107 transmits a data phase shift of each terminal to each terminal device 103.

Terminal at the end A; transmit O _rad Terminal at the end B; transmit φ _rad Terminal at the end C; transmit φ ″ _rad Terminal at the end D; transmit φ ′ + φ ″ _rad .

In the above embodiment, the terminal device transmits the voltage and current data to the central processing unit at regular intervals, but as another embodiment, the central processing unit simultaneously outputs a data transmission request pulse to each terminal device, Now, an example of transmitting voltage and current data to the central processing unit after receiving a pulse will be described with reference to the drawings.

FIG. 4 shows a flow of processing of the central processing unit. Steps
In S301, the transmission delay time _Td between each end and the central processing unit is measured for each terminal. In step S302, _Td is transmitted to each terminal. In step S303, a data transmission request pulse is simultaneously output to each terminal.

FIG. 5 shows a flow of processing of the terminal device. Step S401
Then, the transmission delay time between the central processing unit and its own end is received. In step S402, a data transmission request pulse is received. The voltage and current data at the point in time before the pulse is received in step S403 by the transmission delay time _Td are transmitted to the central processing unit.

FIG. 6 shows a method of measuring the transmission delay time _Td in step S301.

The flag is transmitted from the central processing unit to each terminal device. The terminal device receives the flag from the central processing unit, transmitting the confirmation flag receipt to ₀ hours after T to the central processing unit. The central processing unit measures the time T from transmitting the flag to each terminal device until receiving the flag from each terminal. Since the round trip transmission delay time between the central processing unit and the terminal device is almost equal, the transmission delay time is Is required.

 FIG. 7 is a block diagram of another embodiment.

In this embodiment, the function of the central processing unit is included in the terminal device at the A-end, and is used as a main device.

In the figure, 501 is a transmission line, and 502, 503, 504, and 505 are electric stations. Data is input from the data processing units 511b, 511c, 511d of the terminal devices 510b, 510c, 510d installed at each terminal, and the transmission lines 513b, 513c, 51 are transmitted from the transmission / reception units 512b, 512c, 512d of the terminal device.
The data is transmitted to the main device 506 via 3d. The main unit 506 receives data from each terminal device by the transmission / reception unit 509, inputs voltage and current data of its own terminal from the data processing unit 507, and calculates a deviation of the sampling synchronization of each terminal from the sampling phase itself from the sampling phase. Calculate at 508. The transmission / reception unit 509 transmits the obtained sampling phase shift of each terminal to each terminal device via the transmission paths 513b, 513c, and 513d.

[Effects of the Invention] As described above, according to the present invention, a branch voltage is obtained using the voltage and current obtained at each terminal, and based on the sampling synchronization shift of each terminal calculated using the obtained branch voltage. Since the sampling timing is corrected at each terminal, sampling synchronization of each terminal can be achieved without requiring a special large-capacity transmission line.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a sampling synchronizer according to the present invention, FIG. 2 is a functional block diagram of a terminal device and a central processing unit of the present invention, and FIG. 3 calculates a shift in sampling timing of each terminal. Flowchart, FIG. 4 is a flowchart showing another example of the data transmission process of the terminal device,
FIG. 5 is a flowchart showing another example of the data transmission process of the central processing unit, FIG. 6 is an explanatory diagram of a method of measuring a transmission delay time, and FIG. 7 is a configuration of another embodiment of the sampling synchronizer according to the present invention. FIG. DESCRIPTION OF SYMBOLS 1 ... Transmission line, 2-5 ... Electric station 6 ... Terminal device, 7 ... Data processing part 8 ... Data transmission part, 9 ... Central processing unit 10 ... Transceiving part, 11 ... Calculation part 12 …… Transmission path

Claims (1)

(57) [Claims] 1. A sampling synchronizer of a power system protection control system for synchronizing sampling of voltage and current data of each terminal of a multi-terminal transmission line, means for sampling and inputting terminal voltage and current at a fixed period, A terminal device comprising: means for transmitting voltage and current data to the central processing unit; means for receiving a shift in the sampling phase of the own terminal from the central processing unit; means for correcting the sampling timing of the own terminal; , Means for receiving current data, means for calculating a branch point voltage for each terminal device from voltage and current data transmitted from each terminal device,
Means for calculating the phase shift between the voltage and current data of each terminal based on the branch point voltage calculated for each terminal data;
A sampling synchronizer comprising a central processing unit comprising means for transmitting the phase shift to each terminal device.