JP6271114B1 - Current differential relay and sampling synchronization method - Google Patents

Abstract

In the current differential relay (53A), the voltage calculation unit (74) connects the first terminal and the second terminal of the transmission line based on the current data (I1) and the voltage data (V1) of the first terminal. The voltage at the specific point on the line is calculated as the first specific point voltage, and the voltage at the specific point is calculated as the second specific point voltage based on the current data (Is1) and the voltage data (Vs1) of the second terminal. Here, the voltage calculation unit (74) is configured such that each of the first line connecting the first terminal and the specific point and the second line connecting the second terminal and the specific point are represented by a single π By simulating as an L-type circuit that is a part of the π-type circuit or a single T-type circuit or a plurality of T-type circuits connected in series, 2 Calculate the specific point voltage. The phase difference calculator (75) calculates the phase difference between the first specific point voltage and the second specific point voltage. The synchronization processing unit (73) adjusts the sampling time based on the time corresponding to the phase difference.

Description

  The present disclosure relates to a current differential relay for protecting a transmission line, and a sampling synchronization method for detecting a current value and a voltage value at both ends of the transmission line by the current differential relay and the like.

  The current differential relay that protects the transmission line is provided at both ends of the protection section of the transmission line. Each current differential relay takes in a current value from a current transformer installed at its own end, and transmits the taken current value to each other via a transmission line. Each current differential relay detects a failure in the transmission line based on the difference between the current values at both ends of the transmission line. At that time, synchronization of current sampling timings at both ends of the transmission line is necessary for accurate failure determination.

  A sampling synchronization method that has been used in the past and has been mainstream is disclosed in, for example, Japanese Patent Laid-Open No. 62-262615 (Patent Document 1). In this method, each current differential relay incorporates transmission timing information in transmission data when transmitting current data of its own end to the other end. Each current differential relay measures the time from when transmission timing information is transmitted to the other end until reception of the transmission timing information at the other end. Each current differential relay transmits the measured time to each other, and adjusts the sampling timing so that this time becomes equal to each other.

  In order to accurately perform sampling synchronization by this method, the condition that the transmission time from the own end to the other end is equal to the transmission time from the other end to the own end is essential. However, when transmission is performed using a general-purpose communication device, there may be a difference of several hundreds of μs in the transmission time in these two directions. For this reason, an error occurs in the sampling synchronization, and this synchronization error becomes an error factor of the current differential relay calculation.

  Therefore, in the case where particularly high accuracy is required, such as a failure point locating device for locating a failure point in a transmission line serving as a protection section, it is described in, for example, JP-A-4-17509 (Patent Document 2). A sampling synchronization method has been proposed. Specifically, the fault location apparatus according to this method acquires the detected values of voltage and current at both ends of the transmission line. Then, the fault location device calculates the terminal voltage at the other end by subtracting the voltage drop of the transmission line due to the terminal current at one end from the terminal voltage at one end of the transmission line. The failure point locating device performs sampling synchronization at both ends of the transmission line based on the phase difference between the calculated terminal voltage at the other end and the actually acquired terminal voltage at the other end.

JP-A-62-262615 Japanese Patent Laid-Open No. 4-17509

  The inventor of the present application examined error factors of the sampling synchronization method disclosed in Patent Document 2 and the like described above. As a result, the sampling synchronization method according to this document has found that the influence of the charging current from the transmission line to the ground based on the ground capacitance of the transmission line is not considered. In particular, the charging current cannot be ignored when the power transmission line is formed of an underground cable or when the line length is long with an overhead line, and therefore the error becomes large in sampling synchronization in which the charging current is ignored. Such a problem has not been generally examined so far.

  This disclosure takes the above-mentioned problems into consideration, and its purpose is to provide a sampling synchronization processing method that accurately realizes sampling synchronization at both ends of a transmission line, and a current differential relay that implements this sampling synchronization processing method. Is to provide.

  The current differential relay according to one embodiment is provided at the first terminal of the transmission line. The current differential relay includes an analog / digital conversion unit, a receiver, a voltage calculation unit, a phase difference calculation unit, and a synchronization processing unit. The analog / digital conversion unit samples current and voltage of the first terminal of the transmission line to generate current data and voltage data. The receiver receives current data and voltage data of the second terminal from a second current differential relay provided at the second terminal of the power transmission line. The voltage calculation unit calculates a voltage at a specific point between the first terminal and the second terminal of the transmission line as a first specific point voltage based on the current data and voltage data of the first terminal, Based on the current data and the voltage data, the voltage at this specific point is calculated as the second specific point voltage. The phase difference calculation unit calculates a phase difference between the first specific point voltage and the second specific point voltage. The synchronization processing unit adjusts the sampling time of the current and voltage of the first terminal based on the time corresponding to this phase difference. Here, the voltage calculation unit is configured such that each of the first line connecting the first terminal and the specific point and the second line connecting the second terminal and the specific point are the same as the single π-type circuit. The first specific point voltage and the second voltage are simulated by simulating as an L-shaped circuit that is a part of the π-shaped circuit at the time, or as a single T-shaped circuit or as a plurality of T-shaped circuits connected in series. Calculate the specific point voltage.

  According to the above embodiment, each of the first line and the second line is an L-type circuit that is a part of the π-type circuit when the entire transmission line is a single π-type circuit, or a single line Since the influence of the ground capacity of the transmission line is taken into the calculation by being simulated as a T-type circuit or a plurality of T-type circuits connected in series, sampling synchronization at both ends of the transmission line can be performed with high accuracy.

It is a systematic diagram of the power transmission line which has a back power supply in both ends. It is a block diagram which shows an example of the hardware constitutions of each current differential relay of FIG. FIG. 2 is an equivalent circuit diagram of a positive phase circuit when there is no failure in the power transmission system of FIG. 1. It is a figure for demonstrating the charging current in the positive phase circuit of FIG. It is a vector diagram which shows an example of the phase difference of A terminal voltage V1 and B terminal voltage Vs1. It is a figure for demonstrating the sampling synchronization method. It is an equivalent circuit diagram by the positive phase circuit of the power transmission system simulated with the π-type circuit. It is a figure for demonstrating the charging current in the positive phase circuit of FIG. FIG. 3 is a block diagram illustrating a functional configuration of the current differential relay according to the first embodiment. 4 is a flowchart illustrating a procedure of sampling synchronization processing according to the first embodiment. It is a vector diagram which shows an example of the phase difference of intermediate point voltage Vf and Vfs. It is a flowchart which shows another sampling synchronization procedure. It is a figure for demonstrating in detail the procedure of step S711 of FIG. It is a flowchart which shows another sampling synchronization procedure. It is an equivalent circuit diagram by the positive phase circuit of the power transmission system to which the sampling synchronous process by the modification of Embodiment 1 is applied. It is an equivalent circuit diagram by the positive phase circuit of the power transmission system to which the sampling synchronous process by Embodiment 2 is applied. 10 is a flowchart illustrating a procedure of sampling synchronization processing according to the second embodiment. It is an equivalent circuit diagram by the positive phase circuit of the power transmission system at the time of simulating a power transmission line with two stages of T-shaped circuits. It is a flowchart which shows the sampling synchronous procedure of the power transmission system simulated with the equivalent circuit of FIG. It is an equivalent circuit diagram by the positive phase circuit of the power transmission system to which the sampling synchronous process of Embodiment 3 is applied. It is a flowchart which shows the sampling synchronous procedure of the power transmission system simulated with the equivalent circuit of FIG. It is an equivalent circuit diagram by the positive phase circuit of a power transmission system in the case of simulating each terminal to an intermediate point with a two-stage T-shaped circuit. It is a flowchart which shows the sampling synchronous procedure of the power transmission system simulated with the equivalent circuit of FIG. It is a systematic diagram of a three-terminal power transmission line having a back power supply at each terminal. It is an equivalent circuit diagram by the positive phase circuit of the power transmission system of FIG. It is a flowchart which shows the procedure which synchronizes the sample timing of A terminal with the sample timing of B terminal. It is a flowchart which shows the procedure which synchronizes the sample timing of C terminal with the sample timing of B terminal. It is a systematic diagram of the 4-terminal power transmission line which has a back power supply in each terminal. It is a flowchart which shows an example of the procedure of a sampling synchronous process in the power transmission system of FIG.

  Hereinafter, each embodiment will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

Embodiment 1 FIG.
<Common configuration and assumptions>
First, the configuration and assumptions common to the respective embodiments will be described, and then the features of the first embodiment will be described.

[System diagram of transmission line with power supply at both ends]
FIG. 1 is a system diagram of a transmission line having a rear power supply at both ends. Referring to FIG. 1, a rear power source 52 </ b> A is provided at the A end (also referred to as a first end) of the power transmission line 50, and a rear power source 52 </ b> B is provided at the B end (also referred to as a second end) of the power transmission line 50. . The power transmission line 50 is a three-phase power transmission line, but in FIG. 1, it is shown as a single line for ease of illustration.

  A current transformer (CT: Current Transformer) CT1 is provided at the A end of the transmission line 50, and a voltage transformer (VT: Voltage Transformer) VT1 is provided at the A-end bus 51A. Similarly, a current transformer CT2 is provided at the B end of the transmission line 50, and a voltage transformer VT2 is provided at the B end bus 51B. Further, on the power transmission line 50 between the A end and the B end, a circuit breaker (CB: Circuit Breaker) 68A is provided close to the A end, and a circuit breaker 68B is provided close to the B end.

  In this specification, the current transformers CT1 and CT2 are collectively referred to as current transformers CT1 and CT2 when they are collectively referred to or unspecified. The voltage transformers VT1 and VT2 are collectively referred to as “voltage transformer VT” when they are collectively referred to or unspecified. Further, current and voltage may be collectively referred to as an electric quantity.

  Current differential relays 53A and 53B are further provided at the A end and B end of the power transmission line 50, respectively. In this specification, the current differential relay 53 is described when a current differential relay provided at any of the terminals is shown. The current differential relays 53A and 53B provided at each terminal of the power transmission line 50 may be collectively referred to as a current differential relay system.

  Each of the current differential relays 53 </ b> A and 53 </ b> B obtains a signal representing a three-phase alternating current flowing through the own end of the transmission line 50 from the own-end current transformer CT and the three-phase AC voltage at the own end of the transmission line 50. Is obtained from the voltage transformer VT on its own end. Each of the current differential relays 53A and 53B generates current data and voltage data by sampling and A / D converting the acquired current and voltage at its own end. Each current differential relay transmits its own current data and voltage data to the current differential relay at the other end via the communication path 54. In this case, the communication path 54 may be wired and wireless. The current differential relays 53A and 53B calculate the difference current between both ends of the transmission line 50 from the acquired current data of the own end and the other end, and are inside the current transformers CT1 and CT2 based on the calculated difference current. It is determined whether or not a failure has occurred in the transmission line 50 within the protection section.

  In the above, in order to accurately calculate the differential current at both ends of the transmission line 50, the timings at which the current differential relays 53A and 53B at both ends of the transmission line 50 sample current values from the current transformers CT1 and CT2 are synchronized. There is a need. For this reason, the current differential relays 53A and 53B perform the synchronization process. The most basic synchronization process is as follows.

  Specifically, each current differential relay 53 transmits current and voltage sampling data of its own current and voltage to the other end at regular intervals (for example, a cycle of 30 ° of the electrical angle of AC electricity). A timing signal is incorporated into the transmission data. Each current differential relay 53 measures the time interval between the transmission time of the timing signal to the other end and the reception time of the timing signal from the other end. Each current differential relay 53 transmits the measured time interval to the other end. Each current differential relay 53 has an electric quantity sampling timing and a timing signal so that the time interval T1 between the transmission time and the reception time of the timing signal measured at its own end is equal to the time interval T2 received from the other end. Adjust the transmission timing.

  In practice, the timing adjustment described above may be performed by only one of the current differential relays 53A and 53B at both ends of the transmission line 50. For example, one of the current differential relays 53A and 53B (slave) performs a timing adjustment based on information representing the above time interval received from the other (master).

  In order to accurately perform the above basic synchronization processing, the transmission time through the communication path 54 from the A end to the B end of the transmission line 50 and the transmission time through the communication path 54 from the B end to the A end are The precondition that is equal to each other is necessary. If these transmission times are different, the sampling synchronization error is ½ of the difference between the transmission times. When a general-purpose communication device is used, even if the length of the communication path from the A end to the B end is equal to the length of the communication path from the B end to the A end, the difference in transmission time is about several hundreds μs at the maximum. There is a case.

  Therefore, the current differential relay 53 of the present disclosure performs sampling synchronization processing using voltage data and current data at both ends of the transmission line 50. Specifically, the current differential relay 53 calculates the voltage at a specific point on the transmission line 50 using the voltage data and current data at the A end, and uses this voltage data and current data at the B end to calculate this specific point. Calculate the voltage of. The current differential relay 53 performs sampling synchronization of both ends of the transmission line 50 based on the calculated phase difference between the two voltages. The specific point may be at the B end. In this case, the current differential relay 53 calculates the voltage at the B end using the voltage data and current data at the A end, and actually calculates the calculated voltage at the B end. Sampling synchronization of both ends of the transmission line 50 is performed based on the detected phase difference from the voltage at the B end.

  Hereinafter, this sampling synchronization method is referred to as a sampling synchronization method based on a voltage phase difference. The sampling synchronization process based on the voltage phase difference may be used to complement the synchronization process based on the time interval between the transmission time and the reception time of the timing signal described above, or may be used instead of the synchronization process described above. . The basic concept of the sampling synchronization processing based on this voltage phase difference will be described later with reference to FIGS.

[Example of hardware configuration of current differential relay]
FIG. 2 is a block diagram illustrating an example of a hardware configuration of each current differential relay of FIG. The current differential relay 53 in FIG. 2 has the same configuration as a so-called digital relay device. Specifically, referring to FIG. 2, a current differential relay 53 includes an input conversion unit 100, an A / D (analog / digital) conversion unit 110, an arithmetic processing unit 120, and an I / O (Input and Output). Unit 130.

  The input conversion unit 100 includes auxiliary transformers 101_1, 101_2,... For each input channel. The input converter 100 receives the current signal from the current transformer CT of FIG. 1 and the voltage signal from the voltage transformer VT. Each auxiliary transformer 101 converts the current signal from the current transformer CT and the voltage signal from the voltage transformer VT into a signal of a voltage level suitable for signal processing in the A / D converter 110 and the arithmetic processor 120. .

  The A / D conversion unit 110 includes analog filters (AF) 111_1, 111_2,..., Sample hold circuits (S / H: Sample Hold Circuit) 112_1, 112_2,. A / D converter 114. The analog filter 111 and the sample hold circuit 112 are provided for each channel of the input signal.

  Each analog filter 111 is a low-pass filter provided to remove aliasing errors during A / D conversion. Each sample and hold circuit 112 samples and holds the signal that has passed through the corresponding analog filter 111 at a specified sampling frequency. The sampling frequency is, for example, 4800 Hz. The multiplexer 113 sequentially selects the voltage signals held in the sample hold circuits 112_1, 112_2,. The A / D converter 114 converts the signal selected by the multiplexer 113 into a digital value.

  The arithmetic processing unit 120 includes a CPU (Central Processing Unit) 121, a RAM (Random Access Memory) 122, a ROM (Read Only Memory) 123, and a bus 124 for connecting them. The CPU 121 controls the overall operation of the current differential relay 53. The RAM 122 and ROM 123 are used as the main memory of the CPU 121. The ROM 123 can store programs, setting values for signal processing, and the like by using a non-volatile memory such as a flash memory.

  Note that the arithmetic processing unit 120 only needs to be configured by some circuit, and is not limited to the example of FIG. For example, the arithmetic processing unit 120 may include a plurality of CPUs. Further, the arithmetic processing unit 120 may be configured with at least one ASIC (Application Specific Integrated Circuit) instead of a processor such as a CPU, or may be configured with at least one FPGA (Field Programmable Gate Array). Also good. Alternatively, the arithmetic processing unit 120 may be configured by any combination of a processor, an ASIC, and an FPGA.

  The I / O unit 130 includes a transceiver (TX / RX) 131, a digital input (D / I) circuit 132, and a digital output (D / O) circuit 133. The transceiver 131 includes a transmitter 131_1 and a receiver 131_2, and communicates with the transceiver 131 provided in the current differential relay 53 at the other end via the communication path 54 in FIG. The digital input circuit 132 and the digital output circuit 133 are interface circuits for performing communication between the CPU 121 and an external device. For example, the digital output circuit 133 outputs a trip signal to the circuit breaker 68A or 68B on its own end side shown in FIG.

[Sampling synchronization method based on voltage phase difference]
(Equivalent circuit with positive phase circuit)
When sampling synchronization processing based on the voltage phase difference is performed in a state where there is no failure in the transmission line 50, the synchronization processing may be performed using voltage data and current data of any one of the three phases. . In the present disclosure, sampling synchronization processing is performed using a positive phase current and a positive phase voltage of the symmetric coordinate method for the purpose of leveling the detection errors in consideration of current and voltage detection errors.

  FIG. 3 is an equivalent circuit diagram of a positive phase circuit when there is no failure in the power transmission system of FIG. Referring to FIG. 3, the positive phase voltage at the A terminal is V1, and the positive phase current at the A terminal is I1. Similarly, the positive phase voltage at the B end is Vs1, and the positive phase current at the B end is Is1.

As is well known, the positive phase voltage V1 uses the A-phase three-phase voltages Va, Vb, Vc,
V1 = (Va + α · Vb + α ² · Vc) / 3 (1)
It is expressed. The positive phase current I1 is obtained by using the three-phase currents Ia, Ib and Ic at the A end
I1 = (Ia + α · Ib + α ² · Ic) / 3 (2)
It is expressed. Where j is the imaginary unit,
α = (− 1 + j · √3) / 2 (3)
Holds. The same applies to the B end. In this specification, the multiplication symbol is represented by “·”, “*” or “×”.

  The positive phase impedance of the power transmission line 50 is Z1, and the ground capacitance of the power transmission line 50 is C (may be simply referred to as ground capacity C). The charging current Ic corresponds to a current flowing through the ground capacitance C. Note that the resistance, reactance, and capacity of the transmission line 50 are represented by distributed constants, but are represented here as lumped constants for simplicity. Hereinafter, the positive phase voltage, the positive phase current, the positive phase impedance, and the like may be simply referred to as voltage, current, and impedance for the sake of simplicity.

(Charging current of transmission line)
FIG. 4 is a diagram for explaining the charging current in the positive phase circuit of FIG. In FIG. 4, the position of the A end is represented by x = 0, and the position of the B end is represented by x = 1. That is, the length of the power transmission line 50 is normalized by 1.

  FIG. 4A shows a voltage change on the transmission line when there is a voltage difference between the local voltage V1 and the counterpart voltage Vs1. Originally, the voltages V1 and Vs1 should be represented by vectors (that is, voltage amplitude and phase), but as shown in the graph 60, it is simply shown that there is a difference in scalar (that is, only voltage amplitude). . Actually, there are more cases where there is no difference in amplitude and there is a phase difference between the voltages V1 and Vs1.

  A graph 61 in FIG. 4B shows a change in load current on the transmission line. As described above, the load current flows due to the difference in voltage vectors at both ends of the transmission line 50. The load current at the A end is I1, and the load current at the B end is Is1. In the load current Is1, the direction from the B end to the A end is positive.

The charging current Ic (x) at the point x on the transmission line depends on the transmission line voltage V (x) at the point x. The relationship is that the capacitance per unit length of the transmission line is C,
Ic (x) = jωC · V (x) (4)
It is represented by At the A end, ie, x = 0,
Ic (0) = jωC · V1 (5)
And at the B end, ie, x = 1,
Ic (1) = jωC · Vs (6)
Holds. Therefore, the total amount of the charging current Ic of the transmission line 50 is expressed by the following equation (7). Here, x represents a position on the transmission line, and the A end of the transmission line 50 is set to x = 0, and the B end of the transmission line 50 is set to x = 1.

(Sampling synchronization based on voltage phase difference when there is no load current)
When there is no load current, the A terminal voltage V1 and the B terminal voltage Vs1 are equal (see the graph 62 in FIG. 4A). In this case, the phase difference between the A-end voltage V1 and the B-end voltage Vs1 should be negligible. However, since the sampling timing at both ends of the transmission line 50 is actually shifted, the A A phase difference φ occurs between the end voltage V1 and the B end voltage Vs1.

FIG. 5 is a vector diagram illustrating an example of a phase difference between the A-end voltage V1 and the B-end voltage Vs1. In the vector diagram of FIG. 5, the B-end voltage Vs1 is advanced by the phase difference φ from the A-end voltage V1. Therefore, for sampling synchronization, it is necessary to advance the sampling time at the B end by a time t corresponding to the phase difference φ, or delay the sampling time at the A end by a time t corresponding to the phase difference φ. The time t is expressed in units of the phase difference φ.
t = (φ / 360 °) * 1 cycle time (8)
It is represented by If the AC frequency is f, the time for one cycle is 1 / f [sec].

[Combination of two sampling synchronization methods]
Next, a method of combining the sampling synchronization method based on the voltage phase difference with the sampling synchronization method based on the time interval between the transmission time and the reception time of the timing signal will be described.

  FIG. 6 is a timing chart for explaining the sampling synchronization method. Similarly to FIG. 5, it is assumed that the B terminal voltage Vs1 is advanced by the phase difference φ from the A terminal voltage V1. Let t be the time corresponding to the phase difference φ.

  Referring to FIG. 6A, the timing signal transmitted from the A end at time t1 is received at the B end at time t4, and the timing signal transmitted from the B end at time t2 is received at the A end at time t3. Suppose that In this case, the time interval T1 between the transmission time and the reception time of the timing signal at the A end (ie, from time t1 to time t3) is the time interval T2 between the transmission time and the reception time of the timing signal at the B end (ie, , From time t2 to time t4). However, the sampling timing at the B end is delayed by a time t from the sampling timing at the A end.

  In the above case, the signal transmission time from the B end to the A end is T1-t, and the signal transmission time from the A end to the B end is T1 + t. Accordingly, the fact that sampling synchronization can be achieved by correcting the sampling timing at the B end so as to advance by the time t in the above equation (8) means that the B end via the communication path 54 in FIG. This means that the transmission time is shorter by 2 × t than the transmission time from the A end to the B end.

  Referring to FIG. 6B, the time interval between the transmission time and the reception time of the timing signal at the A end is T3, and the time interval between the transmission time and the reception time of the timing signal at the B end is T4. In this case, the current differential relay 53 at either the A end or the B end (for example, the slave side) is configured to sample the electric quantity so that the time interval T3 is longer than the time interval T4 by 2 × t. And the timing which transmits a timing signal is adjusted. Thereby, sampling synchronization at the A end and the B end can be realized.

  Specifically, as shown in FIG. 6B, it is assumed that timing signals are transmitted from the A end and the B end to the other end at time t11. Then, the timing signal transmitted from the A end is received at the B end at time t13 when a time 2 × t has elapsed from the time t12 when the timing signal transmitted from the B end is received at the A end.

  As described above, even if there is a difference in the transmission time of the communication path 54 from upstream to downstream (that is, from the own end to the other end and from the other end to the own end), the amount of electricity can be more accurately determined by the sampling synchronization processing based on the voltage phase difference. Sampling becomes possible. As a result, the protection characteristic of the transmission line by the current differential relay is improved.

  As shown by the graph 60 in FIG. 4A, when affected by the load current, a voltage difference occurs between the A-end voltage V1 and the B-end voltage Vs1. A sampling synchronization method applicable also in this case will be described below as a first embodiment with reference to FIGS.

  When there is no system failure in the transmission line and the load current flowing through the transmission line is so small that it can be ignored, only the charging current flows through the current transformers CT1 and CT2 provided at the A and B ends. Therefore, a current detection threshold value in the current differential relay 53 is set in advance so as not to detect the charging current (that is, slightly larger than the charging current). When the load current cannot be detected (that is, below the threshold), the phase difference is calculated from the voltages at both ends of the transmission line 50, and the time corresponding to the phase difference (the above equation (8)) is used. It is possible to detect the difference between the upstream and downstream of the transmission time of the communication path 54 almost accurately. Therefore, when the current values at both ends of the transmission line 50 do not exceed the threshold value, the transmission time of the transmission line 50 is set to 2 using the time t corresponding to the phase difference measured in advance by the above method. Assuming that there is a difference of xt, timing synchronization processing based on the time interval between the transmission time and the reception time of the timing signal can be executed.

<Sampling synchronization method of Embodiment 1>
In the first embodiment, by simulating the power transmission line 50 with a π-type circuit, it is assumed that the charging current flows in half at each terminal, and the terminal current compensated for the charging current is used at the intermediate point of the power transmission line 50. A method for calculating the voltage will be described. An intermediate point is more generally referred to as a specific point. In the case of the first embodiment, the voltage at the intermediate point calculated using the current and voltage at the A end (also referred to as a first specific point voltage) and the voltage at the intermediate point calculated using the current and voltage at the B end (second And the sampling timing is corrected from the time corresponding to the phase difference.

  Thus, by incorporating the charging current into the calculation, the sampling synchronization error can be further reduced even when there is an influence of the load current. Hereinafter, specific description will be given with reference to the drawings.

[Equivalent circuit of transmission line]
FIG. 7 is an equivalent circuit diagram of a positive phase circuit of a power transmission system simulated by a π-type circuit. Note that simulating the entire transmission line as a π-type circuit means that the first line from the A end to the intermediate point 57 is simulated by an L-type circuit, and the second line from the B end to the intermediate point 57 is another L-type. It can be thought that it was simulated by a circuit.

  Referring to FIG. 7, the positive phase voltage at the A terminal is V1, and the positive phase current at the A terminal is I1. Similarly, the positive phase voltage at the B end is Vs1, and the positive phase current at the B end is Is1.

  Let C be the total amount of ground capacity in the entire transmission line 50. In the π-type circuit, a capacitor having a size that is ½ of the ground capacitance C is connected to the A end, and a capacitor having a size that is ½ of the ground capacitance C is connected to the B end. As a result, the charging current Ic flows through the A terminal, and the charging current Ics flows through the B terminal.

  The positive phase impedance of the entire transmission line 50 is assumed to be Z1. Then, the line impedance from the A end of the transmission line 50 to the intermediate point 57 is represented by Z1 / 2, and the line impedance from the B end of the transmission line 50 to the intermediate point 57 is represented by Z1 / 2.

  The voltage at the intermediate point 57 calculated from the current I1 at the A end and the voltage V1 is Vf, and the voltage at the intermediate point 57 calculated from the current Is1 and the voltage Vs1 at the B end is Vsf. Note that the position of the A end is x = 0, the position of the B end is x = 1, and the position of the intermediate point is x = 1/2.

[Charging current]
FIG. 8 is a diagram for explaining the charging current in the positive phase circuit of FIG. FIG. 8A shows a voltage change on the transmission line when there is a voltage difference between the local voltage V1 and the counterpart voltage Vs1. A graph 64 represents the voltages V1 and Vs1 as vectors (that is, indicated by voltage amplitude and phase), and schematically shows a case where there is a phase difference rather than amplitude. The graph 63 is simply shown so that there is a difference in scalars (that is, only voltage amplitude).

  A graph 65 in FIG. 8B shows a change in load current on the transmission line. A load current obtained by subtracting the charging current Ic from the terminal current I1 flows at the A end, and a load current obtained by subtracting the charging current Ics from the terminal current Is1 flows at the B end.

[Functional configuration example of current differential relay]
FIG. 9 is a block diagram illustrating a functional configuration of the current differential relay according to the first embodiment. Although FIG. 9 shows the functional configuration of the A-terminal current differential relay 53A, the same applies to the B-terminal current differential relay 53B. The functional block diagram of FIG. 9 is also applied to other embodiments described later.

  From a functional viewpoint, the arithmetic processing unit 120 of the current differential relay 53A includes a self-end data storage unit 70, a transmission data processing unit 71, a reception data processing unit 72, a synchronization processing unit 73, and a voltage calculation unit 74. And a phase difference calculator 75 and a relay calculator 76. These functions are realized when the program is executed by the CPU 121 of the arithmetic processing unit 120.

  Referring to FIG. 9, the signal representing the current and voltage at its own end received by input conversion unit 100 is converted into a digital value by A / D conversion unit 110 and stored in self-end data storage unit 70. Thereafter, the data is processed into transmission data by the transmission data processing unit 71 for transmission to the counterpart relay. The transmission data is transmitted to the receiver (RX) 131_2 of the counterpart relay by the transmitter (TX) 131_1. On the other hand, received data (that is, current data and voltage data of the other end) received from the other end relay transmitter 131_1 received by the receiver (RX) 131_2 is received by the received data processing unit 72. To be processed.

  The synchronization processing unit 73 performs a sampling synchronization process on the local data and the counterpart data for calculation in order to synchronize the sampling time of the data acquired by the both-end relays of the transmission line. Specifically, the synchronization process is performed based on the time interval between the transmission time and the reception time of the timing signal described above.

  For the calculation in the voltage calculation unit 74, the local end data and the counterpart end data after the above-described synchronization processing are used. Specifically, voltage calculation unit 74 calculates voltage Vf at a specific point on power transmission line 50 (in the first embodiment, intermediate point 57) using current I1 and voltage V1 at its own end, and A voltage Vsf at a specific point is calculated using the current Is1 and the voltage Vs1. For this calculation, the impedance Z1 of the transmission line 50 and the ground capacitance C of the transmission line 50 are used.

  The phase difference calculator 75 calculates the phase difference φ between the voltage Vf at the specific point calculated based on the local end data and the voltage Vsf at the specific point calculated based on the counterpart data. The phase difference calculator 75 further obtains a time t corresponding to the calculated phase difference φ, and feeds back information on the time t to the synchronization processor 73. Alternatively, the phase difference calculation unit 75 calculates the difference between the transmission time from the own end to the other end and the transmission time from the other end to the own end (that is, 2 × t when T1 = T2 in FIG. 6A). Alternatively, the synchronization processing unit 73 may be fed back.

  Based on the transmission time difference detected by the phase difference calculation unit 75, the synchronization processing unit 73 performs sampling synchronization processing on the local data and the counterpart data for calculation. Specifically, as described in FIG. 6B, the time interval between the transmission time and the reception time of the timing signal at the A end is T3, and the time interval between the transmission time and the reception time of the timing signal at the B end. Is set to T4, the sampling timing is adjusted so that the time interval T3 and the time interval T4 differ by the transmission time difference. Alternatively, the synchronization processing unit 73 corrects the sampling time only for the time t corresponding to the phase difference φ (that is, the time corresponding to the current phase difference φ is 0) without being based on the transmission time difference. Also good.

  Furthermore, when the counterpart relay is the master (when it is a slave), the synchronization processing unit 73 determines that the time t corresponding to the phase difference φ obtained by the phase difference calculation unit 75 is 0. The sampling timing in the / D conversion unit 110 is controlled. As a result, the own-end sampling timing is synchronized with the counterpart-end sampling timing.

  The relay calculation unit 76 uses the data of the current I1 of the other end and the data of the current I1 synchronized with the data of the current Is1 of the other end, and enters the protection section of the transmission line 50 based on these difference currents. It is determined whether or not a failure has occurred.

  Any known method can be used to calculate the phase difference in the phase difference calculation unit 75.

For example, the sampling intervals of the voltages Vf and Vsf are set every 30 °, the current values of the voltages Vf and Vsf are set to Vf [m] and Vsf [m], respectively, and values 90 ° before the current time are set to Vf [m−3]. And Vsf [m-3]. Then, the cosine and sine of the phase difference φ between the voltage Vf [m] and the voltage Vsf [m] are obtained by using the amplitude | Vf | of the voltage Vf and the amplitude | Vsf |
| Vf | × | Vsf | × cosφ = Vf [m] × Vsf [m] + Vf [m-3] × Vsf [m-3] (9)
| Vf | × | Vsf | × sinφ = Vf [m-3] × Vsf [m] −Vf [m] × Vsf [m-3] (10)
It is expressed.

[Sampling synchronization procedure-1]
FIG. 10 is a flowchart showing the procedure of the sampling synchronization process according to the first embodiment. Hereinafter, the procedure of the sampling synchronization processing will be described in more detail mainly with reference to FIGS. 7, 9, and 10. In the following description, the A end is referred to as a self end, and the B end is referred to as a counterpart end.

  First, the A / D conversion unit 110 in FIG. 9 generates current data I1 and voltage data V1 by sampling its own current and voltage (step S101).

Next, the voltage calculation unit 74 calculates the charging current Ic using the self-end voltage V1 (step S102). If the imaginary unit is j and the angular frequency of the AC voltage of the transmission line 50 is ω, the charging current Ic is
Ic = jω (C / 2) * V1 (11)
It is represented by Here, C is the total amount of the ground capacity of the transmission line, and Ic is the charging current from the end of the line to the intermediate point 57 (that is, 1/2 of all the lines).

Next, the voltage calculation unit 74 calculates the midpoint voltage Vf using the value (I1-Ic) obtained by subtracting the charging current Ic from the self-end current I1 and the self-end voltage V1 (step S103). Specifically, the midpoint voltage Vf is
Vf = V1- (Z1 / 2) * (I1-Ic) (12)
It is represented by The second term on the right side of the above equation (12) indicates the voltage drop caused by the transmission line 50 from the own end to the intermediate point 57.

  Next, the receiver 131_2 receives the current and voltage sampling values (that is, the current data Is1 and the voltage data Vs1) at the other end (step S104). The received current data Is1 and voltage data Vs1 are taken into the received data processing unit 72. Note that step S104 may be executed before step S102. Further, the above steps S102 and S103 may be executed in parallel with steps S105 and S106.

Next, the voltage calculation unit 74 calculates the charging current Ics using the counterpart voltage Vs1 (step S105). Specifically, the charging current Ics is
Ics = jω (C / 2) * Vs1 (13)
And the charging current in the line from the other end to the intermediate point 57 (that is, 1/2 of all the lines).

Next, the voltage calculation unit 74 calculates the midpoint voltage Vsf using the value (Is1-Ics) obtained by subtracting the charging current Ics from the counterpart end current Is1 and the counterpart end voltage Vs1 (step S106). Specifically, the midpoint voltage Vsf is
Vsf = Vs1- (Z1 / 2) * (Is1-Ics) (14)
It is represented by The second term on the right side of the above equation (14) indicates the voltage drop caused by the transmission line 50 from the other end to the intermediate point 57.

  Next, the phase difference calculation unit 75 calculates the phase difference φ between the midpoint voltages Vs and Vsf (step S107). Further, the phase difference calculation unit 75 calculates a delay time (or advance time) corresponding to the calculated phase difference φ and outputs it to the synchronization processing unit 73. The synchronization processing unit 73 corrects the sampling time by the delay time or advance time (step S108). That is, the synchronization processing unit 73 controls the current and voltage sampling times at its own end so that the time t corresponding to the phase difference φ becomes zero.

  The midpoint voltage Vf calculated by Expression (12) and the midpoint voltage Vsf calculated by Expression (14) indicate the same voltage vector when sampling synchronization is established at both ends of the transmission line 50. When sampling synchronization is not established, a phase difference occurs between the midpoint voltages Vs and Vsf. Therefore, sampling timing can be synchronized by measuring the phase difference and performing synchronization correction only for the time corresponding to the phase difference.

FIG. 11 is a vector diagram showing an example of the phase difference between the midpoint voltages Vf and Vfs. In FIG. 11, the phase of the intermediate point voltage Vf calculated from the local end voltage V1 and the local end current I1 is advanced by φ from the phase of the intermediate point voltage Vsf calculated from the counterpart end voltage Vs1 and the counterpart end current Is1. It shows a state. Therefore, the sampling timing at the own end is advanced by the phase angle φ from the sampling timing at the other end. Therefore, in the sampling synchronization process, the self-sampling time is set to the time t corresponding to the phase difference φ,
t = (φ / 360 °) × 1 cycle time (15)
Correct in the delay direction only. If the AC frequency is f, the time for one cycle is 1 / f [sec]. The cycle time of one cycle is represented by 1 / f, where the AC frequency is f.

  By performing the sampling synchronization process according to the above procedure, sampling synchronization with less influence of the load current due to the voltage difference between both ends of the transmission line 50 becomes possible. Thereby, the protection characteristic of the transmission line by the current differential relay is improved.

[Sampling synchronization procedure-2]
The sampling synchronization processing based on the voltage phase difference is not applicable when the voltage and current phases at the A and B ends are affected by a failure on the transmission line. Further, as in the case where at least one of the circuit breakers 68A and 68B provided on the power transmission line 50 between the A end and the B end or a disconnector (not shown) is in an open state, the A end and the B end When the interval is not in the conductive state, the sampling synchronization processing based on the voltage phase difference cannot be applied. Further, the sampling synchronization processing based on the voltage phase difference is based on the premise that the absolute value of the voltage phase difference to be measured is less than 180 degrees, and cannot be applied when the timing shift width to be synchronized is too large.

  In such a case, as described in FIGS. 6A and 6B, the sampling synchronization processing may be executed by combining sampling synchronization methods based on the time interval between the transmission time and the reception time of the timing signal. it can. Hereinafter, a specific description will be given with reference to FIGS. 1, 9, and 12. Note that the following procedure can be similarly applied to other embodiments described later.

  FIG. 12 is a flowchart showing another sampling synchronization procedure. In the initial state, it is assumed that no failure has occurred in the power transmission line 50 and the circuit breaker and disconnector provided between the terminals are in the on state.

  First, in step S701, the transmitter 131_1 of the A-terminal current differential relay 53A transmits a timing signal together with its own current data and voltage data to the B-terminal current differential relay 53B. Similarly, the transmitter 131_1 of the B-end current differential relay 53B transmits a timing signal together with its own-end current data and voltage data to the A-end current differential relay 53A.

  In the next step S702, the receiver 131_2 of the A-terminal current differential relay 53A receives the timing signal together with the current data and voltage data from the other end. Similarly, the receiver 131_2 of the B-terminal current differential relay 53A receives the timing signal together with the current data and voltage data from the other end.

  Furthermore, each current differential relay 53A, 53B calculates the time interval between the transmission time of the timing signal from its own end and the reception time of the timing signal from the other end. The current differential relays 53A and 53B mutually transmit the calculated time interval between the transmission time and the reception time of the timing signal. The calculation of the time interval and the transmission of the calculation result may be, for example, about once per cycle of the power system.

  In the next step S703, the synchronization processing unit 73 of the A-terminal current differential relay 53A transmits the time interval T1 between the transmission time and the reception time of the timing signal on the own end side and the transmission of the timing signal on the other end side. The current and voltage sampling times in the A / D converter 110 of the A-terminal current differential relay 53A are controlled so that the time interval T2 between the time and the reception time is equal.

  As a result, when it is determined that synchronization is established, that is, when the time interval T1 is equal to the time interval T2 (YES in step S704), the position of the A-terminal current differential relay 53A is determined in the next step S705. As described in steps S101 to S107 of FIG. 10 described above, the phase difference calculation unit 75 generates the specific point voltage Vsf based on the current data and voltage data at the other end and the specific point voltage Vsf based on the current data and voltage data at the other end. And the phase difference φ is calculated. Here, the specific point is an intermediate point between the A end and the B end. Then, the synchronization processing unit 73 stores the time t corresponding to the phase difference φ as a specific time interval Ts in a memory (for example, the RAM 122 or the ROM 123 in FIG. 2). As described with reference to FIGS. 6A and 6B, twice the specific time interval Ts is obtained by the transmission time of the communication path from the A end to the B end and the transmission time of the communication path from the B end to the A end. It corresponds to the difference.

  Thereafter, as in the case of steps S701 and S702, first, in step S706, the transmitter 131_1 of the A-terminal current differential relay 53A sends the timing signal together with its own-end current data and voltage data to the B-terminal current differential. Transmit to relay 53B. Similarly, the transmitter 131_1 of the B-end current differential relay 53B transmits a timing signal together with its own-end current data and voltage data to the A-end current differential relay 53A.

  In the next step S707, the receiver 131_2 of the A-terminal current differential relay 53A receives the timing signal together with the current data and voltage data from the other end. Similarly, the receiver 131_2 of the B-terminal current differential relay 53A receives the timing signal together with the current data and voltage data from the other end.

  Furthermore, each current differential relay 53A, 53B calculates the time interval between the transmission time of the timing signal from its own end and the reception time of the timing signal from the other end. The current differential relays 53A and 53B mutually transmit the calculated time interval between the transmission time and the reception time of the timing signal. The calculation of the time interval and the transmission of the calculation result may be, for example, about once per cycle.

  Synchronization processing is executed in the next steps S708 to S711. The execution frequency of the synchronization processing may be about once every several cycles, for example.

  Specifically, in step S708, the synchronization processing unit 73 of the A-terminal current differential relay 53A determines the time interval T1 between the transmission time and the reception time of the timing signal on the own end side, and the timing signal on the other end side. The current and voltage of the A / D converter 110 of the A-terminal current differential relay 53A are set so that the time interval T2 between the transmission time and the reception time differs by twice the specific time interval Ts obtained in step S705. Control sampling time.

  For example, in step S705 described above, the specific point voltage Vsf based on the B-end current data and voltage data is advanced by the phase difference φ from the specific point voltage Vs based on the A-end current data and voltage data. . In this case, as described in FIG. 6A, the transmission time through the communication path 54 from the A end to the B end is 2 × longer than the transmission time through the communication path 54 from the B end to the A end. Only Ts is long. Therefore, the sampling timing at the A end is controlled so that the time interval T1 is shorter than the time interval T2 by 2 × Ts.

  Conversely, in step S705 described above, it is assumed that the specific point voltage Vsf based on the B-terminal current data and voltage data is delayed by the phase difference φ from the specific point voltage Vs based on the A-terminal current data and voltage data. . In this case, the transmission time through the communication path 54 from the A end to the B end is shorter by 2 × Ts than the transmission time through the communication path 54 from the B end to the A end. Therefore, the sampling timing at the A end is controlled so that the time interval T1 is longer by 2 × Ts than the time interval T2.

  When it is determined that the synchronization is achieved by executing step S708, that is, the difference between the time interval T1 and the actual interval T2 is equal to 2 × Ts (YES in step S709), and the power transmission line is faulty. Is not generated, and the circuit breaker between both ends of the transmission line is not opened (NO in step S710), the process proceeds to step S711 for correcting the specific time interval Ts described above. The reason for correcting the specific time interval Ts in this way is that the transmission time difference 2 × Ts obtained in step S705 is affected by measurement errors, jitter, wander, fluctuations in device characteristics (for example, clock fluctuations, etc.), etc. This is because it may fluctuate. As another reason, when an abnormality occurs in the transmission path between the current differential relay 53A at the A end and the current differential relay 53B at the B end, the transmission route may be switched. This is because the transmission time difference may be changed.

  In step S711, the phase difference calculation unit 75 of the A-terminal current differential relay 53A determines the specific point voltage Vs based on its own current data and voltage data and the specific point voltage Vsf based on the other-end current data and voltage data. The phase difference φ is calculated. Here, the specific point is an intermediate point between the A end and the B end. Then, the synchronization processing unit 73 corrects the specific time interval Ts by adding or subtracting the time t ′ corresponding to the phase difference φ to the current specific time interval Ts. A more detailed correction method will be described later with reference to FIG.

  Thereafter, steps S706 to S711 are repeated. Therefore, step S708 is executed using the specific time interval Ts corrected in step S711. Further, when the power transmission line has not failed and the circuit breaker between both ends of the power transmission line is not opened (NO in step S710), the specific time interval Ts is obtained by repeatedly executing step S711. Is continuously corrected.

  On the other hand, when a failure occurs in the transmission line or a breaker between both ends of the transmission line is opened (YES in step S710), step S711 for correcting the specific time interval Ts is not executed. The synchronization processing in step S708 is continued using the specific time interval Ts corrected immediately before the occurrence of a power transmission line failure or immediately before opening of the circuit breaker or the like.

  Here, the failure of the power transmission line 50 may be detected by the current differential relays 53A and 53B, or may be detected by another method. For example, a sudden change in the terminal current may be detected by a current change width relay, or a failure detection signal may be received from another protection relay. The switching states of the circuit breakers 68A and 68B and the disconnecting switch (not shown) indicate that the current differential relays 53A and 53B receive signals representing the switching states output from the circuit breakers 68A and 68B and the disconnecting switch. May be detected.

  According to the above procedure shown in FIG. 12, even when a failure has occurred in the transmission line or when a circuit breaker provided between both ends of the transmission line is opened, the sampling synchronization process is more accurate than in the past. Can be realized. In the above description, the A-terminal current differential relay 53A is on the slave side, and the A-terminal current differential relay 53A adjusts its own sampling timing. Conversely, the B-terminal current differential relay 53B may adjust its own sampling timing.

  FIG. 13 is a diagram for explaining the procedure of step S711 in FIG. 12 in more detail. FIGS. 13A to 13D are based on FIGS. 6A and 6B.

  First, referring to FIG. 6A, the time interval T1 between the transmission time t1 and the reception time t3 of the timing signal at the A end, and the time interval T2 between the transmission time t2 and the reception time t4 of the timing signal at the B end. And are equal. At this time, when the specific point voltage Vs based on the voltage data and current data at the A end and the specific point voltage Vsf based on the voltage data and current data at the B end are compared, the specific point voltage Vsf is greater than the specific point voltage Vs. Suppose that the phase difference φ is advanced. In this case, if the time corresponding to the phase difference φ is t, the transmission time from the A end to the B end via the communication path is longer by 2 × t than the transmission time from the B end to the A end. In this specification, t (that is, 1/2 of the transmission time difference) in this case is referred to as a specific time interval Ts.

  Therefore, in the case of FIG. 6A, as shown in FIG. 6B, the time interval T1 between the transmission time and the reception time of the timing signal at the A end (corresponding to T3 in FIG. 6B). A value obtained by adding 2 × Ts (corresponding to 2 × t in FIG. 6B) and a time interval T2 (corresponding to T4 in FIG. 6B) between the transmission time and the reception time of the timing signal at the B end. Sampling synchronization can be realized by controlling the sampling timing at the A-end or B-end so that they are equal. However, even if correction is made so that T1 + 2 × Ts = T2 due to the influence of measurement error, jitter, wander, fluctuations in device characteristics (for example, fluctuations in the clock, etc.), signal fluctuations, etc., it is completely normal. Sampling synchronization is never realized continuously. In addition, when an abnormality occurs in the communication path between the A-end transmission apparatus and the B-end transmission apparatus, the transmission route may be switched, and in this case, there is a possibility that a change occurs in the transmission time difference between upstream and downstream. Therefore, the accuracy of sampling synchronization is improved by continuously correcting the specific time interval Ts. Hereinafter, this will be described in detail with reference to FIGS.

  Referring to FIG. 13A, it is assumed that the sampling timing at the A end or B end is adjusted so that T1 + 2 × Ts = T2 as in the case of FIG. 6B. In this case, when the specific point voltage Vs based on the voltage data and current data at the A end and the specific point voltage Vsf based on the voltage data and current data at the B end are compared, the specific point voltage Vsf is the specific point voltage Vsf. It is assumed that the phase difference is advanced by φ. If the time corresponding to the phase difference φ is t ′, this means that the sampling timing at the B end is delayed by t ′ from the sampling timing at the A end.

  Therefore, as shown in FIG. 13B, sampling synchronization can be realized by controlling the sampling timing at the A end or B end so that T1 + 2 × Ts + 2 × t ′ = T2. In other words, sampling synchronization is realized by correcting the specific time interval Ts so as to add the time t ′ (that is, by correcting Ts ′ = Ts + t ′ when the corrected specific time interval is Ts ′). it can.

  Referring to FIG. 13C, it is assumed that the sampling timing at the A end or B end is adjusted so that T1 + 2 × Ts = T2 as in the case of FIG. 6B. In this case, when the specific point voltage Vs based on the voltage data and current data at the A end is compared with the specific point voltage Vsf based on the voltage data and current data at the B end, the case of FIG. Conversely, it is assumed that the specific point voltage Vsf is delayed from the specific point voltage Vs by the phase difference φ. If the time corresponding to the phase difference φ is t ′, this means that the sampling timing at the B end is earlier than the sampling timing at the A end by t ′.

  Therefore, as shown in FIG. 13D, sampling synchronization can be realized by controlling the sampling timing at the A end or B end so that T1 + 2 × Ts−2 × t ′ = T2. In other words, sampling synchronization is performed by correcting the specific time interval Ts so as to subtract the time t ′ (that is, by correcting Ts ′ = Ts−t ′ if the specific time interval after correction is Ts ′). Can be realized.

  In the case of a phase relationship opposite to that in the above example, those skilled in the art can easily understand that if the A end and the B end are interchanged in the above description, the above description is almost as it is. Let's go.

[Sampling synchronization procedure-Part 3]
FIG. 14 is a flowchart showing still another sampling synchronization procedure. The sampling synchronization procedure of FIG. 14 shows a modification of the sampling synchronization procedure of FIG. 12, and is characterized in that only the synchronization processing based on the voltage phase difference is performed during normal transmission lines.

  Referring to FIG. 14, in the initial state, it is assumed that no failure has occurred in power transmission line 50 and the circuit breaker provided between the terminals is in the on state.

  First, in step S801, the transmitter 131_1 of the A-terminal current differential relay 53A transmits a timing signal together with its own current data and voltage data to the B-terminal current differential relay 53B. Similarly, the transmitter 131_1 of the B-end current differential relay 53B transmits a timing signal together with its own-end current data and voltage data to the A-end current differential relay 53A.

  In the next step S802, the receiver 131_2 of the A-terminal current differential relay 53A receives the timing signal together with the current data and voltage data from the other end. Similarly, the receiver 131_2 of the B-terminal current differential relay 53A receives the timing signal together with the current data and voltage data from the other end.

  Furthermore, each current differential relay 53A, 53B calculates the time interval between the transmission time of the timing signal from its own end and the reception time of the timing signal from the other end. The current differential relays 53A and 53B transmit the calculated time signal transmission / reception time intervals to each other. The calculation of the time interval and the transmission of the calculation result may be, for example, about once per cycle.

  In next step S803, the synchronization processing unit 73 of the A-terminal current differential relay 53A transmits the time interval T1 between the transmission time and the reception time of the timing signal on the own end side, and the transmission of the timing signal on the other end side. The current and voltage sampling times in the A / D converter 110 of the A-terminal current differential relay 53A are controlled so that the time interval T2 between the time and the reception time is equal.

  As a result, when the time interval T1 is equal to the time interval T2 (YES in step S804), in the next step S805, the synchronization processing unit 73 of the A-terminal current differential relay 53A performs the above-described steps S101 to S101 in FIG. As described in S107, the phase difference φ between the specific point voltage Vs based on the current data and voltage data at its own end and the specific point voltage Vsf based on the current data and voltage data at the other end is calculated. Here, the specific point is an intermediate point between the A end and the B end. Then, the synchronization processing unit 73 stores the time corresponding to the phase difference φ as a specific time interval Ts in a memory (for example, the RAM 122 or the ROM 123 in FIG. 2).

  Thereafter, in step S806, the synchronization processing unit 73 controls the current and voltage sampling timings on the own end side so that the time t corresponding to the phase difference φ between the specific point voltages Vs and Vsf becomes zero. When the power transmission line 50 is normal, the sampling synchronization process based on this voltage phase difference is repeated.

  Next, it is assumed that a failure of the power transmission line 50 is detected or the circuit breakers 68A and 68B between the A end and the B end are opened (YES in step S807). If a power transmission line failure or an open circuit breaker occurs (YES in step S807), the synchronization processing unit 73 cannot continue the timing synchronization process based on the voltage phase difference, so the timing signal transmission time and reception time Switch to the timing synchronization process based on the time interval.

  Specifically, in step S808, the transmitter 131_1 of the A-terminal current differential relay 53A transmits a timing signal together with its own current data and voltage data to the B-terminal current differential relay 53B. Similarly, the transmitter 131_1 of the B-end current differential relay 53B transmits a timing signal together with its own-end current data and voltage data to the A-end current differential relay 53A.

  In the next step S809, the receiver 131_2 of the A-terminal current differential relay 53A receives the timing signal together with the current data and voltage data from the other end. Similarly, the receiver 131_2 of the B-terminal current differential relay 53A receives the timing signal together with the current data and voltage data from the other end. Similarly to step S802, each of the current differential relays 53A and 53B calculates a time interval between the transmission time of the timing signal from its own end and the reception time of the timing signal from the other end. The current differential relays 53A and 53B transmit the calculated time signal transmission / reception time intervals to each other.

  In the next step S810, the synchronization processing unit 73 of the A-terminal current differential relay 53A transmits the time interval T1 between the timing signal transmission time and the reception time on the own end side, and the transmission of the timing signal on the other end side. Sampling of current and voltage in the A / D converter 110 of the A-terminal current differential relay 53A so that the time interval T2 between the time and the reception time differs by twice the specific time interval Ts obtained in step S805. Control the time.

  As described above, even when a power transmission line failure occurs or the circuit breaker is opened between both ends, it is possible to realize sampling synchronization processing with higher accuracy than in the past. In the above description, the A-terminal current differential relay 53A is on the slave side, and the A-terminal current differential relay 53A adjusts its own sampling timing. Conversely, the B-terminal current differential relay 53B may adjust its own sampling timing.

<Modification of Embodiment 1>
In the above description, the intermediate point 57 on the transmission line 50 is set as a specific point, and the voltage at the specific point is calculated from each terminal voltage and terminal current. An arbitrary point can be set as the specific point 67. Hereinafter, description will be given with reference to the drawings. For calculation accuracy, the specific point 67 is preferably an intermediate point.

  FIG. 15 is an equivalent circuit diagram of a positive phase circuit of a power transmission system to which the sampling synchronization processing according to the modification of the first embodiment is applied. The equivalent circuit diagram of FIG. 15 is a modification of the equivalent circuit diagram of FIG. 7. Therefore, the same reference numerals are assigned to portions common to FIG. 7, and description thereof is not repeated. Note that the position of the specific point 67 on the power transmission line 50 is x = m (0 ≦ m ≦ 1). In the following description, the A end is referred to as a self end, and the B end is referred to as a counterpart end.

Since the power transmission line 50 is simulated by a π-type circuit, the ground capacity is collected at both ends of the power transmission line. Therefore, each of the ground capacity gathered at the own end and the ground capacity gathered at the other end is ½ of the entire capacity C of the transmission line 50 regardless of the length from the own end to the specific point 67. . Therefore, the charging current Ic flowing at its own end is
Ic = jω (C / 2) * V1 (16)
It is represented by The voltage Vf at the specific point 67 can be calculated using a value (I1−Ic) obtained by subtracting the charging current Ic from the own end current I1 and the own end voltage V1. The voltage Vf at the specific point 67 is
Vf = V1-Z1 * m * (I1-Ic) (17)
It is represented by The second term on the right side of the above equation (12) indicates the voltage drop caused by the transmission line 50 from the own end to the specific point 67.

Similarly, considering that the other end has 1/2 of the ground capacity C of the entire line, the charging current Ics flowing through the other end is
Ics = jω (C / 2) * Vs1 (18)
It is represented by The voltage at the specific point 67 can be calculated using the value (Is1-Ics) obtained by subtracting the charging current Ics from the counterpart end current Is1 and the counterpart end voltage Vs1. Specifically, the midpoint voltage Vsf is
Vsf = Vs1-Z1 * (1-m) * (Is1-Ics) (19)
It is represented by The second term on the right side of the above equation (14) indicates the voltage drop caused by the transmission line 50 from the other end to the specific point 67.

  Accordingly, the sampling timing is based on the time t corresponding to the phase difference φ between the voltage Vf at the specific point 67 expressed by the above equation (17) and the voltage Vsf at the specific point 67 expressed by the above equation (19). Can be synchronized.

Embodiment 2. FIG.
In the first embodiment, the transmission line is simulated by a π-type circuit, the charging current is calculated using the terminal voltage of the transmission line when there is no system failure, and the terminal current and the terminal voltage with which the charging current is compensated are calculated. Used to calculate the midpoint voltage. Then, the phase difference φ between the intermediate point voltage Vf based on the voltage and current at the A end and the intermediate point voltage Vsf based on the voltage and current at the B end is calculated, and sampling is performed based on the time t corresponding to the calculated phase difference φ. The time was corrected.

  In the second embodiment, the transmission line circuit is simulated by a T-shaped circuit. The T-type circuit is a model in which a capacitor corresponding to a ground capacitance C that generates a charging current is provided at an intermediate point of the transmission line, and this capacitor is sandwiched by 1/2 of the line impedance of the transmission line. The capacitor point to which the capacitor is connected is not limited to the intermediate point, but may be any point between the A end and the B end, but the intermediate point is preferable in terms of accuracy.

  In the second embodiment, the voltage at the B end as the specific point is further calculated based on the current and voltage at the A end, and the phase difference between the calculated B end voltage and the actual B end voltage is calculated. By simulating the transmission line with a T-shaped circuit, the charging current due to the ground capacity can be taken into account in addition to the voltage drop caused by the load current flowing through the transmission line. be able to.

[When simulating a transmission line with a single T-shaped circuit]
FIG. 16 is an equivalent circuit diagram of a positive phase circuit of a power transmission system to which the sampling synchronization processing according to the second embodiment is applied. Referring to FIG. 16, the positive phase voltage at the A terminal is V1, and the positive phase current at the A terminal is I1. Similarly, the positive phase voltage at the B end is Vs1, and the positive phase current at the B end is Is1.

  Let C be the total amount of ground capacity in the entire transmission line 50. In the T-type circuit, a capacitor corresponding to the ground capacitance C is connected to the intermediate point 57. The capacitor point to which the capacitor is connected is not limited to the intermediate point, but may be any point between the A end and the B end, but the intermediate point is preferable in terms of accuracy.

  Further, if the positive phase impedance of the entire transmission line 50 is Z1, the line impedance from the A end of the transmission line 50 to the intermediate point 57 is represented by Z1 / 2, and the line from the B end of the transmission line 50 to the intermediate point 57 The impedance is represented by Z1 / 2. A T-type circuit 80 is constituted by the capacitor corresponding to the ground capacitance C and the two line impedances Z1 / 2.

  FIG. 17 is a flowchart illustrating a procedure of sampling synchronization processing according to the second embodiment. Hereinafter, the procedure of the sampling synchronization process will be described mainly with reference to FIGS. 9, 16, and 17. In the following description, the A end is referred to as a self end, and the B end is referred to as a counterpart end.

  First, the A / D conversion unit 110 in FIG. 9 generates current data I1 and voltage data V1 by sampling its own current and voltage (step S201). The receiver 131_2 receives current data Is1 and voltage data Vs1 that are sampling values of the current and voltage of the other end (step S202). If only the phase difference between the voltages at both ends is calculated and the current data Is1 at the other end is not required, only the voltage data Vs1 may be received.

Next, the voltage calculation unit 74 calculates the voltage Vt at the intermediate point 57 (also referred to as a capacitor point) using the self-end voltage V1 and the self-end current I1 (step S203). Specifically, the voltage Vt is
Vt = V1- (Z1 / 2) * I1 (20)
It is represented by The second term on the right side of the above equation (20) indicates the voltage drop caused by the transmission line 50 from the own end to the intermediate point 57.

Next, the voltage calculation unit 74 calculates the charging current Ict using the capacitor point voltage Vt (step S204). Specifically, the charging current Ict is
Ict = jωC * Vt (21)
It is represented by

Next, the voltage calculation unit 74 calculates the counterpart voltage Vs1 ′ using the value (I1−Ict) obtained by subtracting the charging current Ict from the local current I1 and the voltage Vt at the capacitor point (step S205). ). Specifically, the counterpart voltage Vs1 ′ is
Vs1 '= Vt- (Z1 / 2) * (I1-Ict) (22)
It is represented by The second term on the right side of the above equation (22) indicates a voltage drop caused by the transmission line 50 from the intermediate point 57 to the other end. That is, the synchronization processing unit 73 controls the current and voltage sampling times at its own end so that the time t corresponding to the phase difference φ becomes zero. Note that the sampling synchronization method described in FIG. 14 can also be applied to the case of this embodiment.

  Next, the phase difference calculator 75 calculates the phase difference φ between the actually detected counterpart voltage Vs1 and the calculated counterpart voltage Vs1 '(step S206). The phase difference calculation unit 75 obtains a delay time (or advance time) corresponding to the phase difference φ and outputs it to the synchronization processing unit 73. The synchronization processing unit 73 corrects the sampling time by the delay time or advance time (step S207).

  As described above, by simulating the transmission line with a T-shaped circuit, the charging current due to the ground capacity can be taken into account along with the voltage drop caused by the load current flowing through the transmission line. Synchronization can be realized. Furthermore, the accuracy of sampling synchronization can be increased by increasing the number of stages of the T-type circuit.

[When simulating a transmission line with a two-stage T-shaped circuit]
FIG. 18 is an equivalent circuit diagram of a positive phase circuit of a power transmission system when a transmission line is simulated by a two-stage T-shaped circuit.

  Referring to FIG. 18, the first stage T-shaped circuit 81 includes a capacitor having a ground capacitance of C / 2 provided at a first capacitor point 56 which is a point of x = 1/4 of the transmission line, and a capacitor point thereof. Line impedance of a size of Z1 / 4 connected to both sides of each. The T-type circuit 82 in the second stage includes a capacitor having a ground capacitance of C / 2 provided at the second capacitor point 58 that is a point of x = 3/4 of the transmission line, and both sides of the capacitor point. Line impedance of the size of Z1 / 4 connected. The voltage at the first capacitor point 56 is Vt, and the charging current at the first capacitor point 56 is Ict. The voltage at the second capacitor point 58 is Vt ', and the charging current at the second capacitor point 58 is Ict'. Note that the line lengths of the two-stage T-shaped circuit need not be the same. When the line lengths of the two-stage T-type circuits are different, the ground capacitance proportional to the line length of each T-type circuit may be at the midpoint of each line.

  FIG. 19 is a flowchart showing a sampling synchronization procedure of the power transmission system simulated by the equivalent circuit of FIG. Hereinafter, the procedure of the sampling synchronization processing will be described mainly with reference to FIGS. 9, 18, and 19. In the following description, the A end is referred to as a self end, and the B end is referred to as a counterpart end.

  The A / D conversion unit 110 in FIG. 9 generates current data I1 and voltage data V1 by sampling its own current and voltage (step S301). The receiver 131_2 receives current data Is1 and voltage data Vs1 that are sampling values of the current and voltage of the other end (step S302). If only the phase difference between the voltages at both ends is calculated and the current data Is1 at the other end is not required, only the voltage data Vs1 may be received.

Next, the voltage calculation unit 74 calculates the voltage Vt at the first capacitor point (x = 1/4) using the self-end voltage V1 and the self-end current I1 (step S303). Specifically, the voltage Vt is
Vt = V1- (Z1 / 4) * I1 (23)
It is represented by The second term on the right side of the above equation (23) indicates the voltage drop by the power transmission line 50 from the own end to the first capacitor point 56.

Next, the voltage calculation unit 74 calculates the charging current Ict at the first capacitor point 56 using the voltage Vt of the above equation (23) (step S304). Specifically, the charging current Ict is
Ict = jω (C / 2) * Vt (24)
It is represented by

Next, the voltage calculation unit 74 uses the value (I1−Ict) obtained by subtracting the charging current Ict from the self-end current I1 and the voltage Vt of the first capacitor point 56 to use the second capacitor point 58 ( The voltage Vt ′ of x = 3/4) is calculated (step S305). Specifically, the voltage Vt ′ is
Vt ′ = Vt − ((Z1 / 4) + (Z1 / 4)) * (I1−Ict)
= Vt- (Z1 / 2) * (I1-Ict) (25)
It is represented by The second draft on the right side of the above equation (25) shows the voltage drop in the transmission line 50 between the first capacitor point 56 and the second capacitor point 58.

Next, the voltage calculation unit 74 calculates the charging current Ict ′ at the second capacitor point 58 using the voltage Vt ′ of the above equation (25) (step S306). Specifically, the charging current Ict ′ is
Ict ′ = jω (C / 2) * Vt ′ (26)
It is represented by

Next, the voltage calculation unit 74 uses the value obtained by subtracting the charging currents Ict and Ict ′ from the self-end current I1 (I1−Ict−Ict ′) and the voltage Vt ′ at the second capacitor point, An end voltage Vs1 ′ is calculated (step S307). Specifically, the voltage Vs1 ′ at the other end is
Vs1 ′ = Vt ′ − (Z1 / 4) * (I1−Ict−Ict ′) (27)
It is represented by The second term on the right side of the above equation (27) indicates the voltage drop caused by the transmission line 50 from the second capacitor point 58 to the other end.

  Next, the phase difference calculator 75 calculates the phase difference φ between the actually detected counterpart voltage Vs1 and the calculated counterpart voltage Vs1 '(step S308). Further, the phase difference calculation unit 75 obtains a delay time (or advance time) corresponding to the phase difference φ and outputs it to the synchronization processing unit 73. The synchronization processing unit 73 corrects the sampling time by the delay time or the advance time (step S309). That is, the synchronization processing unit 73 controls the current and voltage sampling times at its own end so that the time t corresponding to the phase difference φ becomes zero. Note that the sampling synchronization method described in FIG. 14 can also be applied to the case of this embodiment.

  In this way, by increasing the number of stages of the T-type circuit, it is possible to approach a distributed constant line that simulates an actual power transmission line, so that the accuracy of sampling synchronization can be further increased. Further, in the second embodiment, since the charging current can be compensated based on the voltage difference between both ends of the transmission line 50, the sampling synchronization can be continuously corrected in a state where there is no failure in the transmission line. When a system failure occurs, sampling synchronization processing is performed using the result of the most recent synchronization processing in a state where there is no system failure (that is, by pre-holding).

[Modification of Embodiment 2]
In the above, the voltage calculation unit 71 of the current differential relay 53A calculates the voltage Vs1 ′ at the other end using the current data I1 and the voltage data V1 at the own end of the transmission line, and the phase difference calculation unit 72 calculates the calculation result. And the phase difference φ between the actual voltage value Vs1 at the other end. On the contrary, the voltage calculation unit 71 of the current differential relay 53A calculates its own voltage V1 ′ using the current data Is1 and voltage data Vs1 of the other end of the transmission line, and the phase difference calculation unit 72 The phase difference φ between the calculation result and the actual voltage value V1 at the end of the transmission line may be calculated. Even in this way, the self-sampling timing can be adjusted based on the time t corresponding to the phase difference φ, so that sampling synchronization can be executed with higher accuracy than in the prior art.

Embodiment 3 FIG.
In the second embodiment, the B-end voltage is calculated using the A-end current and voltage, and the calculated B-end voltage is compared with the actually detected B-end voltage. In the third embodiment, as described with reference to FIGS. 7 and 10 of the first embodiment, the midpoint voltage Vf is calculated using the current and voltage at the A end, and the midpoint is calculated using the current and voltage at the B end. The voltage Vsf is calculated. Then, sampling synchronization processing is performed based on the calculated phase difference between the intermediate point voltages Vf and Vsf.

  The intermediate point is not limited to a specific point arbitrarily defined between the A end and the B end. In this case, the intermediate point voltage Vf is referred to as a first specific point voltage Vf, and the intermediate point voltage Vsf is referred to as a second specific point voltage Vsf. Further, the power transmission line 50 is simulated by a two-stage T-shaped circuit as in FIG. 18 of the second embodiment. As a result, the accuracy can be improved as compared with the case of the first embodiment.

  FIG. 20 is an equivalent circuit diagram of a positive phase circuit of a power transmission system to which the sampling synchronization processing of the third embodiment is applied. The equivalent circuit diagram of FIG. 20 corresponds to the equivalent circuit diagram of FIG. 18, and the transmission line 50 is simulated by two-stage T-shaped circuits 81 and 82. The voltage at the first capacitor point 56 is Vt, and the charging current at the first capacitor point 56 is Ict. The voltage at the second capacitor point 58 is Vts, and the charging current at the second capacitor point 58 is Icts. Also, the voltage at the intermediate point 57 based on the current A1 at the A end and the voltage V1 is Vf, and the voltage at the intermediate point 57 based on the current Is1 and the voltage Vs1 at the B end is Vsf.

  FIG. 21 is a flowchart showing a sampling synchronization procedure of the power transmission system simulated by the equivalent circuit of FIG. Hereinafter, the procedure of the sampling synchronization process will be described mainly with reference to FIG. 9, FIG. 20, and FIG. In the following description, the A end is referred to as a self end, and the B end is referred to as a counterpart end.

  First, the A / D conversion unit 110 in FIG. 9 generates current data I1 and voltage data V1 by sampling the current and voltage at its own end (step S401).

Next, the voltage calculation unit 74 calculates the voltage Vt at the first capacitor point (x = 1/4) using the self-end voltage V1 and the self-end current I1 (step S402). Specifically, the voltage Vt is
Vt = V1- (Z1 / 4) * I1 (28)
It is represented by The second term on the right side of the above equation (28) represents a voltage drop by the power transmission line 50 from the A end to the first capacitor point 56.

Next, the voltage calculation unit 74 calculates the charging current Ict at the first capacitor point 56 using the voltage Vt of the above equation (28) (step S403). Specifically, the charging current Ict is
Ict = jω (C / 2) * Vt (29)
It is represented by

Next, the voltage calculation unit 74 calculates the midpoint voltage Vf using the value (I1−Ict) obtained by subtracting the charging current Ict from the self-end current I1 and the voltage Vt of the first capacitor point 56. (Step S404). Specifically, the midpoint voltage Vf is
Vf = Vt- (Z1 / 4) * (I1-Ict) (30)
It is represented by The second term on the right side of the above equation (30) represents a voltage drop caused by the transmission line 50 from the first capacitor point 56 to the intermediate point 57.

  Next, the receiver 131_2 receives the current and voltage sampling values (that is, the current data Is1 and the voltage data Vs1) at the other end (step S405). The received current data Is1 and voltage data Vs1 are taken into the received data processing unit 72. Note that step S405 may be executed before step S402. Steps S402 to S404 may be executed in parallel with steps S406 to S408.

Next, the voltage calculation unit 74 calculates the voltage Vts at the second capacitor point (x = 3/4) using the counterpart terminal voltage Vs1 and the counterpart terminal current Is1 (step S406). Specifically, the voltage Vts is
Vts = Vs1- (Z1 / 4) * Is1 (31)
It is represented by The second term on the right side of the above equation (31) represents a voltage drop by the power transmission line 50 from the B end to the second capacitor point 58.

Next, the voltage calculation unit 74 calculates the charging current Icts at the second capacitor point 58 using the voltage Vts of the above equation (31) (step S407). Specifically, the charging current Icts is
Icts = jω (C / 2) * Vts (32)
It is represented by

Next, the voltage calculation unit 74 calculates the midpoint voltage Vsf using the value (Is1−Icts) obtained by subtracting the charging current Icts from the phase point end current Is1 and the voltage Vts of the second capacitor point 58. (Step S408). Specifically, the midpoint voltage Vsf is
Vsf = Vts− (Z1 / 4) * (Is1−Icts) (33)
It is represented by The second term on the right side of the above equation (33) represents a voltage drop caused by the transmission line 50 from the second capacitor point 58 to the intermediate point 57.

  Next, the phase difference calculation unit 75 calculates a phase difference φ between the midpoint voltages Vs and Vsf (step S409). Further, the phase difference calculation unit 75 calculates a delay time (or advance time) corresponding to the calculated phase difference φ and outputs it to the synchronization processing unit 73. The synchronization processing unit 73 corrects the sampling time by the delay time or advance time (step S410). That is, the synchronization processing unit 73 controls the current and voltage sampling times at its own end so that the time t corresponding to the phase difference φ becomes zero. Note that the sampling synchronization method described in FIG. 14 can be applied to this embodiment.

  In the first embodiment, there is a possibility that the error cannot be ignored when the load current increases. However, in the third embodiment, the error is reduced by configuring each terminal to the intermediate point 57 using a T-type circuit. can do. In addition, if the line from each terminal to the intermediate point 57 is configured by a two-stage T-shaped circuit, the equivalent circuit further approaches the distributed constant, so that the accuracy of sampling synchronization can be further improved.

  FIG. 22 is an equivalent circuit diagram of the positive phase circuit of the power transmission system when each terminal to the middle point is simulated by a two-stage T-shaped circuit.

  Referring to FIG. 22, in the transmission line from the A end to intermediate point 57, the first stage T-shaped circuit 83 is connected to the ground provided at first capacitor point 91 which is the point of x = 1/8 of the transmission line. A capacitor having a capacitance of C / 4 and a line impedance having a size of Z1 / 8 connected to both sides of the capacitor point are included. The T-type circuit 84 in the second stage includes a capacitor having a ground capacitance of C / 4 provided at the second capacitor point 93, which is a point of x = 3/8 of the transmission line, and both sides of the capacitor point. And connected line impedance of the size of Z1 / 8. The voltage at the first capacitor point 91 is Vp, and the charging current at the first capacitor point 91 is Icp. The voltage at the second capacitor point 93 is Vp ′, and the charging current at the second capacitor point 93 is Icp ′.

  Similarly, in the transmission line from the B end to the intermediate point 57, the T-type circuit 86 of the first stage has a ground capacitance provided at the third capacitor point 96 which is a point of x = 7/8 of the transmission line. 4 capacitors and a line impedance having a size of Z1 / 8 connected to both sides of the capacitor point. The T-type circuit 85 in the second stage includes a capacitor having a ground capacitance of C / 4 provided at the fourth capacitor point 94 which is a point of x = 5/8 of the transmission line, and both sides of the capacitor point. And connected line impedance of the size of Z1 / 8. The voltage at the third capacitor point 96 is Vps, and the charging current at the third capacitor point 96 is Icps. The voltage at the fourth capacitor point 94 is Vps ′, and the charging current at the fourth capacitor point 94 is Icps ′.

  FIG. 23 is a flowchart showing a sampling synchronization procedure of the power transmission system simulated by the equivalent circuit of FIG. Hereinafter, the procedure of the sampling synchronization processing will be described mainly with reference to FIG. 9, FIG. 22, and FIG. In the following description, the A end is referred to as a self end, and the B end is referred to as a counterpart end.

  First, the A / D conversion unit 110 in FIG. 9 generates current data I1 and voltage data V1 by sampling its own current and voltage (step S501).

Next, the voltage calculation unit 74 calculates the voltage Vp of the first capacitor point 91 (x = 1/8) using the self-end voltage V1 and the self-end current I1 (step S502). Specifically, the voltage Vp is
Vp = V1- (Z1 / 8) * I1 (34)
It is represented by The second term on the right side of the above equation (34) represents a voltage drop by the power transmission line 50 from the A end to the first capacitor point 91.

Next, the voltage calculation unit 74 calculates the charging current Icp at the first capacitor point 91 using the voltage Vp of the above equation (34) (step S503). Specifically, the charging current Icp is
Icp = jω (C / 4) * Vp (35)
It is represented by

Next, the voltage calculation unit 74 uses the value (I1−Icp) obtained by subtracting the charging current Icp from the self-end current I1 and the voltage Vp at the first capacitor point 91 to use the second capacitor point 93. A voltage Vp ′ of (x = 3/8) is calculated (step S504). Specifically, the voltage Vp ′ is
Vp ′ = Vp− (Z1 / 4) * (I1−Icp) (36)
It is represented by The second term on the right side of the above equation (36) represents the voltage drop by the power transmission line 50 from the first capacitor point 91 to the second capacitor point 93.

Next, the voltage calculation unit 74 calculates the charging current Icp ′ at the second capacitor point 93 using the voltage Vp ′ of the above equation (36) (step S505). Specifically, the charging current Icp ′ is
Icp ′ = jω (C / 4) * Vp ′ (37)
It is represented by

Next, the voltage calculation unit 74 uses the value obtained by subtracting the charging currents Icp and Icp ′ from the current I1 (I1−Icp−Icp ′) and the voltage Vp ′ at the second capacitor point, The point voltage Vf is calculated (step S506). Specifically, the midpoint voltage Vf is
Vf = Vp ′ − (Z1 / 8) * (I1−Icp−Icp ′) (38)
It is represented by The second term on the right side of the above equation (38) represents a voltage drop caused by the transmission line 50 from the second capacitor point 93 to the intermediate point 57.

  Next, the receiver 131_2 receives sampling values of the current and voltage at the other end (that is, current data Is1 and voltage data Vs1) (step S507). The received current data Is1 and voltage data Vs1 are taken into the received data processing unit 72. Note that step S507 may be executed before step S502. Further, steps S502 to S506 may be executed in parallel with steps S508 to S512.

Next, the voltage calculation unit 74 calculates the voltage Vps at the third capacitor point (x = 7/8) using the counterpart terminal voltage Vs1 and the counterpart terminal current Is1 (step S508). Specifically, the voltage Vps is
Vps = Vs1- (Z1 / 8) * Is1 (39)
It is represented by The second term on the right side of the above equation (39) represents a voltage drop by the power transmission line 50 from the B end to the third capacitor point 96.

Next, the voltage calculation unit 74 calculates the charging current Icps at the third capacitor point 96 using the voltage Vps of the above equation (39) (step S509). Specifically, the charging current Icps is
Icps = jω (C / 4) * Vps (40)
It is represented by

Next, the voltage calculation unit 74 uses the value (Is1−Icps) obtained by subtracting the charging current Icps from the counterpart terminal current Is1 and the voltage Vps at the third capacitor point 96 to use the fourth capacitor point 94. The voltage Vps ′ at (x = 5/8) is calculated (step S510). Specifically, the voltage Vps ′ is
Vps ′ = Vps− (Z1 / 4) * (Is1−Icps) (41)
It is represented by The second term on the right side of the above equation (41) represents a voltage drop caused by the transmission line 50 from the third capacitor point 96 to the fourth capacitor point 94.

Next, the voltage calculation unit 74 calculates the charging current Icps ′ at the fourth capacitor point 94 using the voltage Vps ′ of the above equation (41) (step S511). Specifically, the charging current Icps ′ is
Icps ′ = jω (C / 4) * Vps ′ (42)
It is represented by

Next, the voltage calculation unit 74 uses a value obtained by subtracting the charging currents Icps and Icps ′ from the counterpart terminal current Is1 (Is1−Icps−Icps ′) and the voltage Vps ′ at the fourth capacitor point 94, The midpoint voltage Vsf is calculated (step S512). Specifically, the midpoint voltage Vsf is
Vsf = Vps ′ − (Z1 / 8) * (Is1−Icps−Icps ′) (43)
It is represented by The second term on the right side of the above equation (43) represents a voltage drop caused by the transmission line 50 from the fourth capacitor point 94 to the intermediate point 57.

  Next, the phase difference calculator 75 calculates the phase difference φ between the midpoint voltages Vs and Vsf (step S513). Further, the phase difference calculation unit 75 calculates a delay time (or advance time) corresponding to the calculated phase difference φ and outputs it to the synchronization processing unit 73. The synchronization processing unit 73 corrects the sampling time by the delay time or advance time (step S514). That is, the synchronization processing unit 73 controls the current and voltage sampling times at its own end so that the time t corresponding to the phase difference φ becomes zero. Note that the sampling synchronization method described in FIG. 14 can also be applied to the case of this embodiment.

  By increasing the number of stages of the T-type circuit as described above, the equivalent circuit of the transmission line 50 becomes closer to the distributed constant circuit, so that the accuracy of sampling synchronization can be further increased. Furthermore, the sampling synchronization can be continuously corrected under the condition that there is no system failure. Even if the lines from each terminal to the intermediate point are simulated by three or more T-shaped circuits, the sampling synchronization processing can be performed in the same manner as described above.

Embodiment 4 FIG.
Although the case where the power transmission line has two terminals has been described in the first to third embodiments, the case where the power transmission line has three or more terminals will be described in the fourth embodiment.

[When the power transmission line has 3 terminals]
FIG. 24 is a system diagram of a three-terminal power transmission line having a back power supply at each terminal. In the power transmission line of FIG. 24, the A end is connected to the branch point 200 via the power transmission line 201, the B end is connected to the branch point 200 via the power transmission line 202, and the C end is connected to the branch point 200 and the power transmission line 203. Connected through. Back power supplies 52A, 52B, and 52C are connected to the A end, B end, and C end of the power transmission line, respectively.

  A current transformer CT1 is provided at the A end, and a voltage transformer VT1 is provided at the A-end bus 51A. A current transformer CT2 is provided at the B end, and a voltage transformer VT2 is provided at the bus 51B at the B end. A current transformer CT3 is provided at the C terminal, and a voltage transformer VT3 is provided at the C-terminal bus 51C.

  Current differential relays 53A, 53B, and 53C are installed at the A end, the B end, and the C end, respectively. Each current differential relay 53 is connected to its own voltage transformer VT and current transformer CT. The current differential relays 53A, 53B, 53C are connected to each other via the communication paths 54, 54B, 54C, and exchange the detected current data and voltage data with each other.

  FIG. 25 is an equivalent circuit diagram of the positive phase circuit of the power transmission system of FIG. Each of the transmission lines 201, 202, 203 is simulated by T-type circuits 204, 205, 206, respectively.

  In the T-type circuit 204, a capacitor having the size of the ground capacitance CA of the transmission line 201 is provided at an intermediate point (also referred to as a first capacitor point) 211 of the transmission line 201. On both sides of the intermediate point 211, impedances each having a value half that of the positive phase impedance ZA1 of the transmission line 201 are connected.

  Similarly, in the T-type circuit 205, a capacitor having the size of the ground capacitance CB of the power transmission line 202 is provided at an intermediate point (also referred to as a second capacitor point) 212 of the power transmission line 202. On both sides of the intermediate point 212, impedances each having a value half the positive phase impedance ZB1 of the transmission line 202 are connected.

  Similarly, in the T-type circuit 206, a capacitor having the size of the ground capacitance CC of the power transmission line 203 is provided at an intermediate point (also referred to as a third capacitor point) 213 of the power transmission line 203. On both sides of the intermediate point 213, an impedance having a value half the positive phase impedance ZC1 of the transmission line 203 is connected.

  In a specific sampling synchronization process, the sample timing of the other two terminals is synchronized with the sample timing of one of the three terminals. Hereinafter, a case where the sample timings of the A terminal and the C terminal are synchronized with the sample timing of the B terminal will be described.

  FIG. 26 is a flowchart showing a procedure for synchronizing the sample timing of the A terminal with the sample timing of the B terminal. The specific procedure is the same as in the case of FIG. 21 of the third embodiment. In FIG. 21, the midpoint voltages Vf and Vsf are calculated based on the currents and voltages at the A and B ends, respectively. However, in the case of FIG. The voltages Vf and Vsf are calculated.

  24, 25, and 26, first, A / D converter 110 of current differential relay 53A samples current data I1 and voltage data by sampling the current and voltage at its own terminal (A terminal). V1 is generated (step S401A).

  Next, the voltage calculation unit 74 of the current differential relay 53A calculates the voltage VA of the first capacitor point 211 using the self-end voltage V1 and the self-end current I1 (step S402A).

  Next, the voltage calculation unit 74 of the current differential relay 53A calculates the charging current IAc using the voltage VA at the first capacitor point 211 (step S403A).

  Next, the voltage calculation unit 74 of the current differential relay 53A uses the value (I1-IAc) obtained by subtracting the charging current IAc from the self-end current I1 and the voltage VA of the first capacitor point 211 to generate a branch point. The voltage Vf is calculated (step S404A).

  Next, the receiver 131_2 of the current differential relay 53A receives the current and voltage sampling values (that is, current data Is1 and voltage data Vs1) at the other end (end B) via the communication path 54 (step S405A). ). The received current data Is1 and voltage data Vs1 are taken into the received data processing unit 72. Note that step S405A may be executed before step S402A. Steps S402A to S404A may be executed in parallel with steps S406A to S408A.

  Next, the voltage calculation unit 74 of the current differential relay 53A calculates the voltage VB of the second capacitor point 212 using the counterpart terminal voltage Vs1 and the counterpart terminal current Is1 (step S406A).

  Next, the voltage calculation unit 74 of the current differential relay 53A calculates the charging current IBc using the voltage VB of the second capacitor point 212 (step S407A).

  Next, the voltage calculation unit 74 of the current differential relay 53A branches using a value (Is1-IBc) obtained by subtracting the charging current IBc from the phase point end current Is1 and the voltage VB of the second capacitor point 212. The point voltage Vsf is calculated (step S408A).

  Next, the phase difference calculation unit 75 of the current differential relay 53A calculates the phase difference φ between the branch point voltages Vs and Vsf (step S409A). Further, the phase difference calculation unit 75 of the current differential relay 53A obtains a delay time (or advance time) corresponding to the phase difference φ and outputs it to the synchronization processing unit 73. The synchronization processing unit 73 corrects the sampling time by the delay time or advance time (step S410A). That is, the synchronization processing unit 73 controls the current and voltage sampling times at its own end so that the time t corresponding to the phase difference φ becomes zero. Thereby, the sample timing of the A terminal can be synchronized with the sample timing of the B terminal. Note that the sampling synchronization method described in FIG. 14 can be applied to the above case.

  FIG. 27 is a flowchart showing a procedure for synchronizing the sample timing of the C terminal with the sample timing of the B terminal. The specific procedure is the same as in the case of FIG. 21 of the third embodiment. However, in the case of FIG. 27, the voltages Vrf and Vsf at the branch point 200 are calculated instead of the intermediate point 57.

  24, 25, and 27, first, A / D converter 110 of current differential relay 53C samples current data Ir1 and voltage data by sampling the current and voltage at its own terminal (C terminal). Vr1 is generated (step S401C).

  Next, the voltage calculation unit 74 of the current differential relay 53C calculates the voltage VC at the third capacitor point 213 using the self-end voltage Vr1 and the self-end current Ir1 (step S402C).

  Next, the voltage calculator 74 of the current differential relay 53C calculates the charging current ICc using the voltage VC at the third capacitor point 213 (step S403C).

  Next, the voltage calculation unit 74 of the current differential relay 53C uses the value (Ir1-ICc) obtained by subtracting the charging current ICc from the local current Ir1 and the voltage VC of the third capacitor point 213 to determine the branch point. The voltage Vrf is calculated (step S404C).

  Next, the receiver 131_2 of the current differential relay 53C receives the current and voltage sampling values (that is, the current data Is1 and the voltage data Vs1) at the other end (B end) via the communication path 54C (Step 1). S405C). The received current data Is1 and voltage data Vs1 are taken into the received data processing unit 72. Note that step S405C may be executed before step S402C. Steps S402C to S404C may be executed in parallel with steps S406C to S408C.

  Next, the voltage calculation unit 74 of the current differential relay 53C calculates the voltage VB of the second capacitor point 212 using the counterpart terminal voltage Vs1 and the counterpart terminal current Is1 (step S406C).

  Next, the voltage calculation unit 74 of the current differential relay 53C calculates the charging current IBc using the voltage VB of the second capacitor point 212 (step S407C).

  Next, the voltage calculation unit 74 of the current differential relay 53C branches using a value (Is1-IBc) obtained by subtracting the charging current IBc from the phase point end current Is1 and the voltage VB of the second capacitor point 212. The point voltage Vsf is calculated (step S408C).

  Next, the phase difference calculation unit 75 of the current differential relay 53C calculates the phase difference φ between the branch point voltages Vrf and Vsf (step S409C). Furthermore, the phase difference calculation unit 75 of the current differential relay 53C obtains a delay time (or advance time) corresponding to the phase difference φ and outputs it to the synchronization processing unit 73. The synchronization processing unit 73 corrects the sampling time by the delay time or advance time (step S410C). That is, the synchronization processing unit 73 controls the current and voltage sampling times at its own end so that the time t corresponding to the phase difference φ becomes zero. Thereby, the sample timing of the C terminal can be synchronized with the sample timing of the B terminal. Further, the sampling synchronization method described in FIG. 14 can be applied to the above case.

  A three-terminal power transmission line can also be simulated using a π-type circuit. In this case, as in the case of the two terminals, each terminal to the branch point is simulated as an L-type circuit that is a part of the π-type circuit.

[When the power transmission line has 4 terminals]
FIG. 28 is a system diagram of a four-terminal power transmission line having a back power supply at each terminal. In the power transmission line of FIG. 28, the A end is connected to the branch point g via the power transmission line 221, and the D end is connected to the branch point g via the power transmission line 221. The B end is connected to the branch point f via the power transmission line 222, and the C end is connected to the branch point f via the power transmission line 223. The branch point g and the branch point f are connected via the power transmission line 220. Back power supplies 52A, 52B, 52C, and 52D are connected to the A end, B end, C end, and D end of the power transmission line, respectively.

  A current transformer CT1 is provided at the A end, and a voltage transformer VT1 is provided at the A-end bus 51A. A current transformer CT2 is provided at the B end, and a voltage transformer VT2 is provided at the bus 51B at the B end. A current transformer CT3 is provided at the C terminal, and a voltage transformer VT3 is provided at the C-terminal bus 51C. A current transformer CT4 is provided at the D end, and a voltage transformer VT4 is provided at the D-end bus 51D.

  In addition, current differential relays 53A, 53B, 53C, and 53D are installed at the A end, B end, C end, and D end, respectively. Each current differential relay 53 is connected to its own voltage transformer VT and current transformer CT. The current differential relays 53A, 53B, and 53C are connected to each other via a communication path (not shown), and exchange the detected current data and voltage data with each other.

  Hereinafter, in the above configuration, a procedure for synchronizing the sampling timings of the A end, the C end, and the D end with the sampling timing of the B end will be described.

  FIG. 29 is a flowchart illustrating an example of a procedure of sampling synchronization processing in the power transmission system of FIG. In the procedure of FIG. 29, the sampling timing of the other terminals is synchronized with the sampling timing of the B end in FIG.

  First, the D-terminal current differential relay 53D calculates the voltage Vg at the branch point g based on the A-terminal voltage V1 and the A-terminal current I1 (step S601). Further, the current differential relay 53D calculates the voltage Vqg at the branch point g based on the D terminal voltage Vq1 and the D terminal current Iq1 (step S602). These specific calculation methods are the same as those described in the first and third embodiments.

  Next, the current differential relay 53D calculates the phase difference φ1 between the voltage Vg and the voltage Vqg at the branch point g (step S603). The current differential relay 53D corrects the sampling time at the D end by a delay time (or advance time) corresponding to the phase difference φ1 (that is, synchronizes the sampling time at the D end with the sampling time at the A end) (step) S604).

  Next, the current differential relay 53A calculates a combined current Ig + Iqg of the current Ig flowing from the A end to the branch point g and the current Iqg flowing from the D end to the branch point g (step S605).

  Next, the current differential relay 53A calculates the voltage Vgf at the branch point f based on the voltage Vg at the branch point g and the combined current Ig + Iqg (step S606). Further, the current differential relay 53A calculates the voltage Vsf at the branch point f based on the B terminal voltage Vs1 and the B terminal current Is1 (step S607).

  Next, the current differential relay 53A calculates the phase difference φ2 between the voltage Vgf and the voltage Vsf at the branch point f (step S608).

  Next, the current differential relay 53A corrects the sampling time at the A end by a delay time (or advance time) corresponding to the phase difference φ2 (that is, the sampling time at the A end is synchronized with the sampling time at the B end. ). The D-terminal current differential relay 53D corrects the D-terminal sampling time by a delay time (or advance time) corresponding to the phase difference φ2 (that is, the D-terminal sampling time is changed to the B-end sampling time). (Synchronized) (step S609). Therefore, the sampling time at the D end is finally corrected by a time corresponding to the phase difference (φ1 + φ2).

  Next, the C-terminal current differential relay 53C calculates the voltage Vrf at the branch point f based on the C-terminal voltage Vr1 and the C-terminal current Ir1 (step S610). Further, the C-terminal current differential relay 53C calculates the voltage Vsf at the branch point f based on the B-terminal voltage Vs1 and the B-terminal current Is1 (step S611).

  Next, the current differential relay 53C calculates the phase difference φ3 between the voltage Vsf and the voltage Vrf at the branch point f (step S612). The current differential relay 53C corrects the sampling time at the C end by a delay time (or advance time) corresponding to the calculated phase difference φ3 (that is, the sampling time at the C end is synchronized with the sampling time at the B end). (Step S613). Thus, the sampling synchronization process is completed.

  Thus, the terminal (B end) where the master current differential relay 53B to be synchronized is installed and the current differential relay 53C at the C end connected via one branch point f are connected to each terminal (B The voltage at the branch point f is calculated based on the current and voltage data at the end and the C end. The current differential relay 53C can correct the sample timing based on the calculated phase difference between the branch point voltages.

  On the other hand, the current differential relays 53A and 53D at the A and D ends connected to the terminal (B end) where the master current differential relay 53B to be synchronized is connected via two or more branch points f and g. First, it is necessary to calculate a combined current at a branch point g different from the branch point f directly connected to the B end. For this reason, the step which synchronizes the other sampling timing with the sampling timing of either one of these current differential relays 53A and 53D is needed.

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  50, 201-203, 220-223 Transmission line, 52A-52D Power supply behind, 53, 53A-53D Current differential relay, 54, 54B, 54C Communication path, 56, 91, 211 First capacitor point, 57 Intermediate point 58, 93, 212 Second capacitor point, 96, 213 Third capacitor point, 94 Fourth capacitor point, 67 Specific point, 76 Relay operation unit, 74 Voltage operation unit, 75 Phase difference operation unit, 73 Synchronization Processing unit, 80-86, 204-206 T-type circuit, 100 input conversion unit, 110 A / D conversion unit, 120 arithmetic processing unit, 130 I / O unit, 131 transceiver, 132 digital input circuit, 133 digital output circuit , 200, f, g Branch point, C, CA, CB Ground capacity, CT, CT1 to CT4 Current transformer, VT, VT1 to VT4 Voltage change Generator, Ts Specific time interval.

Claims (16)

A current differential relay provided at the first terminal of the power transmission line,
An analog / digital converter that samples current and voltage of the first terminal of the transmission line to generate current data and voltage data;
A receiver for receiving current data and voltage data of the second terminal from a second current differential relay provided at a second terminal of the power transmission line;
Based on the current data and voltage data of the first terminal, a voltage at a specific point between the first terminal and the second terminal of the transmission line is calculated as a first specific point voltage, and the second terminal A voltage calculation unit that calculates a voltage at the specific point as a second specific point voltage based on current data and voltage data;
A phase difference calculator that calculates a phase difference between the first specific point voltage and the second specific point voltage;
A synchronization processing unit that adjusts the sampling time of the current and voltage of the first terminal based on the time corresponding to the phase difference;
The voltage calculation unit includes a first line that connects the first terminal and the specific point, and a second line that connects the second terminal and the specific point. The first specific point is obtained by simulating as an L-shaped circuit that is a part of the π-shaped circuit when formed into a shaped circuit, as a single T-shaped circuit, or as a plurality of T-shaped circuits connected in series. A current differential relay for calculating a voltage and the second specific point voltage. Each of the first line and the second line is simulated as an L-type circuit that is a part of the π-type circuit when the entire transmission line is a single π-type circuit,
The voltage calculation unit calculates a charging current of the first line based on the voltage of the first terminal, and subtracts the charging current of the first line from the current of the first terminal. Calculating the voltage drop of one line, and calculating the first specific point voltage by subtracting the voltage drop of the first line from the voltage of the first terminal;
The voltage calculation unit calculates the charging current of the second line based on the voltage of the second terminal, and subtracts the charging current of the second line from the current of the second terminal. 2. The current differential relay according to claim 1, wherein the second specific point voltage is calculated by calculating a voltage drop of two lines and subtracting a voltage drop of the second line from a voltage of the second terminal. The first line is simulated as a single first T-type circuit, the second line is simulated as a single second T-type circuit,
The voltage calculation unit subtracts a voltage drop from the first terminal to the capacitor point of the first T-type circuit from the voltage of the first terminal, thereby obtaining a voltage at the capacitor point of the first T-type circuit. A current obtained by calculating, calculating a charging current of the first line based on a voltage at a capacitor point of the first T-type circuit, and subtracting the charging current of the first line from the current of the first terminal; And the first specific point voltage based on the voltage at the capacitor point of the first T-shaped circuit,
The voltage calculation unit subtracts a voltage drop from the second terminal to the capacitor point of the second T-type circuit from the voltage of the second terminal, thereby obtaining a voltage at the capacitor point of the second T-type circuit. A current obtained by calculating, calculating the charging current of the second line based on the voltage at the capacitor point of the second T-type circuit, and subtracting the charging current of the second line from the current of the second terminal 2. The current differential relay according to claim 1, wherein the second specific point voltage is calculated based on a voltage at a capacitor point of the second T-shaped circuit. A current differential relay provided at the first terminal of the power transmission line,
An analog / digital converter that samples current and voltage of the first terminal of the transmission line to generate current data and voltage data;
A receiver for receiving current data and voltage data of the second terminal from a second current differential relay provided at a second terminal of the power transmission line;
By simulating a line connecting the first terminal and the second terminal as a single T-type circuit or a plurality of T-type circuits connected in series, the current data and voltage data of the first terminal A voltage calculation unit for calculating a voltage at two terminals;
A phase difference calculator that calculates a phase difference between the voltage of the second terminal calculated by the voltage calculator and the actual voltage of the second terminal;
A current differential relay comprising: a synchronization processing unit that adjusts a sampling time of the current and voltage of the first terminal based on a time corresponding to the phase difference. The line connecting the first terminal and the second terminal is simulated as a single T-shaped circuit,
The voltage calculation unit calculates a voltage at the capacitor point of the T-type circuit by subtracting a voltage drop from the first terminal to the capacitor point of the T-type circuit from the voltage of the first terminal, Calculate the charging current of the line based on the voltage at the capacitor point of the circuit, and based on the current obtained by subtracting the charging current of the line from the current of the first terminal and the voltage at the capacitor point of the T-shaped circuit. The current differential relay according to claim 4, wherein the voltage of the second terminal is calculated. A current differential relay provided at the first terminal of the power transmission line,
An analog / digital converter that samples current and voltage of the first terminal of the transmission line to generate current data and voltage data;
A receiver for receiving current data and voltage data of the second terminal from a second current differential relay provided at a second terminal of the power transmission line;
By simulating a line connecting the first terminal and the second terminal as a single T-type circuit or a plurality of T-type circuits connected in series, the current data and voltage data of the second terminal A voltage calculator for calculating the voltage at one terminal;
A phase difference calculator that calculates a phase difference between the voltage at the first terminal calculated by the voltage calculator and the actual voltage at the first terminal;
A current differential relay comprising: a synchronization processing unit that adjusts a sampling time of the current and voltage of the first terminal based on a time corresponding to the phase difference. The current differential relay further includes a transmitter that transmits a first timing signal to the second current differential relay together with current data and voltage data of the first terminal,
The receiver receives a second timing signal from the second current differential relay together with current data and voltage data of the second terminal,
The synchronization processing unit
A first time interval from when the transmitter transmits the first timing signal to when the receiver receives the second timing signal; and the second current differential relay is A first step of controlling a sampling time of current and voltage of the first terminal so that a second time interval from transmission of a timing signal to reception of the first timing signal is equal;
A second step of storing, as a third time interval, a time corresponding to the phase difference calculated by the phase difference calculating unit when the first time interval and the second time interval are equal;
Performing a third step of controlling the sampling time of the current and voltage of the first terminal so that the first time interval and the second time interval differ by twice the third time interval. The current differential relay according to claim 1, configured as described above. The synchronization processing unit corresponds to the phase difference calculated by the phase difference calculation unit when the first time interval and the second time interval are different from each other by twice the third time interval. Further configured to perform a fourth step of correcting the third time interval using time;
The current differential relay according to claim 7, wherein in the third step, the third time interval corrected by the fourth step is used. The synchronization processing unit is configured to continuously correct the third time interval by repeatedly executing the fourth step when the transmission line is normal.
The synchronization processing unit does not execute the fourth step when the power transmission line fails, but performs the third step using the third time interval corrected immediately before the power transmission line failure occurs. The current differential relay according to claim 8, configured as described above. The synchronization processing unit performs the first step and the second step when the power transmission line is normal, and then the time corresponding to the phase difference calculated by the phase difference calculation unit becomes 0. Configured to perform a fifth step of controlling the sampling time of the current and voltage of the first terminal;
The current differential relay according to claim 7, wherein the synchronization processing unit is configured to execute the third step instead of the fifth step when the power transmission line fails. Sampling the current and voltage of the first terminal of the transmission line to generate current data and voltage data;
Sampling the current and voltage of the second terminal of the transmission line to generate current data and voltage data;
Calculating a voltage at a specific point between the first terminal and the second terminal of the transmission line as a first specific point voltage from current data and voltage data of the first terminal;
Calculating the voltage at the specific point as the second specific point voltage from the current data and voltage data of the second terminal,
In the step of calculating the first specific point voltage and the second specific point voltage, a first line connecting the first terminal and the specific point and a second line connecting the second terminal and the specific point Are each an L-type circuit that is a part of the π-type circuit when the entire transmission line is a single π-type circuit, or a single T-type circuit, or a plurality of Ts connected in series. Simulated as a shaped circuit,
And calculating a phase difference between the first specific point voltage and the second specific point voltage as a first phase difference;
Adjusting the sampling time of the current and voltage of the first terminal based on the time corresponding to the first phase difference. The power transmission line further includes a third terminal connected to the specific point via a third line,
The sampling synchronization method further includes:
Sampling current and voltage of the third terminal to generate current data and voltage data;
By simulating the third line as a single L-shaped circuit that is part of a pi-shaped circuit or as a single T-shaped circuit or as a plurality of T-shaped circuits connected in series, the current of the third terminal Calculating a voltage at the specific point as a third specific point voltage from data and voltage data;
Calculating a phase difference between the second specific point voltage and the third specific point voltage as a second phase difference;
The sampling synchronization method according to claim 11, further comprising a step of adjusting a sampling time of current and voltage of the third terminal based on a time corresponding to the second phase difference. The sampling synchronization method includes:
Transmitting a first timing signal together with current data and voltage data of the first terminal from a first transmitter / receiver provided at the first terminal to a second transmitter / receiver provided at the second terminal;
Transmitting a second timing signal together with current data and voltage data of the second terminal from the second transceiver to the first transceiver;
Adjusting the sampling time of the current and voltage of the first terminal,
A first time interval from when the first transceiver transmits the first timing signal to reception of the second timing signal; and the second transceiver transmits the second timing signal. A first step of controlling the current and voltage sampling times of the first terminal so that a second time interval from transmission to reception of the first timing signal is equal;
A second step of storing, as a third time interval, a time corresponding to the first phase difference when the first time interval and the second time interval are equal;
A third step of controlling the sampling time of the current and voltage of the first terminal so that the first time interval and the second time interval differ by twice the third time interval; The sampling synchronization method according to claim 11 or 12. The step of adjusting the sampling time of the current and voltage of the first terminal further includes
Using the time corresponding to the first phase difference calculated when the first time interval and the second time interval differ by twice the third time interval; A fourth step of correcting the time interval of
The sampling synchronization method according to claim 13, wherein in the third step, the third time interval corrected in the fourth step is used. In the step of adjusting the sampling time of the current and voltage of the first terminal,
When the power transmission line is normal, the third time interval is continuously corrected by repeatedly executing the fourth step,
The fourth step is not executed when the power transmission line fails, and the third step is executed using the third time interval corrected immediately before the power transmission line failure occurs. The sampling synchronization method described. In the step of adjusting the sampling time of the current and voltage of the first terminal,
Sampling time of current and voltage of the first terminal so that the time corresponding to the first phase difference becomes 0 after the first step and the second step are executed when the power transmission line is normal A fifth step of controlling
The sampling synchronization method according to claim 13, wherein the third step is executed instead of the fifth step when the power transmission line is abnormal.

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