KR20200014914A - Current Differential Relay and Sampling Synchronization Method - Google Patents

Abstract

In the current differential relay 53A, the voltage calculating section 74 is a specific point on the line connecting the first terminal and the second terminal of the power transmission line based on the current data I1 and the voltage data V1 of the first terminal. The voltage at is calculated as the first specific point voltage, and the voltage at the specific point is calculated as the second specific point voltage based on the current data Is1 and the voltage data Vs1 of the second terminal. Here, the voltage calculating part 74 uses the 1st line which connects a 1st terminal and a specific point, and the 2nd line which connects a 2nd terminal and a specific point, when the whole transmission line is made into a single (pi) type circuit. The 1st specific point voltage and the 2nd specific point voltage are computed by simulating as an L type circuit which is a part of said (pi) type circuit, as a single T type circuit, or as a some T type circuit connected in series. The phase difference calculator 75 calculates a phase difference between the first specific point voltage and the second specific point voltage. The synchronization processor 73 adjusts the sampling time based on the time corresponding to the phase difference.

Description

Current Differential Relay and Sampling Synchronization Method

The present disclosure relates to a current differential relay for protecting a transmission line, and a sampling synchronization method for detecting current and voltage values at both ends of a transmission line by the current differential relay and the like.

A current differential relay that protects a power transmission line is provided at both ends of a protection section of the power transmission line. Each current differential relay receives a current value from a current transformer provided in its own end and transmits the received current values to each other via a transmission path. Each current differential relay detects a failure in the power transmission line based on the difference between the current values at both ends of the power transmission line. At that time, synchronization of the sampling timing of the current at both ends of the power transmission line is necessary for accurate failure determination.

The sampling synchronization method used conventionally and becoming mainstream is disclosed, for example in Unexamined-Japanese-Patent No. 62-262615 (patent document 1). In this method, each current differential relay incorporates transmission timing information into the transmission data when transmitting current data of its own end to the other end. Each of the current differential relays measures the time from transmitting the transmission timing information to the other end and then receiving the transmission timing information of the other end. Each current differential relay transmits the measured time to each other, and adjusts the sampling timing so that these times are equal to each other.

In order to accurately perform sampling synchronization by this method, it is essential that the transfer time from the other end to the other end is equal to the transfer time from the opposite end to the other end. However, when transmitting using a general-purpose communication device, there may be a difference of several hundred microseconds in these two-way transmission times. For this reason, an error occurs in the sampling synchronization, and this synchronization error is an error factor of the current differential relay operation.

Thus, for example, in the case where precision is necessary, such as a fault point expression device that looks for a fault point in a transmission line serving as a protective section, it is described in, for example, Japanese Patent Laid-Open No. 4-17509 (Patent Document 2). A sampling synchronization method as is proposed. Specifically, the fault point expression apparatus according to this method acquires detection values of voltage and current at both ends of a power transmission line. And the fault-point expression apparatus calculates the terminal voltage of the other end by subtracting the voltage drop of the transmission line by the terminal current of the one end from the terminal voltage of the one end of a transmission line. The fault point expression apparatus performs sampling synchronization at both ends of a power transmission line based on the phase difference between the calculated terminal voltage of the other end and the terminal voltage of the other end actually acquired.

Patent Document 1: Japanese Patent Application Laid-Open No. 62-262615 Patent Document 2: Japanese Patent Application Laid-Open No. 4-17509

The inventor of this application examined the error factor of the sampling synchronization method disclosed in patent document 2 etc. mentioned above. As a result, the sampling synchronization method according to this document found that the problem was that the influence of the charging current from the power transmission line to the ground based on the ground capacitance of the power transmission line was not considered. In particular, since the charging current cannot be ignored when the transmission line is composed of underground cables or when the length of the line is long in the overhead line, the error is large in sampling synchronization in which charging current is ignored. Such a problem has not been generally examined until now.

This disclosure considers the above problems, and an object thereof is to provide a sampling synchronization processing method for accurately realizing sampling synchronization at both ends of a transmission line, and a current differential relay incorporating this sampling synchronization processing method.

The current differential relay according to one embodiment is provided at a first terminal of a power transmission line. The current differential relay includes an analog / digital converter, a receiver, a voltage calculator, a phase difference calculator, and a synchronization processor. The analog / digital converter generates current data and voltage data by sampling current and voltage at the first terminal of the power transmission line. The receiver receives current data and voltage data of the second terminal from a second current differential relay provided at the second terminal of the power transmission line. The voltage calculating unit calculates the voltage at the specific point between the first terminal and the second terminal of the power transmission line as the first specific point voltage based on the current data and the voltage data of the first terminal, and the current data and the second terminal. Based on the voltage data, the voltage at this specific point is calculated as the second specific point voltage. The phase difference calculator calculates a phase difference between the first specific point voltage and the second specific point voltage. The synchronization processor adjusts the sampling time of the current and the voltage of the first terminal based on the time corresponding to this phase difference. Here, the voltage calculation unit is a π-type when each of the first line that connects the first terminal and the specific point and the second line that connects the second terminal and the specific point is a single π-type circuit. The first specific point voltage and the second specific point voltage are calculated by simulating as an L-type circuit which is part of the circuit, as a single T-type circuit, or as a plurality of T-type circuits connected in series.

According to the above embodiment, each of the first line and the second line is an L-type circuit which is part of the π-type circuit when the entire transmission line is a single π-type circuit, or as a single T-type circuit, or By simulating as a plurality of T-type circuits connected in series, the influence of the earth capacity of the power transmission line is taken into account for calculation, so that the sampling synchronization at both ends of the power transmission line can be performed with high accuracy.

1 is a system diagram of a power transmission line having a rear power supply at both ends.
FIG. 2 is a block diagram showing an example of a hardware configuration of each current differential relay of FIG. 1. FIG.
3 is an equivalent circuit diagram of a normal circuit when there is no failure in the power transmission system of FIG.
4 is a view for explaining a charging current in the normal circuit of FIG.
5 is a vector diagram illustrating an example of a phase difference between the A stage voltage V1 and the B stage voltage Vs1.
6 is a diagram for explaining a sampling synchronization method.
7 is an equivalent circuit diagram of a normal circuit of a power transmission system simulated by a π-type circuit.
FIG. 8 is a diagram for describing charging current in the normal circuit of FIG. 7. FIG.
9 is a block diagram showing the functional configuration of the current differential relay of Embodiment 1. FIG.
10 is a flowchart showing a procedure of sampling synchronization processing according to the first embodiment.
11 is a vector diagram showing an example of the phase difference between the midpoint voltages Vf and Vfs.
12 is a flowchart showing another sampling synchronization sequence.
FIG. 13 is a diagram for explaining the procedure of step S711 of FIG. 12 in more detail.
14 is a flow chart showing another sampling synchronization sequence.
Fig. 15 is an equivalent circuit diagram of a normal circuit of a power transmission system to which the sampling synchronization process according to the modification of Embodiment 1 is applied.
Fig. 16 is an equivalent circuit diagram of a normal circuit of a power transmission system to which the sampling synchronization process according to the second embodiment is applied.
Fig. 17 is a flowchart showing a procedure of sampling synchronization processing according to the second embodiment.
18 is an equivalent circuit diagram of a normal circuit of a power transmission system in the case of simulating a power transmission line in a two-stage T-type circuit.
FIG. 19 is a flow chart showing a sampling synchronization sequence of a power transmission system simulated by the equivalent circuit of FIG. 18. FIG.
20 is an equivalent circuit diagram of a normal circuit of a power transmission system to which the sampling synchronization process of Embodiment 3 is applied.
21 is a flowchart showing a sampling synchronization sequence of a power transmission system simulated by the equivalent circuit of FIG. 20.
Fig. 22 is an equivalent circuit diagram of the normal circuit of the power transmission system in the case where the terminal from the terminal to the intermediate point is simulated by a two-stage T-type circuit.
FIG. 23 is a flowchart showing a sampling synchronization sequence of a power transmission system simulated by the equivalent circuit of FIG.
24 is a system diagram of a three-terminal power transmission line having a rear power supply at each terminal.
25 is an equivalent circuit diagram of a normal circuit of the power transmission system of FIG. 24.
Fig. 26 is a flowchart showing a procedure for synchronizing the sample timing of terminal A to the sample timing of terminal B;
Fig. 27 is a flowchart showing a procedure for synchronizing the sample timing of the C terminal with the sample timing of the B terminal.
28 is a system diagram of a four-terminal power transmission line having a rear power supply at each terminal.
29 is a flowchart showing an example of a procedure of sampling synchronization processing in the power transmission system of FIG. 28;

EMBODIMENT OF THE INVENTION Hereinafter, each embodiment is described in detail with reference to drawings. In addition, the same code | symbol is attached | subjected to the same or corresponding part, and the description is not repeated.

Embodiment 1.

<Common Configuration and Prerequisites>

First, the structure and matters which are assumed in common in each embodiment are demonstrated, and the characteristic of Embodiment 1 is demonstrated after that.

[Schematic diagram of transmission line with rear power supply at both ends]

1 is a system diagram of a power transmission line having rear power supplies at both ends. Referring to FIG. 1, a rear power supply 52A is provided at the A stage (also referred to as the first stage) of the power transmission line 50, and the B stage (also referred to as the second stage) of the power transmission line 50. The rear power source 52B is provided. In addition, although the transmission line 50 is a three-phase transmission line, it is shown by one line in FIG. 1 for ease of illustration.

A current transformer (CT) CT1 is provided at the A stage of the power transmission line 50, and a voltage transformer VT1 is provided at the bus line 51A of the A stage. Similarly, the current transformer CT2 is provided at the B stage of the power transmission line 50, and the voltage transformer VT2 is provided at the bus line 51B of the B stage. A breaker (CB: Circuit Breaker) 68A is provided near the A stage, and a breaker 68B is provided near the B stage, above the power transmission line 50 between the A stage and the B stage.

In this specification, when describing generically about the current transformers CT1 and CT2, or when showing an unspecified thing, it describes as current transformer CT. The voltage transformers VT1 and VT2 are referred to as voltage transformers VT when they are generically used or when they are unspecified. In addition, a current and voltage may be generically called an electric quantity.

Current differential relays 53A and 53B are further provided at the A and B ends of the power transmission line 50, respectively. In addition, in this specification, when showing the current differential relay provided in any one terminal, it describes as the current differential relay 53. As shown in FIG. In addition, the current differential relays 53A and 53B provided at each terminal of the power transmission line 50 may be integrated to be referred to as a current differential relay system.

Each of the current differential relays 53A and 53B acquires a signal indicating a three-phase alternating current flowing through the magnetic end of the power transmission line 50 from the current transformer CT of its own end, A signal indicative of the three-phase alternating voltage of the rosewood is obtained from the voltage transformer VT of the rosewood. Each of the current differential relays 53A and 53B generates current data and voltage data by sampling and acquiring A / D conversion of the current and voltage of the magnetic poles obtained. Each current differential relay transmits its own current data and voltage data to the current differential relay of the other end via the communication path 54. In this case, the communication path 54 may be wired or wireless. The current differential relays 53A and 53B calculate the difference current at both ends of the power transmission line 50 from the acquired magnetic and relative current data, and protect the inner side of the current transformers CT1 and CT2 based on the calculated difference current. It is determined whether a failure occurs in the power transmission line 50 within the section.

In order to accurately calculate the difference current at both ends of the power transmission line 50, the current differential relays 53A and 53B at both ends of the power transmission line 50 may synchronize the timing of sampling current values from the current transformers CT1 and CT2, respectively. There is a need. For this reason, the synchronous processing is performed by the current differential relays 53A and 53B. The most basic synchronization process is as follows.

Specifically, each current differential relay 53 transmits the current and voltage sampling data of its own end to the other end at a predetermined interval (for example, 30 ° period of the electric angle of the alternating current). Decorate the timing signal in the transmission data. Each current differential relay 53 measures the time interval between the transmission time of the timing signal to the counterpart and the reception time of the timing signal from the counterpart. Each of the current differential relays 53 transmits the measured time intervals to each other. Each current differential relay 53 has a sampling timing and a timing signal of the electric quantity so that the time interval T1 between the transmission time and the reception time of the timing signal measured at its own end and the time interval T2 received from the opposite end are equal. To adjust the timing of the transmission.

In practice, the above-described timing adjustment may be performed only in either one of the current differential relays 53A and 53B at both ends of the power transmission line 50. For example, timing adjustment is performed based on information indicating the above-described time interval received from the other (master) by a predetermined one (slave) of the current differential relays 53A and 53B.

In order to perform the above-described basic synchronization processing correctly, the transmission time through the communication path 54 from the A terminal to the B terminal of the power transmission line 50 and the transmission time through the communication path 54 from the B terminal to the A terminal are mutually different. The precondition of equality is required. If these transmission times are different, the sampling synchronization error is 1/2 of the difference of each transmission time. In the case of using a general-purpose communication device, even if the lengths of the communication paths from the A stage to the B stage and the lengths of the communication paths from the B stage to the A stage are equal, the difference in the transmission time is at most about 100 ms. There is a case.

Therefore, the current differential relay 53 of the present disclosure performs sampling synchronization processing using voltage data and current data at both ends of the power transmission line 50. Specifically, the current differential relay 53 calculates the voltage at a specific point on the power transmission line 50 using the voltage data and current data of the A stage, and uses this voltage and current data of the B stage. Calculate the voltage. The current differential relay 53 performs sampling synchronization on both ends of the power transmission line 50 based on the calculated phase difference between the positive voltages. The above specific point may be the B stage. In this case, the current differential relay 53 calculates the voltage of the B stage using the voltage data and the current data of the A stage, and detects the voltage of the B stage and the actual detection. Sampling synchronization of both ends of the power transmission line 50 is performed based on the phase difference of the voltage of one B-stage.

Hereinafter, this sampling synchronization method is called a sampling synchronization method based on a voltage phase difference. The sampling synchronization processing based on the voltage phase difference may be used to complement the synchronization processing based on the time interval between the transmission time and the reception time of the timing signal described above, or may be used instead of the synchronization processing described above. The basic idea of sampling synchronization processing based on this voltage phase difference will be described later with reference to FIGS. 3 to 7.

[Example of Hardware Configuration of Current Differential Relay]

FIG. 2 is a block diagram illustrating an example of a hardware configuration of each current differential relay of FIG. 1. The current differential relay 53 in FIG. 2 has the same configuration as a so-called digital relay device. Specifically, referring to FIG. 2, the current differential relay 53 includes an input converter 100, an A / D (analog / digital) converter 110, an operation processor 120, and an I / O ( Input and Output) 130 is provided.

The input converter 100 includes auxiliary transformers 101_1, 101_2,... For each input channel. The input converter 100 receives a current signal from the current transformer CT of FIG. 1 and a voltage signal from the voltage transformer VT. Each auxiliary transformer 101 has a voltage level suitable for signal processing in the A / D converter 110 and the arithmetic processing unit 120 for the current signal from the current transformer CT and the voltage signal from the voltage transformer VT. Convert to the signal of.

The A / D converter 110 includes an analog filter (AF: Analog Filters 111_1, 111_2, ...), a sample hold circuit (S / H: Sample Hold Circuit) 112_1, 112_2, ..., and a multiplexer ( MPX: Multiplexer) 113 and A / D converter 114. The analog filter 111 and the sample hold circuit 112 are provided for each channel of the input signal.

Each analog filter 111 is a low pass filter provided in order to eliminate the return error at the time of A / D conversion. Each sample hold circuit 112 samples and holds the signal passing through the corresponding analog filter 111 at a prescribed sampling frequency. The sampling frequency is 4800 Hz, for example. The multiplexer 113 sequentially selects the voltage signals held in the sample hold circuits 112_1, 112_2,... The A / D converter 114 converts the signal selected by the multiplexer 113 into a digital value.

The arithmetic processing unit 120 includes a central processing unit (CPU) 121, a random access memory (RAM) 122, a read only memory (ROM) 123, and a bus 124 connecting them. . The CPU 121 controls the operation of the entire current differential relay 53. The RAM 122 and the ROM 123 are used as main memories of the CPU 121. The ROM 123 can store a program and a set value for signal processing by using a nonvolatile memory such as a flash memory.

In addition, the arithmetic processing part 120 should just be comprised by either circuit, and is not limited to the example of FIG. For example, the arithmetic processing unit 120 may include a plurality of CPUs. In addition, the arithmetic processing unit 120 may be configured by at least one ASIC (Application Specific Integrated Circuit) in place of a processor such as a CPU, or may be configured by at least one field programmable gate array (FPGA). . Alternatively, the arithmetic processing unit 120 may be configured by a combination of any one of a processor, an ASIC, and an FPGA.

The I / O unit 130 includes a transceiver (TX / RX) 131, a digital input (D / I: digital input) circuit 132, and a digital output (D / O: digital output) circuit 133. It includes. The transceiver 131 includes a transmitter 131_1 and a receiver 131_2, and communicates with the transceiver 131 provided in the current differential relay 53 at the opposite end via the communication path 54 of FIG. 1. The digital input circuit 132 and the digital output circuit 133 are interface circuits when communicating between the CPU 121 and an external device. For example, the digital output circuit 133 outputs a trip signal to the breaker 68A or 68B on the magnetic end side shown in FIG.

[Sampling Synchronization Method Based on Voltage Phase Difference]

(Equivalent circuit by normal circuit)

When sampling synchronization processing based on the voltage phase difference is performed in a state where there is no failure in the power transmission line 50, the synchronization processing may be performed using voltage data and current data of any one of the three phases. In the present disclosure, sampling synchronization processing is performed using a steady current and a steady voltage of the symmetric coordinate method for the purpose of leveling out the detection errors in consideration of detection errors of current and voltage.

3 is an equivalent circuit diagram of a normal circuit when there is no failure in the power transmission system of FIG. 1. Referring to FIG. 3, the normal voltage of the A stage is set to V1, and the normal current of the A stage is set to I1. Similarly, the normal voltage of the B stage is set to Vs1, and the normal current of the B stage is set to Is1.

As is well known, the steady voltage V1 uses the three-phase voltages Va, Vb, and Vc of the A stage.

V1 = (Va + α · Vb + α ² · Vc) / 3... (One)

Is displayed. The steady current I1 uses the three-phase currents Ia, Ib, and Ic of the A stage,

I1 = (Ia + α · Ib + α ² · Ic) / 3... (2)

Is displayed. However, let imaginary unit be j,

α = (− 1 + j.√3) / 2... (3)

This holds true. The same applies to the B stage. In addition, in this specification, a multiplication symbol is represented by "*", "*", or "x".

The normal impedance of the power transmission line 50 is set to Z1, and the earth capacitance of the power transmission line 50 is set to C (only referred to as the ground capacitance C). The charging current Ic corresponds to the current flowing through the ground capacitance C. FIG. In addition, the resistance, the inductive resistance, and the capacity of the power transmission line 50 are represented by a distribution constant, which is expressed intensively here for the sake of simplicity. In the following description, for the sake of simplicity, there are cases where only the voltage, the current, and the impedance are described for the steady voltage, the steady current, and the normal impedance.

(Charging current of transmission line)

4 is a diagram for explaining a charging current in the normal circuit of FIG. 3. In FIG. 4, the position of the A stage is represented by x = 0 and the position of the B stage is represented by x = 1. That is, the length of the transmission line 50 is normalized to one.

Fig. 4A shows the voltage change on the power transmission line when there is a voltage difference between the self-terminal voltage V1 and the relative voltage Vs1. Originally, voltages V1 and Vs1 should be shown as vectors (i.e., voltage amplitude and phase), but as shown in graph 60, they are shown to be simply different in scalar (i.e., only voltage amplitude). In fact, in the voltages V1 and Vs1, there are many cases where there is no difference in amplitude and a phase difference.

The graph 61 of FIG. 4B shows the change of the load current on the power transmission line. As described above, the load current flows due to the difference in the voltage vector at both ends of the power transmission line 50. The load current at the A stage is set to I1, and the load current at the B stage is set to Is1. In addition, the load current Is1 sets the direction from the B stage to the A stage as positive.

The charging current Ic (x) to the point x on the transmission line depends on the voltage V of the transmission line at the point x (x). The relationship is that the capacitance per unit length of the transmission line is C,

Ic (x) = jωC · V (x)... (4)

Is displayed. At A stage, that is, x = 0,

Ic (0) = jωCV1... (5)

Is established and at stage B, i.e., x = 1,

Ic (1) = jωC Vs... (6)

This holds true. Therefore, the total amount of charging current Ic of the power transmission line 50 is represented by following Formula (7). Here, x represents a position on a power transmission line, sets A stage of the transmission line 50 to x = 0, and B stage of the power transmission line 50 to x = 1.

[Equation 1]

(Sampling synchronization based on voltage phase difference without load current)

When there is no load current, the A stage voltage V1 and the B stage voltage Vs1 become equal (see graph 62 in Fig. 4A). In this case, the phase difference between the A-stage voltage V1 and the B-stage voltage Vs1 becomes a negligible level, but in practice, since the timing of sampling at both ends of the power transmission line 50 is shifted, the A-stage voltage The phase difference φ occurs between V1 and the B terminal voltage Vs1.

5 is a vector diagram illustrating an example of a phase difference between the A stage voltage V1 and the B stage voltage Vs1. In the vector diagram of FIG. 5, the B stage voltage Vs1 is shown to precede the A stage voltage V1 by the phase difference φ. Therefore, for sampling synchronization, it is necessary to advance the sampling time of the B stage by a time t corresponding to the phase difference φ, or to delay the sampling time of the A stage by a time t corresponding to the phase difference φ. have. If the time t is taken as the unit of the phase difference φ,

t = (φ / 360 °) * time of 1 cycle... (8)

Is displayed. If the alternating frequency is f, one cycle time is 1 / f [sec].

[Combination of two sampling synchronization methods]

Next, a method of combining the sampling synchronization method based on the voltage phase difference described above with the sampling synchronization method based on the time interval between the transmission time and the reception time of the timing signal described above will be described.

6 is a timing diagram for explaining a sampling synchronization method. As in FIG. 5, it is assumed that the B stage voltage Vs1 is preceded by the phase difference φ before the A stage voltage V1. The time corresponding to phase difference (phi) is set to t.

Referring to Fig. 6A, the timing signal transmitted from the A stage at the time t1 is received at the B stage at the time t4, and the timing signal transmitted from the B stage at the time t2 is the time t3. Is said to have been received at stage A. In this case, the time interval T1 (that is, the time t1 to the time t3) between the transmission time and the reception time of the timing signal at the A stage is the transmission time and the reception time of the timing signal at the B stage. Is equal to the time interval T2 (that is, from time t2 to time t4). However, the timing of the sampling of the B stage is delayed by the time t than the timing of the sampling of the A stage.

In this case, the signal transmission time from stage B to A is T1-t, and the signal transmission time from stage A to B is T1 + t. Therefore, the sampling synchronization is achieved by correcting the timing of sampling at stage B to be advanced by the time t of the above expression (8). Therefore, the transfer from the stage B to the stage A via the communication path 54 of FIG. This means that the time is 2xt shorter than the transfer time from the A stage to the B stage.

Referring to Fig. 6B, the time interval between the transmission time and the reception time of the timing signal in the A stage is T3, and the time interval between the transmission time and the reception time of the timing signal in the B stage is T4. In this case, the current differential relays 53 of either one of the A stage and the B stage (for example, the slave side) are connected to each other so that the time interval T3 is longer by 2 x t than the time interval T4. Adjust the timing for sending the sampling timing and timing signal. As a result, sampling synchronization at the A stage and the B stage can be realized.

Specifically, as shown in Fig. 6B, it is assumed that timing signals are transmitted from the A stage and the B stage to the counterpart at time t11. Therefore, the timing signal transmitted from the A stage is received at the B stage at a time t13 when the timing signal transmitted from the B stage has elapsed 2 times t from the time t12 received at the A stage.

By the above, even if there is a difference in the transmission time of the communication path 54 up and down (that is, from the other end to the opposite end and the other end from the other end), the electric quantity at a more accurate timing by the sampling synchronization process based on the voltage phase difference Sampling can be performed. As a result, the protection characteristics of the transmission line by the current differential relay are improved.

As shown by the graph 60 of FIG. 4A, under the influence of the load current, a voltage difference occurs between the A terminal voltage V1 and the B terminal voltage Vs1. The sampling synchronization method that can be applied also in this case will be described below with reference to FIGS. 7 to 14 as the first embodiment.

In addition, when there is no system failure in a transmission line and the load current which flows through a transmission line is negligibly small, only a charging current flows through the current transformers CT1 and CT2 provided in A stage and B stage. Therefore, the threshold value of current detection in the current differential relay 53 is set in advance so as not to detect this charging current (that is, slightly larger than the magnitude of the charging current). When the load current cannot be detected (i.e., below the threshold), the phase difference is calculated from the voltages at both ends of the power transmission line 50, and the time corresponding to the phase difference (Equation (8) described above) is used. It is possible to detect the difference between the up and down of the transmission time of the communication path 54 almost accurately. Therefore, when the current values at both ends of the power transmission line 50 do not exceed the threshold value, it is 2x the transmission time of the transmission line 50 up and down by using the time t corresponding to the phase difference previously measured by the above-described method. Assuming that there is a difference in t, timing synchronization processing based on the time interval between the transmission time and the reception time of the timing signal can be executed.

<Sampling Synchronization Method of Embodiment 1>

In the first embodiment, by simulating the power transmission line 50 in a π-type circuit, it is assumed that the charging current flows in each terminal for half a minute, and at the midpoint of the power transmission line 50 using the terminal current compensated for the charging current. How to calculate the voltage of The midpoint is more generally called a specific point. In the first embodiment, the voltage at the midpoint (also referred to as the first specific point voltage) calculated using the current and voltage at stage A and the voltage at the midpoint calculated using the current and voltage at stage B (second The phase difference of the dot) is also referred to, and the sampling timing is corrected from the time corresponding to the phase difference.

In this way, by taking the charging current into the calculation, even when there is an influence of the load current, the sampling synchronization error can be made smaller. Hereinafter, with reference to the drawings will be described in detail.

[Equivalent Circuit of Transmission Line]

7 is an equivalent circuit diagram of a normal circuit of a power transmission system simulated by a π-type circuit. In addition, simulating the entire transmission line as a π-type circuit simulates the first line from the A stage to the intermediate point 57 with an L type circuit, and the second line from the B stage to the intermediate point 57 with another L. You can think of it as simulating a circuit.

Referring to FIG. 7, the normal voltage of A stage is set to V1, and the normal current of A stage is set to I1. Similarly, the normal voltage of the B stage is set to Vs1, and the normal current of the B stage is set to Is1.

The total amount of land capacity in the entire power transmission line 50 is taken as C. In the π-type circuit, a capacitor of 1/2 the size of the earth capacitance C is connected to the A stage, and a capacitor of the size of 1/2 of the earth capacitance C is connected to the A stage. As a result, the charging current Ic flows through the A stage, and the charging current Ics flows through the B stage.

The normal impedance of the entire power transmission line 50 is set to Z1. Thus, the line impedance from the A end of the power transmission line 50 to the intermediate point 57 is represented by Z1 / 2, and the line impedance from the B end of the power transmission line 50 to the intermediate point 57 is represented by Z1 / 2. do.

The voltage at the intermediate point 57 calculated from the current I1 and the voltage V1 at the A stage is set to Vf, and the voltage at the intermediate point 57 calculated from the current Is1 and the voltage Vs1 at the B stage. Let Vsf be. In addition, the position of the stage A is set to x = 0, the position of the stage B is set to x = 1, and the position of the intermediate point is set to x = 1/2.

[Charging Current]

FIG. 8 is a diagram for explaining charging current in the normal circuit of FIG. 7. Fig. 8A shows the voltage change on the power transmission line when there is a voltage difference between the self-terminal voltage V1 and the relative voltage Vs1. The graph 64 shows the voltages V1 and Vs1 as vectors (that is, represented by voltage amplitude and phase), and schematically shows the case where the phase difference is greater than the amplitude. The graph 63 is shown so that there may be a difference in the scalar (that is, only the voltage amplitude) simply.

The graph 65 of FIG. 8B shows the change of the load current on the power transmission line. In the A stage, a load current obtained by subtracting the charging current Ic flows from the terminal current I1, and in the B stage, a load current which subtracts the charging current Ics from the terminal current Is1 flows.

[Functional Configuration of Current Differential Relay]

Fig. 9 is a block diagram showing the functional configuration of the current differential relay of the first embodiment. In Fig. 9, the functional configuration of the current differential relay 53A in the A stage is shown. The same applies to the current differential relay 53B in the B stage. In addition, the functional block diagram of FIG. 9 is applied also to other embodiment mentioned later.

Functionally speaking, the arithmetic processing unit 120 of the current differential relay 53A includes a self-end data storage unit 70, a transmission data processing unit 71, a reception data processing unit 72, a synchronization processing unit 73, The voltage calculator 74, the phase difference calculator 75, and the relay calculator 76 are included. These functions are realized by executing a program by the CPU 121 of the arithmetic processing unit 120.

Referring to FIG. 9, a signal representing the current and voltage of the rosewood received by the input converter 100 is converted into a digital value by the A / D converter 110, and the rosewood data accumulator 70 is converted into a digital value. It is stored. Thereafter, the data is processed into transmission data by the transmission data processing unit 71 for transmission to the counterpart relay. The transmission data is transmitted by the transmitter TX131_1 to the receiver RX131_2 of the opposite end relay. On the other hand, the reception data (i.e., current data and voltage data of the opposite end) of the opposite end relay received by the receiver RX131_2 is calculated by the receiving data processing unit 72 in the opposite end data. Is processed.

In order to synchronize the sampling time of the data acquired by the relay of both ends of a power transmission line, the synchronization processing part 73 performs sampling synchronization process with respect to rosewood data and the counterpart data for arithmetic. Specifically, synchronization processing is performed based on the time interval between the transmission time and the reception time of the timing signal described above.

In the calculation by the voltage calculating unit 74, the above-listed rosewood data and the data of the opposite end are used. Specifically, the voltage calculating section 74 uses the current I1 and the voltage V1 of its own end to supply the voltage Vf of the specific point on the power transmission line 50 (in the case of the first embodiment, the intermediate point 57). Next, the voltage Vsf at a specific point is calculated using the current Is1 and the voltage Vs1 of the opposite end. In this calculation, the impedance Z1 of the power transmission line 50 and the ground capacitance C of the power transmission line 50 are used.

The phase difference calculating unit 75 calculates the phase difference φ between the voltage Vf of the specific point calculated based on the self-end data and the voltage Vsf of the specific point calculated based on the relative end data. The phase difference calculator 75 further calculates a time t corresponding to the calculated phase difference φ and feeds back the information of the time t to the synchronization processor 73. Alternatively, the phase difference calculating unit 75 synchronizes the difference between the transmission time of the terminal end and the opposite end and the transmission time from the opposite end to the end (i.e., 2xt when T1 = T2 in Fig. 6A). 73 may be fed back.

The synchronization processing unit 73 performs sampling synchronization processing on the self-end data and the counter end data for the calculation based on the transmission time difference detected by the phase difference calculation unit 75. Specifically, as described with reference to Fig. 6B, the time interval between the transmission time and the reception time of the timing signal in the A stage is T3, and the time interval between the transmission time and the reception time of the timing signal in the B stage is determined. When T4 is set, the sampling timing is adjusted so that the time interval T3 and the time interval T4 differ by the transmission time difference. Alternatively, the synchronization processing unit 73 does not base the sampling time on the basis of the time difference corresponding to the phase difference φ (that is, so that the time corresponding to the current phase difference φ becomes zero). You may correct it.

In addition, when the counterpart relay is a master (when it is a slave), the synchronization processing unit 73 is such that the time t corresponding to the phase difference φ obtained by the phase difference calculator 75 becomes zero. The sampling timing in the / D converter 110 is controlled. This synchronizes the sampling timing of the own end with the sampling timing of the other end.

The relay calculating unit 76 uses data of the current Is1 of the opposite end and the data of the own current I1 synchronized with the data of the current Is1 of the opposite end, and based on these difference currents, the transmission line ( It is determined whether a failure occurs in the protective section of 50).

Arbitrary well-known methods can be used for calculation of the phase difference in said phase difference calculating part 75.

For example, the sampling intervals of the voltages Vf and Vsf are set to every 30 degrees, the present values of the voltages Vf and Vsf are set to Vf [m] and Vsf [m], respectively, and the value 90 degrees before the current point is Vf. [m-3] and Vsf [m-3]. Then, the cosine and the sine of the phase difference φ between the voltage Vf [m] and the voltage Vsf [m] use the amplitude | Vf | of the voltage Vf | and the amplitude | Vsf | of the voltage Vsf | So,

| Vf | × | Vsf | × cosφ = Vf [m] × Vsf [m] + Vf [m-3] × Vsf [m-3]. (9)

| Vf | x | Vsf | xsinphi = Vf [m-3] xVsf [m] -Vf [m] xVsf [m-3]. 10

Is displayed.

[Sampling Synchronization Order-Part 1]

FIG. 10 is a flowchart showing a procedure of sampling synchronization processing according to the first embodiment. Hereinafter, with reference to FIGS. 7, 9, and 10, the order of sampling synchronization processing will be described in more detail. In the following description, the A stage will be referred to as the rosewood and the B stage will be referred to as the opposite stage.

First, the A / D converter 110 of FIG. 9 generates the current data I1 and the voltage data V1 by sampling current and voltage of its own end (step S101).

Next, the voltage calculator 74 calculates the charging current Ic using the self-terminal voltage V1 (step S102). If the imaginary unit is j and each frequency of the AC voltage of the power transmission line 50 is ω, the charging current Ic is

Ic = jω (C / 2) * V1... (11)

Is indicated. Here, C is the total amount of land capacity of the transmission line, and Ic represents the charging current from the edge of the line to the midpoint 57 (that is, at 1/2 of all the lines).

Next, the voltage calculating unit 74 calculates the midpoint voltage Vf by using the value I1-Ic obtained by subtracting the charging current Ic from the cutting edge current I1 and the cutting edge voltage V1. (Step S103). Specifically, the midpoint voltage Vf is

Vf = V1- (Z1 / 2) * (I1-Ic)... (12)

Is indicated. The right side claim 2 of the above expression (12) represents the voltage drop by the power transmission line 50 from the magnetic end to the intermediate point 57. As shown in FIG.

Next, the receiver 131_2 receives sampling values of the current and voltage of the opposite end (that is, the current data Is1 and the voltage data Vs1) (step S104). The received current data Is1 and the voltage data Vs1 are received by the reception data processing unit 72. In addition, you may perform step S104 before step S102. In addition, you may perform said step S102, S103 in parallel with step S105, S106.

Next, the voltage calculating part 74 calculates charging current Ics using the relative voltage Vs1 (step S105). Specifically, the charging current Ics is

Ics = jω (C / 2) * Vs1... (13)

The charging current is indicated on the track from the opposite end to the intermediate point 57 (that is, at 1/2 of all the routes).

Subsequently, the voltage calculating unit 74 uses the value Is1-Ics obtained by subtracting the charging current Ics from the relative end current Is1 and the relative end voltage Vs1, and the midpoint voltage Vsf. Is calculated (step S106). Specifically, the midpoint voltage Vsf is

Vsf = Vs1- (Z1 / 2) * (Is1-Ics)... (14)

Is indicated. The right side second term of the above formula (14) shows the voltage drop by the power transmission line 50 from the opposite end to the intermediate point 57.

Next, the phase difference calculating unit 75 calculates the phase difference φ between the midpoint voltages Vs and Vsf (step S107). In addition, the phase difference calculator 75 obtains a delay time (or a preceding time) corresponding to the calculated phase difference φ and outputs it to the synchronization processor 73. The synchronization processor 73 corrects the sampling time by the delay time or the preceding time (step S108). That is, the synchronization processing unit 73 controls the sampling time of the current and the voltage at its own end so that the time t corresponding to the phase difference φ becomes zero.

The midpoint voltage Vf calculated in equation (12) and the midpoint voltage Vsf calculated in equation (14) are the same voltage vectors when the sampling synchronization at both ends of the power transmission line 50 is taken. Indicates. If the sampling synchronization is not taken, a phase difference occurs between the midpoint voltages Vs and Vsf. Therefore, by measuring the phase difference and performing synchronous correction for a time corresponding to the phase difference, the sampling timing can be synchronized.

11 is a vector diagram illustrating an example of the phase difference between the midpoint voltages Vf and Vfs. In FIG. 11, the phase of the midpoint voltage Vf calculated from the self-end voltage V1 and the single-end current I1 is the midpoint voltage Vsf calculated from the relative end voltage Vs1 and the relative end current Is1. The phase is preceded by φ over the phase of. Therefore, the timing of the sampling of the own end is preceded by the phase angle φ prior to the timing of the sampling of the opposite end. Therefore, in the sampling synchronization processing, the time t corresponding to the phase difference φ of the rosewood sampling time, that is,

t = (φ / 360 °) × time of 1 cycle... (15)

Correction in the delay direction. If the alternating frequency is f, one cycle time is 1 / f [sec]. The cycle time of one cycle is represented by 1 / f when the AC frequency is f.

By performing the sampling synchronization processing in the above-described order, sampling synchronization with less influence of the load current due to the voltage difference between the both ends of the power transmission line 50 becomes possible. This improves the protection characteristics of the power transmission line by the current differential relay.

[Sampling Synchronization Order-Part 2]

The sampling synchronization processing based on the above-described voltage phase difference cannot be applied when the phases of voltage and current in the A and B stages are affected by failures on the power line or the like. In addition, when at least one of the circuit breakers 68A and 68B provided in the power transmission line 50 between the A stage and the B stage or a disconnector (not shown) is open, such as when the A stage and the B stage are not in a conductive state. However, the sampling synchronization processing based on the above voltage phase difference is not applicable. The sampling synchronization processing based on the voltage phase difference is based on the premise that the absolute value of the voltage phase difference to be measured is less than 180 degrees and cannot be applied when the deviation width of the timing to be synchronized is too large.

In such a case, as described with reference to Figs. 6A and 6B, the sampling synchronization processing can be executed by combining the sampling synchronization method based on the time interval between the transmission time and the reception time of the timing signal. Hereinafter, with reference to FIG. 1, FIG. 9, FIG. 12, it demonstrates concretely. In addition, the following procedure is similarly applicable to other embodiment mentioned later.

12 is a flowchart showing another sampling synchronization procedure. In the initial state, a failure does not occur in the power transmission line 50, and the breaker, the disconnector, and the like provided between the terminals are in a closed state.

First, in step S701, the transmitter 131_1 of the current differential relay 53A in the A stage transmits a timing signal to the current differential relay 53B in the B stage together with the current data and the voltage data of its own stage. Similarly, the transmitter 131_1 of the current differential relay 53B at stage B transmits a timing signal to the current differential relay 53A at stage A together with the current data and the voltage data of the terminal stage.

In the following step S702, the receiver 131_2 of the current differential relay 53A in the A stage receives a timing signal together with the current data and the voltage data from the opposite stage. Similarly, the receiver 131_2 of the current differential relay 53A at the stage B receives a timing signal together with the current data and the voltage data from the counterpart.

In addition, each of the current differential relays 53A and 53B calculates a time interval between the transmission time of the timing signal from its own end and the reception time of the timing signal from the other end. The current differential relays 53A and 53B transmit the time intervals of the calculated timing signal transmission time and the reception time to face each other. The calculation of this time interval and the transmission of the calculation result may be, for example, about once per cycle of the power system.

In the next step S703, the synchronization processing unit 73 of the current differential relay 53A at the A stage is time interval T1 between the transmission time and the reception time of the timing signal at its own end side, and the transmission time of the timing signal at the other end side. The sampling time of the current and voltage in the A / D converter 110 of the current differential relay 53A in the A stage is controlled so that the time interval T2 of the reception time is equal.

As a result, when it is determined that synchronization has been achieved, that is, when the time interval T1 and the time interval T2 are equal (YES in step S704), then in step S705, the current differential relay 53A at the A stage. The phase difference calculating unit 75 of FIG. 10 performs the specification based on the specific point voltage Vs based on the current data and the voltage data of its own end and the current data and the voltage data on the other end, as described above in steps S101 to S107 of FIG. The phase difference φ of the point voltage Vsf is calculated. Here, the specific point is an intermediate point between the A stage and the B stage. The synchronization processor 73 stores the time t corresponding to the phase difference φ in a memory (for example, the RAM 122 or the ROM 123 of FIG. 2) as a specific time interval Ts. do. As described with reference to Figs. 6A and 6B, twice the specific time interval Ts represents the transfer time of the communication path from the A stage to the B stage and the transmission time of the communication path from the B stage to the A stage. Corresponds to the car.

Then, similarly to the case of steps S701 and S702, first, in step S706, the transmitter 131_1 of the current differential relay 53A in stage A transmits a timing signal together with the current data and voltage data of its stage, and the current in stage B. Transmit to differential relay 53B. Similarly, the transmitter 131_1 of the current differential relay 53B at stage B transmits a timing signal to the current differential relay 53A at stage A together with the current data and the voltage data of the terminal stage.

In following step S707, the receiver 131_2 of the current differential relay 53A of A stage receives a timing signal with current data and voltage data from a counterpart. Similarly, the receiver 131_2 of the current differential relay 53A at the stage B receives a timing signal together with the current data and the voltage data from the counterpart.

In addition, each of the current differential relays 53A and 53B calculates a time interval between the transmission time of the timing signal from its own end and the reception time of the timing signal from the other end. The current differential relays 53A and 53B transmit the time intervals of the calculated timing signal transmission time and the reception time to face each other. The calculation of this time interval and the transmission of the calculation result may be, for example, about once per cycle.

Synchronization processing is executed in the following steps S708 to S711. The execution frequency of this synchronization process may be about once every several cycles, for example.

More specifically, in step S708, the synchronization processing unit 73 of the current differential relay 53A at the A stage includes the time interval T1 between the transmission time and the reception time of the timing signal at its own end side, and the transmission time of the timing signal at the other end side. The current and voltage at the A / D converter 110 of the current differential relay 53A at stage A are different so that the time interval T2 of the reception time differs by twice the specific time interval Ts obtained in step S705. Controls the sampling time of

For example, in the above-described step S705, the specific point voltage Vsf based on the current data and the voltage data of the B stage is higher than the specific point voltage Vs based on the current data and the voltage data of the A stage. φ) is said to be preceded. In this case, as described with reference to Fig. 6A, the transmission time through the communication path 54 from the A stage to the B stage is 2x more than the transmission time through the communication path 54 from the B stage to the A stage. Only Ts is long. Therefore, the sampling timing at the A stage is controlled so that the time interval T1 is shorter by 2 x Ts than the time interval T2.

Conversely, in the above-described step S705, the specific point voltage Vsf based on the current data and the voltage data of the B stage is higher than the specific point voltage Vs based on the current data and the voltage data of the A stage. Delayed by). In this case, the transmission time through the communication path 54 from the A stage to the B stage is shorter by 2 x Ts than the transmission time through the communication path 54 from the B stage to the A stage. Therefore, the sampling timing at the A stage is controlled so that the time interval T1 is longer by 2 x Ts than the time interval T2.

When it is determined that synchronization is achieved by the execution of step S708, that is, when the difference between the time interval T1 and the sensory interval T2 is equal to 2 x Ts (YES in step S709), the power line is broken. If this does not occur and the breaker or the like between both ends of the power transmission line is not opened (NO in step S710), the flow proceeds to step S711 for correcting the above-described specific time interval Ts. The reason for correcting the specific time interval Ts as described above may be due to the influence of measurement error, jitter, wonder, and fluctuations in device characteristics (e.g., fluctuation in clock, etc.). This is because the transmission time difference (2 x Ts) obtained in S705 may vary. For other reasons, if an abnormality occurs in the transmission path between the current differential relay 53A at the A stage and the current differential relay 53B at the B stage, the transmission route may be changed. This is because there is a possibility that the change of the transmission time difference is accompanied.

In step S711, the phase difference calculating unit 75 of the current differential relay 53A in the A stage is characterized by the specific point voltage Vs based on the current data and the voltage data of its own stage and the specific point based on the current data and the voltage data of the other stage. The phase difference phi of the voltage Vsf is calculated. Here, the specific point is an intermediate point between the A stage and the B stage. Then, the synchronization processor 73 corrects the specified time interval Ts by adding or subtracting the time t 'corresponding to the phase difference φ to the current specified time interval Ts. A more detailed correction method will be described later with reference to FIG. 14.

Thereafter, steps S706 to S711 are repeated. Therefore, step S708 is executed using the specific time interval Ts corrected in step S711. In addition, when a failure does not occur in a power transmission line and the breaker etc. between both ends of a power transmission line are not open (NO in step S710), step S711 is repeatedly performed, and the specific time interval Ts is continuously corrected.

On the other hand, if a failure occurs in the transmission line, or a breaker between both ends of the transmission line is open (YES in step S710), step S711 for correcting the specific time interval Ts is not executed, and the transmission line fails. The synchronization process of step S708 is continued using the specific time interval Ts corrected immediately before generation or just before opening of the breaker or the like.

Here, the failure of the power transmission line 50 may be detected by the current differential relays 53A and 53B, or may be detected by another method. For example, a sudden change in terminal current may be detected by a current change width relay, or a failure detection signal may be received from another protection relay. In the open / close states of the breakers 68A and 68B and disconnectors not shown, the current differential relays 53A and 53B receive signals indicating the open / close states output from the breakers 68A and 68B and the disconnectors. It may be detected.

According to the above procedure shown in FIG. 12, even when a failure occurs in the transmission line or when a breaker or the like provided between both ends of the transmission line is opened, sampling synchronization processing with higher accuracy than before can be realized. In addition, in the above, it demonstrated if the current differential relay 53A of the A stage is a slave side, and the current differential relay 53A of the A stage adjusts the sampling timing of its own stage. Conversely, the current differential relay 53B at stage B may adjust the sampling timing of the terminal stage.

FIG. 13 is a diagram for explaining the procedure of step S711 of FIG. 12 in more detail. 13A to 13D are based on Figs. 6A and 6B.

First, referring to FIG. 6 (A), the time interval T1 of the transmission time t1 and the reception time t3 of the timing signal at the A stage, the transmission time t2 of the timing signal at the B stage, and Assume that the time interval T2 at the reception time t4 is equivalent. At this time, when the specific point voltage Vs based on the voltage data and the current data at the A stage is compared with the specific point voltage Vsf based on the voltage data and the current data at the B stage, the specific point voltage Vsf becomes It is assumed that the phase difference φ is preceded by the specific point voltage Vs. In this case, when the time corresponding to the phase difference phi is t, the transmission time from the A stage to the B stage via the communication path is 2xt longer than the transfer time from the B stage to the A stage. In this specification, t in this case (that is, 1/2 of the transmission time difference) is referred to as a specific time interval Ts.

Therefore, in the case of Fig. 6A, as shown in Fig. 6B, the time interval T1 between the transmission time and the reception time of the timing signal at stage A (corresponding to T3 in Fig. 6B). 2xTs (corresponding to 2xt in FIG. 6 (B)), and the time interval T2 between the transmission time and the reception time of the timing signal at the B stage (in T4 of FIG. 6B). Sampling synchronization can be realized by controlling the sampling timing in the A stage or the B stage so that the correspondence is equal. However, even if the correction is performed such that T1 + 2 x Ts = T2 due to the influence of measurement error, jitter, wonder, fluctuations in device characteristics (for example, clock fluctuation, etc.), signal fluctuations, and the like. In normal cases, complete sampling synchronization is not continuously realized. In addition, when an abnormality occurs in the communication path between the transmission device at the A stage and the transmission device at the B stage, the transmission route may be switched, and in this case, there is a possibility that a change in the transmission time difference between up and down occurs. Therefore, the accuracy of the sampling synchronization is increased by continuously correcting the specific time interval Ts. Hereinafter, it demonstrates in detail with reference to FIG.13 (A)-(D).

Referring to Fig. 13A, similarly to the case of Fig. 6B, the sampling timing at the A stage or the B stage is adjusted so that T1 + 2 x Ts = T2. In this case, the specific point voltage Vs based on the voltage data and current data at A stage and the specific point voltage Vsf based on the voltage data and current data at B stage are compared. It is assumed that Vsf precedes the specific point voltage Vs by the phase difference φ. When the time corresponding to the phase difference phi is t ', this means that the sampling timing of the B stage is delayed by t' than the sampling timing of the A stage.

Therefore, as shown in Fig. 13B, the sampling synchronization can be realized by controlling the sampling timing at the A stage or the B stage such that T1 + 2 x Ts + 2 x t '= T2. In other words, the sampling synchronization can be realized by correcting the specific time interval Ts to add the time t '(that is, by correcting Ts' = Ts + t 'when the specified time interval after correction is Ts'). Can be.

Referring to Fig. 13C, as in the case of Fig. 6B, the sampling timing at the A stage or the B stage is adjusted so that T1 + 2 x Ts = T2. In this case, the specific point voltage Vs based on the voltage data and current data at stage A and the specific point voltage Vsf based on the voltage data and current data at stage B are compared. Conversely, the specific point voltage Vsf is delayed by the phase difference φ from the specific point voltage Vs. When the time corresponding to the phase difference phi is t ', this means that the sampling timing of the B stage is earlier than the sampling timing of the A stage by t'.

Therefore, as shown in Fig. 13D, the sampling synchronization can be realized by controlling the sampling timing in the A stage or the B stage such that T1 + 2 x Ts-2 x t '= T2. In other words, sampling synchronization can be realized by correcting the specific time interval Ts so as to subtract the time t '(i.e., correcting the specified time interval after correction to Ts' by Ts '= Ts-t'). Can be.

In addition, in the case of a phase relationship opposite to the above example, it will be readily understood by those skilled in the art that the above description is almost as it is when the A stage and the B stage are replaced in the above description.

[Sampling Synchronization Order-HE 3]

14 is a flowchart showing still another sampling synchronization procedure. The sampling synchronization procedure of FIG. 14 shows a modification of the sampling synchronization procedure of FIG. 12, and is characterized in that only the synchronization processing based on the voltage phase difference is performed during normal transmission line.

Referring to Fig. 14, in the initial state, no failure occurs in the power transmission line 50, and the breaker or the like provided between the terminals is said to be in the closed state.

First, in step S801, the transmitter 131_1 of the current differential relay 53A in the A stage transmits a timing signal to the current differential relay 53B in the B stage together with the current data and the voltage data of the own stage. Similarly, the transmitter 131_1 of the current differential relay 53B at stage B transmits a timing signal to the current differential relay 53A at stage A together with the current data and the voltage data of the terminal stage.

In the next step S802, the receiver 131_2 of the current differential relay 53A in the A stage receives a timing signal together with the current data and the voltage data from the opposite stage. Similarly, the receiver 131_2 of the current differential relay 53A at the stage B receives a timing signal together with the current data and the voltage data from the counterpart.

In addition, each of the current differential relays 53A and 53B calculates a time interval between the transmission time of the timing signal from its own end and the reception time of the timing signal from the other end. The current differential relays 53A and 53B transmit time intervals of the calculated timing signal transmission / reception time to each other. The calculation of this time interval and the transmission of the calculation result may be, for example, about once per cycle.

In the next step S803, the synchronization processing unit 73 of the current differential relay 53A in stage A is provided with a time interval T1 between the transmission time and the reception time of the timing signal on its own end side, and the transmission time of the timing signal on the other end side. The sampling time of the current and voltage in the A / D converter 110 of the current differential relay 53A in the A stage is controlled so that the time interval T2 of the reception time is equal.

As a result, when the time interval T1 and the time interval T2 are equal (YES in step S804), in the next step S805, the synchronization processing unit 73 of the current differential relay 53A in the A stage is described in the above-described FIG. As described in steps S101 to S107 in step 10, the phase difference φ between the specific point voltage Vs based on the current data and the voltage data of the terminal and the specific point voltage Vsf based on the current data and the voltage data of the other end is determined. Calculate Here, the specific point is an intermediate point between the A stage and the B stage. Then, the synchronization processing unit 73 stores the time corresponding to the phase difference φ in a memory (for example, the RAM 122 or the ROM 123 of FIG. 2) as the specific time interval Ts.

Subsequently, in step S806, the synchronization processing unit 73 controls the sampling timing of the current and the voltage at the magnetic end side such that the time t corresponding to the phase difference φ between the specific point voltages Vs and Vsf becomes zero. . When the power transmission line 50 is normal, sampling synchronization processing based on this voltage phase difference is repeated.

Next, a failure of the power transmission line 50 is detected, or the breakers 68A, 68B and the like between the A stage and the B stage are opened (YES in step S807). If there is a power line failure or the breaker is opened between both ends (YES in step S807), the synchronization processing unit 73 cannot continue the timing synchronization processing based on the voltage phase difference, and thus the time interval between the transmission time and the reception time of the timing signal. Switch to timing synchronization processing according to the above.

Specifically, in step S808, the transmitter 131_1 of the current differential relay 53A in the A stage transmits a timing signal to the current differential relay 53B in the B stage together with the current data and the voltage data of the own stage. Similarly, the transmitter 131_1 of the current differential relay 53B at stage B transmits a timing signal to the current differential relay 53A at stage A together with the current data and the voltage data of the terminal stage.

In following step S809, the receiver 131_2 of the current differential relay 53A of A stage receives a timing signal with current data and voltage data from a counterpart. Similarly, the receiver 131_2 of the current differential relay 53A at the stage B receives a timing signal together with the current data and the voltage data from the counterpart. As in step S802, each of the current differential relays 53A and 53B calculates a time interval between the transmission time of the timing signal from its own end and the reception time of the timing signal from the other end. The current differential relays 53A and 53B transmit time intervals of the calculated timing signal transmission / reception time to each other.

In the next step S810, the synchronization processing unit 73 of the current differential relay 53A at the A stage is time interval T1 between the transmission time and the reception time of the timing signal at its own end, and the transmission time of the timing signal at the other end. Current and voltage at the A / D converter 110 of the current differential relay 53A at stage A so that the time interval T2 of the reception time is different by twice the specific time interval Ts obtained in step S805. Controls the sampling time of

As a result, even when transmission line failure or opening of the breaker between both ends occurs, sampling synchronization processing with higher accuracy than before can be realized. In addition, in the above, it demonstrated if the current differential relay 53A of the A stage is a slave side, and the current differential relay 53A of the A stage adjusts the sampling timing of its own stage. Conversely, the current differential relay 53B at stage B may adjust the sampling timing of the terminal stage.

<Modification of Embodiment 1>

In the above description, the intermediate point 57 on the power transmission line 50 is defined as a specific point, and the voltage at the specific point is calculated from the respective terminal voltage and the terminal current. However, the relay installation point may be used without being limited to the intermediate point. Any point on (50) can be set as the specific point 67. A description with reference to the drawings is as follows. In addition, it is preferable to make the specific point 67 into an intermediate point on calculation precision.

FIG. 15 is an equivalent circuit diagram of the normal circuit of the power transmission system to which the sampling synchronization process according to the modification of Embodiment 1 is applied. Since the equivalent circuit diagram of FIG. 15 deforms the equivalent circuit diagram of FIG. 7, the same reference numerals are attached to the parts common to those of FIG. In addition, let the position of the specific point 67 on the power transmission line 50 be x = m (0 <= m <= 1). In addition, in the following description, A stage is called a rosewood and B stage is called a counterpart.

Since the transmission line 50 is simulated by a π-type circuit, the ground capacity is arranged at both ends of the transmission line. Therefore, each of the earth capacity arranged in the rosewood and the earth capacity arranged in the opposite end becomes 1/2 of the total capacity C of the power transmission line 50 regardless of the length from the rosewood to the specific point 67. Therefore, the charging current Ic flowing in the rosewood is

Ic = jω (C / 2) * V1... (16)

Is displayed. The voltage Vf at the specific point 67 can be calculated by using the values I1-Ic obtained by subtracting this charging current Ic from the rosewood current I1 and the rosewood voltage V1. The voltage Vf at the specific point 67 is

Vf = V1-Z1 * m * (I1-Ic)... (17)

Is indicated. The right side claim 2 of the above expression (12) has shown the voltage drop by the power transmission line 50 from the magnetic end to the specific point 67. As shown in FIG.

Similarly, it is assumed that there is 1/2 of C of the overall capacity of the entire line at the opposite end, and the charging current Ics flowing at the opposite end is

Ics = jω (C / 2) * Vs1... (18)

Is indicated. The voltage at the specific point 67 can be calculated using the values Is1-Ics obtained by subtracting this charging current Ics from the relative end current Is1 and the relative voltage Vs1. Specifically, the midpoint voltage Vsf is

Vsf = Vs1-Z1 * (1-m) * (Is1-Ics)... (19)

Is indicated. The right side claim 2 of the above expression (14) represents the voltage drop by the power transmission line 50 from the opposite end to the specific point 67. FIG.

Therefore, at a time t corresponding to the phase difference φ between the voltage Vf of the specific point 67 represented by the above expression (17) and the voltage Vsf of the specific point 67 represented by the above expression (19). Based on this, the synchronous processing of the sampling timing can be performed.

Embodiment 2.

In Embodiment 1, the transmission line is simulated by a π-type circuit, the charging current is calculated using the terminal voltage of the transmission line when there is no system failure, and the intermediate point is obtained by using the terminal current and the terminal voltage whose charging current is compensated for. The voltage was calculated. Then, the phase difference φ of the midpoint voltage Vf based on the voltage and current of the A stage and the midpoint voltage Vsf based on the voltage and current of the B stage is calculated, and the corresponding phase difference φ is calculated. The sampling time was corrected based on the time t.

In Embodiment 2, a power transmission line circuit is simulated by a T-type circuit. The T-type circuit is a model in which a capacitor corresponding to the ground capacitance C for generating a charging current is provided at the midpoint of the power transmission line, and the capacitor is inserted at half the line impedance of the power transmission line. The capacitor point to which the capacitor is connected is not limited to the intermediate point, and may be any point between the A and B stages, but the intermediate point is preferable for accuracy.

In Embodiment 2, the voltage at stage B as a specific point is further calculated based on the current and voltage at stage A, and the phase difference between the calculated stage B voltage and the actual stage B voltage is calculated. By simulating a transmission line in a T-type circuit, the load current can take into account the voltage drop caused by the flow of the transmission line and the charging current due to the earth capacitance in the calculation, thereby achieving a higher accuracy sampling synchronization than before.

[When a transmission line is simulated as a single T-type circuit]

Fig. 16 is an equivalent circuit diagram of the normal circuit of the power transmission system to which the sampling synchronization processing according to the second embodiment is applied. Referring to Fig. 16, the normal voltage of A stage is set to V1, and the normal current of A stage is set to I1. Similarly, the normal voltage of the B stage is set to Vs1, and the normal current of the B stage is set to Is1.

Let C be the total amount of land capacity in the entire power transmission line 50. In the T-type circuit, a capacitor corresponding to the ground capacitance C is connected to the intermediate point 57. The capacitor point to which the capacitor is connected is not limited to the intermediate point, and may be any point between the A and B stages, but the intermediate point is preferred for accuracy.

When the normal impedance of the entire power transmission line 50 is Z1, the line impedance from the A end of the power transmission line 50 to the intermediate point 57 is represented by Z1 / 2, and the midpoint from the B end of the power transmission line 50. The line impedance up to 57 is represented by Z1 / 2. The T-type circuit 80 is configured by the capacitor corresponding to the above ground capacitance C and the two line impedances Z1 / 2.

FIG. 17 is a flowchart showing a procedure of sampling synchronization processing according to the second embodiment. FIG. Hereinafter, with reference to FIG. 9, FIG. 16, and FIG. 17, the procedure of a sampling synchronization process is demonstrated mainly. In the following description, the A stage is referred to as the rosewood and the B stage is referred to as the opposite stage.

First, the A / D converter 110 of FIG. 9 generates the current data I1 and the voltage data V1 by sampling current and voltage of its own end (step S201). The receiver 131_2 receives the current data Is1 and the voltage data Vs1 which are sampling values of current and voltage at the opposite ends (step S202). In addition, only the voltage data Vs1 may be received when only the phase difference between the voltages at both ends is calculated and the current data Is1 at the other end is not needed.

Next, the voltage calculating part 74 calculates the voltage Vt of the intermediate point 57 (also called a capacitor point) using the terminal voltage V1 and the terminal current I1 (step S203). Specifically, the voltage Vt is

Vt = V1- (Z1 / 2) * I1... 20

Is displayed. The right side claim 2 of the above expression (20) has shown the voltage drop by the power transmission line 50 from the magnetic end to the intermediate point 57. As shown in FIG.

Next, the voltage calculation unit 74 calculates the charging current Ict using the voltage Vt at the condenser point (step S204). Specifically, the charging current Ict is

Ict = jωC * Vt... (21)

Is indicated.

Subsequently, the voltage calculating unit 74 uses the value I1-Ict obtained by subtracting the charging current Ict from the terminal current I1 and the voltage Vt at the capacitor point. ) Is calculated (step S205). Specifically, the relative voltage Vs1 'is

Vs1 '= Vt- (Z1 / 2) * (I1-Ict)... (22)

Is displayed. The right side second term of the expression (22) represents the voltage drop by the power transmission line 50 from the intermediate point 57 to the opposite end. That is, the synchronization processing unit 73 controls the sampling time of the current and the voltage at its own end so that the time t corresponding to the phase difference φ becomes zero. The sampling synchronization method described in FIG. 14 can also be applied to the case of this embodiment.

Next, the phase difference calculating unit 75 calculates the phase difference φ between the actually detected relative terminal voltage Vs1 and the calculated relative terminal voltage Vs1 '(step S206). The phase difference calculating unit 75 obtains the delay time (or the preceding time) in response to the above-described phase difference φ and outputs the delay time to the synchronization processing unit 73. The synchronization processing unit 73 corrects the sampling time by the delay time or the preceding time (step S207).

As described above, by simulating a transmission line in a T-type circuit, the load current can take into account the voltage drop caused by the flow of the transmission line and the charging current due to the earth capacitance in the calculation. It can be realized. In addition, the accuracy of sampling synchronization can be increased by increasing the number of T-type circuits.

[When a transmission line is simulated by a two-stage T-type circuit]

18 is an equivalent circuit diagram of a normal circuit of a power transmission system in the case of simulating a power transmission line in a two-stage T-type circuit.

Referring to Fig. 18, the first stage T-type circuit 81 includes a capacitor having a ground capacitance of C / 2 provided at the first condenser point 56, which is a point of x = 1/4 of the transmission line, and the condenser point. It contains line impedance of Z1 / 4 connected to each side. The T-type circuit 82 of the second stage is connected to a capacitor having a ground capacitance of C / 2 provided at the second capacitor point 58 at the point of x = 3/4 of the transmission line, and to both sides of the capacitor point. Includes line impedance of size Z1 / 4. The voltage at the first capacitor point 56 is set to Vt, and the charging current at the first capacitor point 56 is set to Ict. The voltage at the second capacitor point 58 is set to Vt ', and the charging current at the second capacitor point 58 is set to Ict'. In addition, the line lengths of two stage T-type circuits do not need to be the same. In the case where the line lengths of the two-stage T-type circuits are different, the earth capacitance proportional to the line length of each T-type circuit may be at the midpoint of each line.

FIG. 19 is a flowchart illustrating a sampling synchronization procedure of a power transmission system simulated by the equivalent circuit of FIG. 18. Hereinafter, with reference to FIG. 9, FIG. 18, and FIG. 19, the procedure of a sampling synchronization process is demonstrated mainly. In the following description, the A stage is referred to as the rosewood and the B stage is referred to as the opposite stage.

The A / D converter 110 of FIG. 9 generates the current data I1 and the voltage data V1 by sampling the current and the voltage of the own terminal (step S301). The receiver 131_2 receives the current data Is1 and the voltage data Vs1 which are sampling values of current and voltage of the opposite end (step S302). In addition, only the voltage data Vs1 may be received when only the phase difference between the voltages at both ends is calculated and the current data Is1 at the other end is not needed.

Next, the voltage calculating part 74 calculates the voltage Vt of the 1st condenser point x = 1/4 using the terminal voltage V1 and the terminal current I1 (step S303). Specifically, the voltage Vt is

Vt = V1- (Z1 / 4) * I1... (23)

Is displayed. The right side second term of the above formula (23) shows the voltage drop by the power transmission line 50 from the magnetic end to the first condenser point 56.

Next, the voltage calculating part 74 calculates the charging current Ict at the 1st condenser point 56 using the voltage Vt of the above formula 23 (step S304). Specifically, the charging current Ict is

Ict = jω (C / 2) * Vt... (24)

Is indicated.

Next, the voltage calculating section 74 uses the value I1-Ict obtained by subtracting the charging current Ict from the algal current I1 and the voltage Vt of the first condenser point 56. The voltage Vt 'of the second condenser point 58 (x = 3/4) is calculated (step S305). Specifically, the voltage Vt 'is

Vt '= Vt-((Z1 / 4) + (Z1 / 4)) * (I1-Ict)

= Vt− (Z 1/2) * (I 1 -Ict). (25)

Is indicated. The second document on the right side of the equation (25) shows the voltage drop at the power transmission line 50 between the first condenser point 56 and the second condenser point 58.

Next, the voltage calculating part 74 calculates the charging current Ict 'at the 2nd condenser point 58 using the voltage Vt' of the above formula (25) (step S306). Specifically, the charging current Ict 'is

Ict '= jω (C / 2) * Vt'... (26)

Is displayed.

Subsequently, the voltage calculating section 74 subtracts the charging currents Ict and Ict 'from the algal current I1 and the value I1-Ict-Ict' and the voltage Vt 'of the second capacitor point. Calculate the voltage Vs1 'of the opposite end using (step S307). Specifically, the voltage Vs1 'at the opposite end is

Vs1 '= Vt'-(Z1 / 4) * (I1-Ict-Ict ')... (27)

Is indicated. The right side claim 2 of the equation (27) shows the voltage drop by the power transmission line 50 from the second capacitor point 58 to the opposite end.

Next, the phase difference calculating unit 75 calculates the phase difference φ between the actually detected relative terminal voltage Vs1 and the calculated relative terminal voltage Vs1 '(step S308). In addition, the phase difference calculating unit 75 obtains the delay time (or the preceding time) corresponding to the above phase difference φ and outputs it to the synchronization processing unit 73. The synchronization processor 73 corrects the sampling time by the delay time or the preceding time (step S309). That is, the synchronization processing unit 73 controls the sampling time of the current and the voltage at its own end so that the time t corresponding to the phase difference φ becomes zero. The sampling synchronization method described in FIG. 14 can also be applied to the case of this embodiment.

In this way, by increasing the number of T-type circuits, it is possible to be closer to the distributed constant line that simulates the actual transmission line, so that the accuracy of the sampling synchronization can be further increased. Further, in the second embodiment, since the charging current can be compensated based on the voltage difference between the both ends of the power transmission line 50, sampling synchronization can be corrected continuously in a state where there is no failure in the power transmission line. When a system failure occurs, sampling synchronization processing is performed using the result of the latest synchronization processing in the absence of system failure (that is, by pre-holding).

[Modification of Embodiment 2]

In the above, the voltage calculating part 71 of the current differential relay 53A calculates the voltage Vs1 'of the opposite end using the current data I1 and voltage data V1 of the magnetic end of a transmission line, and calculates the phase difference calculating part ( 72) calculated the phase difference (phi) between the calculation result and the actual voltage value Vs1 of the opposite end. On the contrary, the voltage calculation unit 71 of the current differential relay 53A calculates the voltage V1 'of its own end using the current data Is1 and the voltage data Vs1 of the opposite end of the power transmission line, and the phase difference calculating unit. 72 may calculate the phase difference (phi) of the calculation result and the actual voltage value V1 of the magnetic end of a transmission line. In this manner as well, since the sampling timing of the rosewood can be adjusted based on the time t corresponding to the phase difference φ, the sampling synchronization can be executed with higher accuracy than before.

Embodiment 3.

In Embodiment 2, the voltage of stage B is calculated using the current and voltage of stage A, and the calculated voltage of stage B is compared with the voltage of stage B actually detected. In the third embodiment, as described with reference to FIGS. 7 and 10 of the first embodiment, the midpoint voltage Vf is calculated using the current and voltage at the A stage, and the intermediate is obtained using the current and the voltage at the B stage. Calculate the point voltage (Vsf). Then, sampling synchronization processing is performed based on the calculated phase difference between the midpoint voltages Vf and Vsf.

In addition, the specific point arbitrarily determined between A terminal and B terminal may be sufficient as it, and in this case, the intermediate point voltage Vf is called 1st specific point voltage Vf, and the intermediate point voltage Vsf Is referred to as a second specific point voltage Vsf. In addition, the power transmission line 50 is simulated by the two-stage T-type circuit similarly to FIG. 18 of Embodiment 2. As shown in FIG. Thereby, precision can be improved rather than the case of Embodiment 1. FIG.

20 is an equivalent circuit diagram of a normal circuit of a power transmission system to which the sampling synchronization processing of Embodiment 3 is applied. The equivalent circuit diagram of FIG. 20 corresponds to the equivalent circuit diagram of FIG. 18, and the power transmission line 50 is simulated by two stage T-type circuits 81 and 82. The voltage at the first capacitor point 56 is set to Vt, and the charging current at the first capacitor point 56 is set to Ict. The voltage at the second capacitor point 58 is set to Vts, and the charging current at the second capacitor point 58 is set to Icts. In addition, the voltage at the intermediate point 57 based on the current I1 and voltage V1 at the A stage is set to Vf, and the intermediate point 57 based on the current Is1 and the voltage Vs1 at the B stage. Let V is the voltage at.

21 is a flowchart showing a sampling synchronization procedure of a power transmission system simulated by the equivalent circuit of FIG. 20. Hereinafter, with reference to FIG. 9, FIG. 20, FIG. 21, the procedure of a sampling synchronization process is demonstrated. In the following description, the A stage is referred to as the rosewood and the B stage is referred to as the opposite stage.

First, the A / D converter 110 of FIG. 9 generates the current data I1 and the voltage data V1 by sampling current and voltage of its own end (step S401).

Next, the voltage calculating part 74 calculates the voltage Vt of the 1st condenser point x = 1/4 using the terminal voltage V1 and the terminal current I1 (step S402). Specifically, the voltage Vt is

Vt = V1- (Z1 / 4) * I1... (28)

Is indicated. The right side claim 2 of the above expression (28) represents the voltage drop by the power transmission line 50 from the A stage to the first condenser point 56.

Next, the voltage calculating part 74 calculates the charging current Ict at the 1st condenser point 56 using the voltage Vt of the above formula 28 (step S403). Specifically, the charging current Ict is

Ict = jω (C / 2) * Vt... (29)

Is indicated.

Next, the voltage calculating section 74 uses the value I1-Ict obtained by subtracting the charging current Ict from the algal current I1 and the voltage Vt of the first condenser point 56. The midpoint voltage Vf is calculated (step S404). Specifically, the midpoint voltage Vf is

Vf = Vt− (Z 1/4) * (I 1 -Ict). (30)

Is displayed. The right side claim 2 of the above equation (30) represents the voltage drop by the power transmission line 50 from the first condenser point 56 to the intermediate point 57.

Next, the receiver 131_2 receives sampling values (that is, current data Is1 and voltage data Vs1) of current and voltage at the opposite ends (step S405). The received current data Is1 and the voltage data Vs1 are received by the reception data processing unit 72. In addition, you may perform step S405 before step S402. In addition, you may perform step S402-S404 in parallel with step S406-S408.

Next, the voltage calculating unit 74 calculates the voltage Vts of the second condenser point x = 3/4 by using the relative terminal voltage Vs1 and the relative terminal current Is1 (step S406). ). Specifically, the voltage Vts is

Vts = Vs1- (Z1 / 4) * Is1... (31)

Is indicated. The right side second term of the above formula 31 shows the voltage drop by the power transmission line 50 from the B stage to the second condenser point 58.

Next, the voltage calculating part 74 calculates the charging current Icts in the 2nd condenser point 58 using the voltage Vts of the above formula 31 (step S407). Specifically, the charging current (Icts),

Icts = jω (C / 2) * Vts... (32)

Is indicated.

Next, the voltage calculating unit 74 uses the values Is1-Icts obtained by subtracting the charging current Icts from the store current Is1 and the voltage Vts of the second condenser point 58. The midpoint voltage Vsf is calculated (step S408). Specifically, the midpoint voltage Vsf is

Vsf = Vts- (Z1 / 4) * (Is1-Icts)... (33)

Is displayed. The right side second term of the above expression 33 represents the voltage drop by the power transmission line 50 from the second capacitor point 58 to the intermediate point 57.

Next, the phase difference calculator 75 calculates the phase difference φ between the midpoint voltages Vs and Vsf (step S409). In addition, the phase difference calculator 75 obtains a delay time (or a preceding time) corresponding to the calculated phase difference φ and outputs it to the synchronization processor 73. The synchronization processing unit 73 corrects the sampling time by the delay time or the preceding time (step S410). That is, the synchronization processing unit 73 controls the sampling time of the current and the voltage at its own end so that the time t corresponding to the phase difference φ becomes zero. In addition, the sampling synchronization method described in FIG. 14 can be applied to the case of this embodiment.

In the first embodiment, if the load current increases, the error may not be ignored. In the third embodiment, the error can be reduced by configuring the intermediate point 57 from each terminal by using a T-type circuit. have. In addition, if the line from each terminal to the intermediate point 57 is constituted by a two-stage T-type circuit, the equivalent circuit becomes closer to a distribution constant, so that the accuracy of sampling synchronization can be further improved.

Fig. 22 is an equivalent circuit diagram of the normal circuit of the power transmission system in the case where two terminals from the respective terminals to the intermediate point are simulated.

Referring to FIG. 22, in the transmission line from the A stage to the intermediate point 57, the T-type circuit 83 of the first stage is provided at the first condenser point 91, which is a point at x = 1/8 of the transmission line. A capacitor having a ground capacitance of C / 4 and a line impedance of size Z1 / 8 connected to both sides of the capacitor point, respectively. The T-type circuit 84 of the second stage is connected to a capacitor having a ground capacitance of C / 4 provided at the second condenser point 93 at the point of x = 3/8 of the power transmission line, and to both sides of the condenser point, respectively. Includes line impedance of size Z1 / 8. The voltage at the first capacitor point 91 is set to Vp, and the charging current at the first capacitor point 91 is set to Icp. The voltage at the second capacitor point 93 is set to Vp ', and the charging current at the second capacitor point 93 is set to Icp'.

Similarly, in the transmission line from the B stage to the intermediate point 57, the T-type circuit 86 of the first stage has a ground capacitance provided at the third condenser point 96 at the point of x = 7/8 of the transmission line. And a line impedance of size Z1 / 8 connected to both sides of the capacitor point. The T-type circuit 85 of the second stage is connected to a capacitor having a ground capacitance of C / 4 provided at the fourth condenser point 94 at the point of x = 5/8 of the power transmission line, and to both sides of the condenser point, respectively. Includes line impedance of size Z1 / 8. The voltage at the third capacitor point 96 is set to Vps, and the charging current at the third capacitor point 96 is set at Icps. The voltage at the fourth condenser point 94 is set to Vps ', and the charging current at the fourth condenser point 94 is made at Icps'.

FIG. 23 is a flowchart illustrating a sampling synchronization procedure of a power transmission system simulated by the equivalent circuit of FIG. 22. Hereinafter, with reference to FIG. 9, FIG. 22, and FIG. 23, the procedure of a sampling synchronization process is demonstrated mainly. In the following description, the A stage is referred to as the rosewood and the B stage is referred to as the opposite stage.

First, the A / D converter 110 of FIG. 9 generates the current data I1 and the voltage data V1 by sampling current and voltage of its own end (step S501).

Next, the voltage calculating part 74 calculates the voltage Vp of the 1st condenser point 91 (x = 1/8) using the terminal voltage V1 and the terminal current I1 (step). S502). Specifically, the voltage Vp is

Vp = V1- (Z1 / 8) * I1... (34)

Is indicated. The right side claim 2 of the above expression 34 represents the voltage drop by the power transmission line 50 from the A stage to the first condenser point 91.

Next, the voltage calculating part 74 calculates the charging current Icp in the 1st condenser point 91 using the voltage Vp of the above formula 34 (step S503). Specifically, the charging current Icp is

Icp = jω (C / 4) * Vp... (35)

Is indicated.

Next, the voltage calculating unit 74 uses the value I1-Icp obtained by subtracting the charging current Icp from the magnetic current current I1 and the voltage Vp at the first condenser point 91. The voltage Vp 'at the second capacitor point 93 (x = 3/8) is calculated (step S504). Specifically, the voltage Vp 'is

Vp '= Vp− (Z 1/4) * (I 1 -Icp)... (36)

Is displayed. The right side second term of the above equation (36) represents the voltage drop by the power transmission line 50 from the first condenser point 91 to the second condenser point 93.

Next, the voltage calculating unit 74 calculates the charging current Icp 'at the second capacitor point 93 by using the voltage Vp' of the above expression 36 (step S505). Specifically, the charging current Icp 'is

Icp '= jω (C / 4) * Vp'... (37)

Is indicated.

Subsequently, the voltage calculating unit 74 subtracts the charging currents Icp and Icp 'from the multi-phase current I1 (I1-Icp-Icp') and the voltage Vp 'of the second capacitor point. The intermediate point voltage Vf is calculated using (step S506). Specifically, the midpoint voltage Vf is

Vf = Vp '-(Z1 / 8) * (I1-Icp-Icp')... (38)

Is indicated. The right side second term of the expression 38 represents the voltage drop by the power transmission line 50 from the second condenser point 93 to the intermediate point 57.

Next, the receiver 131_2 receives sampling values (that is, current data Is1 and voltage data Vs1) of current and voltage at the opposite ends (step S507). The received current data Is1 and the voltage data Vs1 are received by the reception data processing unit 72. In addition, you may perform step S507 before step S502. In addition, you may perform step S502-S506 in parallel with step S508-S512.

Next, the voltage calculating unit 74 calculates the voltage Vps of the third condenser point x = 7/8 by using the relative terminal voltage Vs1 and the relative terminal current Is1 (step S508). ). Specifically, the voltage Vps is

Vps = Vs1- (Z1 / 8) * Is1... (39)

Is indicated. The right side claim 2 of the equation 39 represents the voltage drop by the power transmission line 50 from the B stage to the third condenser point 96.

Next, the voltage calculator 74 calculates the charging current Icps at the third condenser point 96 using the voltage Vps of the above expression 39 (step S509). Specifically, the charging current (Icps),

Icps = jω (C / 4) * Vps... 40

Is displayed.

Next, the voltage calculating unit 74 uses the values Is1-Icps obtained by subtracting the charging current Icps from the relative current Is1 and the voltage Vps at the third condenser point 96. The voltage Vps' at the fourth condenser point 94 (x = 5/8) is calculated (step S510). Specifically, the voltage Vps' is

Vps' = Vps- (Z1 / 4) * (Is1-Icps)... (41)

Is indicated. The right side claim 2 of the above equation 41 represents the voltage drop by the power transmission line 50 from the third condenser point 96 to the fourth condenser point 94.

Next, the voltage calculating unit 74 calculates the charging current Icps 'at the fourth condenser point 94 by using the voltage Vps' of the above formula 41 (step S511). Specifically, the charging current Icps',

Icps '= jω (C / 4) * Vps'... (42)

Is indicated.

Next, the voltage calculating unit 74 subtracts the charging currents Icps and Icps' from the relative current Is1 and the voltage of the fourth condenser point 94. Using Vps', the midpoint voltage Vsf is calculated (step S512). Specifically, the midpoint voltage Vsf is

Vsf = Vps '-(Z1 / 8) * (Is1-Icps-Icps')... (43)

Is displayed. The right side second term of the upper expression 43 shows the voltage drop by the power transmission line 50 from the fourth capacitor point 94 to the intermediate point 57.

Next, the phase difference calculating unit 75 calculates the phase difference φ between the midpoint voltages Vs and Vsf (step S513). In addition, the phase difference calculator 75 obtains a delay time (or a preceding time) corresponding to the calculated phase difference φ and outputs it to the synchronization processor 73. The synchronization processing unit 73 corrects the sampling time by the delay time or the preceding time (step S514). That is, the synchronization processing unit 73 controls the sampling time of the current and the voltage at its own end so that the time t corresponding to the phase difference φ becomes zero. The sampling synchronization method described in FIG. 14 can also be applied to the case of this embodiment.

As described above, by increasing the number of T-type circuits, the equivalent circuit of the power transmission line 50 is brought closer by the distributed constant circuit, so that the accuracy of the sampling synchronization can be further increased. In addition, the sampling synchronization can be corrected continuously without any system failure. In addition, even if the line from each terminal to the intermediate point is simulated by three or more T-type circuits, the sampling synchronization processing can be performed in the same manner as described above.

Embodiment 4.

In the first to third embodiments, the case where the power transmission line is two terminals has been described. In the fourth embodiment, the case where the power transmission line is three terminals or more is described.

[When the power line is 3 terminals]

24 is a system diagram of a three-terminal power transmission line having a rear power supply at each terminal. In the power transmission line of FIG. 24, the A stage is connected through the branch point 200 and the power transmission line 201, the B stage is connected through the branch point 200 and the power transmission line 202, and the C stage is connected to the branch point 200 and the power transmission line. Connection is made via 203. Rear power supplies 52A, 52B, and 52C are connected to the A, B, and C stages of the power transmission line, respectively.

The current transformer CT1 is provided at the A stage, and the voltage transformer VT1 is provided at the bus line 51A of the A stage. The current transformer CT2 is provided at the B stage, and the voltage transformer VT2 is provided at the bus line 51B of the B stage. The current transformer CT3 is provided at the C stage, and the voltage transformer VT3 is provided at the bus line 51C of the C stage.

In addition, current differential relays 53A, 53B, and 53C are provided in the A, B, and C stages, respectively. Each current differential relay 53 is connected to a voltage transformer VT and a current transformer CT of its own stage. In addition, these current differential relays 53A, 53B, 53C are interconnected through the communication paths 54, 54B, 54C, and mutually exchange the detected current data and the voltage data.

FIG. 25 is an equivalent circuit diagram of a normal circuit of the power transmission system of FIG. 24. Each of the power transmission lines 201, 202, and 203 is simulated by the T-type circuits 204, 205, and 206, respectively.

In the T-type circuit 204, a capacitor having a magnitude of the earth capacitance CA of the power transmission line 201 is provided at the midpoint (also referred to as a first condenser point) 211 of the power transmission line 201. Impedances that are half of the normal impedance ZA1 of the power transmission line 201 are connected to both sides of the intermediate point 211, respectively.

Similarly, in the T-type circuit 205, a capacitor having a magnitude of the ground capacitance CB of the power transmission line 202 is provided at the midpoint (also referred to as a second capacitor point) 212 of the power transmission line 202. Impedances that are half of the normal impedance ZB1 of the power transmission line 202 are connected to both sides of the intermediate point 212, respectively.

Similarly, in the T-type circuit 206, a capacitor having a magnitude of the earth capacitance CC of the power transmission line 203 is provided at the midpoint (also referred to as a third condenser point) 213 of the power transmission line 203. Impedances that are half of the normal impedance ZC1 of the power transmission line 203 are connected to both sides of the intermediate point 213, respectively.

In the specific sampling synchronization process, the sample timing of the other two terminals is synchronized with the sample timing of any one of the three terminals. Hereinafter, the case where the sample timing of the A terminal and the C terminal is synchronized with the sample timing of the B terminal is described.

Fig. 26 is a flowchart showing a procedure for synchronizing the sample timing of the A terminal with the sample timing of the B terminal. The specific procedure is the same as in the case of FIG. 21 of the third embodiment. In FIG. 21, the midpoint voltages Vf and Vsf are calculated based on the currents and voltages of the A and B stages, respectively. In the case of FIG. 26, the branch point 200 is substituted for the midpoint 57. The voltages Vf and Vsf at are calculated.

24, 25, and 26, first, the A / D converter 110 of the current differential relay 53A samples the current data I1 and the current by sampling the current and voltage of its own stage (A stage). The voltage data V1 is generated (step S401A).

Next, the voltage calculating unit 74 of the current differential relay 53A calculates the voltage VA of the first condenser point 211 using the self-terminal voltage V1 and the self-current current I1 (step). S402A).

Next, the voltage calculating unit 74 of the current differential relay 53A calculates the charging current IAC using the voltage VA of the first capacitor point 211 (step S403A).

Next, the voltage calculating unit 74 of the current differential relay 53A includes a value I1-IAc obtained by subtracting the charging current IAc from the self-current current I1 and the voltage of the first condenser point 211 ( The branch point voltage Vf is calculated using VA) (step S404A).

Next, the receiver 131_2 of the current differential relay 53A receives a sampling value (that is, current data Is1 and voltage data Vs1) of the current and voltage of the opposite end (B stage) through the communication path 54. ) Is received (step S405A). The received current data Is1 and the voltage data Vs1 are received by the reception data processing unit 72. In addition, you may perform step S405A before step S402A. In addition, you may perform step S402A-S404A in parallel with step S406A-S408A.

Next, the voltage calculating unit 74 of the current differential relay 53A calculates the voltage VB of the second condenser point 212 using the relative end voltage Vs1 and the relative end current Is1. (Step S406A).

Next, the voltage calculating unit 74 of the current differential relay 53A calculates the charging current IBc using the voltage VB of the second condenser point 212 (step S407A).

Next, the voltage calculating unit 74 of the current differential relay 53A has a value Is1-IBc obtained by subtracting the charging current IBc from the store current Is1 and the voltage of the second capacitor point 212. The branch point voltage Vsf is calculated using (VB) (step S408A).

Next, the phase difference calculator 75 of the current differential relay 53A calculates the phase difference φ of the branch point voltages Vs and Vsf (step S409A). In addition, the phase difference calculating unit 75 of the current differential relay 53A obtains a delay time (or a preceding time) corresponding to the phase difference φ and outputs it to the synchronization processing unit 73. The synchronization processing unit 73 corrects the sampling time by the delay time or the preceding time (step S410A). That is, the synchronization processing unit 73 controls the sampling time of the current and the voltage at its own end so that the time t corresponding to the phase difference φ becomes zero. Thereby, the sample timing of the A terminal can be synchronized with the sample timing of the B terminal. In addition, the sampling synchronization method described in FIG. 14 can be applied to the above-described case.

27 is a flowchart showing a procedure for synchronizing the sample timing of the C terminal with the sample timing of the B terminal. The specific procedure is the same as in the case of FIG. 21 of the third embodiment. In the case of FIG. 27, however, the voltages Vrf and Vsf at the branch point 200 are calculated in place of the intermediate point 57.

24, 25, and 27, first, the A / D converter 110 of the current differential relay 53C samples the current data Ir1 and the current by sampling the current and voltage of its own terminal C stage. The voltage data Vr1 is generated (step S401C).

Next, the voltage calculator 74 of the current differential relay 53C calculates the voltage VC of the third condenser point 213 by using the terminal voltage Vr1 and the terminal current Ir1 (step). S402C).

Next, the voltage calculator 74 of the current differential relay 53C calculates the charging current ICc using the voltage VC of the third condenser point 213 (step S403C).

Next, the voltage calculating unit 74 of the current differential relay 53C includes a value Ir1-ICc obtained by subtracting the charging current ICc from the magnetic current current Ir1 and the voltage of the third condenser point 213. The branch point voltage Vrf is calculated using VC) (step S404C).

Next, the receiver 131_2 of the current differential relay 53C receives a sampling value (that is, current data Is1) and voltage data Vs1 of the current and voltage of the opposite end (B stage) via the communication path 54C. )) (Step S405C). The received current data Is1 and the voltage data Vs1 are received by the reception data processing unit 72. In addition, you may perform step S405C before step S402C. In addition, you may perform step S402C-S404C in parallel with step S406C-S408C.

Next, the voltage calculating unit 74 of the current differential relay 53C calculates the voltage VB of the second condenser point 212 using the relative end voltage Vs1 and the relative end current Is1. (Step S406C).

Next, the voltage calculating unit 74 of the current differential relay 53C calculates the charging current IBc using the voltage VB of the second capacitor point 212 (step S407C).

Next, the voltage calculating unit 74 of the current differential relay 53C has a value Is1-IBc obtained by subtracting the charging current IBc from the store current Is1 and the voltage of the second condenser point 212. The branch point voltage Vsf is calculated using (VB) (step S408C).

Next, the phase difference calculator 75 of the current differential relay 53C calculates the phase difference φ between the branch point voltages Vrf and Vsf (step S409C). In addition, the phase difference calculating unit 75 of the current differential relay 53C obtains a delay time (or a preceding time) corresponding to the phase difference φ and outputs it to the synchronization processing unit 73. The synchronization processing unit 73 corrects the sampling time by the delay time or the preceding time (step S410C). That is, the synchronization processing unit 73 controls the sampling time of the current and the voltage at its own end so that the time t corresponding to the phase difference φ becomes zero. Thereby, the sample timing of the C terminal can be synchronized with the sample timing of the B terminal. In addition, the sampling synchronization method described in FIG. 14 can be applied to the above-described case.

In addition, a three-terminal power transmission line can be simulated using a π-type circuit. In this case, similarly to the case of two terminals, from each terminal to the branch point is simulated as an L-type circuit which is a part of the π-type circuit.

[4 wires for transmission line]

28 is a system diagram of a four-terminal power transmission line having a rear power supply at each terminal. In the power transmission line of Fig. 28, the A stage is connected through the branch point g and the power transmission line 221, and the D stage is connected through the branch point g and the power transmission line 221. The B stage is connected through the branch point f and the power transmission line 222, and the C stage is connected through the branch point f and the power transmission line 223. FIG. The branch point g and the branch point f are connected via the power transmission line 220. Rear power supplies 52A, 52B, 52C, and 52D are connected to the A, B, C, and D stages of the power transmission line, respectively.

The current transformer CT1 is provided at the A stage, and the voltage transformer VT1 is provided at the bus line 51A of the A stage. The current transformer CT2 is provided at the B stage, and the voltage transformer VT2 is provided at the bus line 51B of the B stage. The current transformer CT3 is provided at the C stage, and the voltage transformer VT3 is provided at the bus line 51C of the C stage. The current transformer CT4 is provided at the D stage, and the voltage transformer VT4 is provided at the bus line 51D of the D stage.

In addition, current differential relays 53A, 53B, 53C, and 53D are provided in the A, B, C, and D stages, respectively. Each current differential relay 53 is connected to a voltage transformer VT and a current transformer CT of its own stage. In addition, these current differential relays 53A, 53B, 53C are interconnected through a communication path (not shown), and mutually exchange current data and voltage data of the detected magnetic cluster.

In the above configuration, the procedure in the case of synchronizing the sample timing of the A stage, the C stage, and the D stage with the timing of the sampling of the B stage will be described.

29 is a flowchart illustrating an example of a procedure of sampling synchronization processing in the power transmission system of FIG. 28. In the procedure of FIG. 29, the timing of the sampling of the other terminal is synchronized with the timing of the sampling of the B stage of FIG.

First, the current differential relay 53D in the D stage calculates the voltage Vg at the branch point g based on the A stage voltage V1 and the A stage current I1 (step S601). In addition, the current differential relay 53D calculates the voltage Vqg at the branch point g based on the D stage voltage Vq1 and the D stage current Iq1 (step S602). These specific calculation methods are the same as those explained in Embodiments 1 and 3.

Next, the current differential relay 53D calculates the phase difference φ1 between the voltage Vg at the branch point g and the voltage Vqg (step S603). The current differential relay 53D corrects the sampling time of the D stage by the delay time (or the preceding time) corresponding to the phase difference φ1 (that is, synchronizes the sampling time of the D stage with the sampling time of the A stage) ( Step S604).

Next, the current differential relay 53A selects the combined current Ig + Iqg of the current Ig flowing into the branch point g from the A stage and the current Iqg flowing into the branch point g from the D stage. It calculates (step S605).

Next, the current differential relay 53A calculates the voltage Vgf of the branch point f based on the voltage Vg of the branch point g and the combined current Ig + Iqg (step S606). In addition, the current differential relay 53A calculates the voltage Vsf at the branch point f based on the B stage voltage Vs1 and the B stage current Is1 (step S607).

Next, the current differential relay 53A calculates a phase difference φ 2 between the voltage Vgf of the branch point f and the voltage Vsf (step S608).

Next, the current differential relay 53A corrects the sampling time of the A stage by the delay time (or the preceding time) corresponding to the phase difference φ2 (that is, synchronizes the sampling time of the A stage with the sampling time of the B stage). Let). In addition, the current differential relay 53D of the D stage corrects the sampling time of the D stage by a delay time (or a preceding time) corresponding to the phase difference φ2 (that is, the sampling time of the D stage is changed to the sampling time of the B stage. (Step S609). Accordingly, the sampling time of the D stage is finally corrected by a time corresponding to the phase difference φ1 + φ2.

Next, the current differential relay 53C of the C stage calculates the voltage Vrf of the branch point f based on the C stage voltage Vr1 and the C stage current Ir1 (step S610). Further, the current differential relay 53C at the C stage calculates the voltage Vsf at the branch point f based on the B stage voltage Vs1 and the B stage current Is1 (step S611).

Next, the current differential relay 53C calculates a phase difference φ 3 between the voltage Vsf at the branch point f and the voltage Vrf (step S612). Then, the current differential relay 53C corrects the sampling time of the C stage by the delay time (or the preceding time) corresponding to the calculated phase difference φ3 (that is, the sampling time of the C stage is changed to the sampling time of the B stage. Synchronization) (step S613). The sampling synchronization process is completed by the above.

In this way, the terminal (B stage) provided with the current differential relay 53B of the master to be synchronized with the C stage current differential relay 53C connected through one branch point f is connected to each terminal (B stage, C). The voltage at the branch point f is calculated based on the current and voltage data of step A). The current differential relay 53C can correct the sample timing based on the calculated phase difference of the branch voltages.

On the other hand, the terminal (B stage) provided with the current differential relay 53B of the master to be synchronized with the A and D stage current differential relays 53A and 53D connected through two or more branch points f and g, First, it is necessary to calculate the synthesized current at the branch point f directly connected to the B stage and the other branch point g. For this reason, a step of synchronizing the other sampling timing with one of the sampling timings of these current differential relays 53A and 53D is required.

It should be thought that embodiment disclosed this time is an illustration and restrictive at no points. The scope of the present invention is shown by above-described not description but Claim, and it is intended that the meaning of a Claim and equality and all the changes within a range are included.

50, 201 to 203, 220 to 223: Transmission line 52A to 52D: Rear power supply
53, 53A to 53D: current differential relay 54, 54B, 54C: communication path
56, 91, 211: first condenser point 57: intermediate point
58, 93, 212: second condenser point 96, 213: third condenser point
94: fourth condenser point 67: specific point
76: relay calculator 74: voltage calculator
75: phase difference calculator 73: synchronization processor
80 to 86, 204 to 206: T-type circuit 100: input converter
110: A / D conversion unit 120: arithmetic processing unit
130: I / O section 131: transceiver
132: digital input circuit 133: digital output circuit
200, f, g: branch point C, CA, CB: site capacity
CT, CT1 to CT4: current transformer VT, VT1 to VT4: voltage transformer
Ts: specific time interval

Claims (16)

A current differential relay provided at a first terminal of a power transmission line,
An analog / digital converter configured to generate current data and voltage data by sampling current and voltage of the first terminal of the transmission line;
A receiver for receiving current data and voltage data of the second terminal from a second current differential relay provided at a second terminal of the power transmission line;
Based on the current data and the voltage data of the first terminal, a voltage at a specific point between the first terminal and the second terminal of the power transmission line is calculated as a first specific point voltage, and the current data of the second terminal. And a voltage calculating unit that calculates a voltage at the specific point as a second specific point voltage based on voltage data;
A phase difference calculator configured to calculate a phase difference between the first specific point voltage and the second specific point voltage;
And a synchronization processor for adjusting the sampling time of the current and the voltage of the first terminal based on the time corresponding to the phase difference,
When the voltage calculating section uses each of the first transmission line for connecting the first terminal and the specific point and the second transmission line for connecting the second terminal and the specific point, the entire power transmission line is a single? Type circuit. The first specific point voltage and the second specific point voltage are calculated by simulating as an L-type circuit, a single T-type circuit, or a plurality of T-type circuits connected in series. Current differential relay, characterized in that. The method of claim 1,
Each of the first line and the second line is simulated as an L-type circuit that is part of the π-type circuit when the entire transmission line is a single π-type circuit,
The voltage calculating section calculates the charging current of the first line based on the voltage of the first terminal, and calculates the charging current of the first line from the current of the first terminal by the current obtained by subtracting the first line. Calculates a voltage drop of, calculates the first specific point voltage by subtracting the voltage drop of the first line from the voltage of the first terminal,
The voltage calculating section calculates a charging current of the second line based on the voltage of the second terminal, and converts the charging current of the second line from the current of the second terminal to the second line. And calculating the voltage drop of the second voltage, and calculating the second specific point voltage by subtracting the voltage drop of the second line from the voltage of the second terminal. The method of claim 1,
The first line is simulated as a single first T-type circuit, the second line is simulated as a single second T-type circuit,
The voltage calculating section calculates a voltage drop from the first terminal to the capacitor point of the first T-type circuit by subtracting the voltage from the voltage of the first terminal to determine the voltage at the capacitor point of the first T-type circuit. A current obtained by calculating the charging current of the first line based on the voltage at the capacitor point of the first T-type circuit, and subtracting the charging current of the first line from the current of the first terminal. And the first specific point voltage is calculated based on the voltage at the capacitor point of the first T-type circuit,
The voltage calculating section converts the voltage drop from the second terminal to the capacitor point of the second T-type circuit by subtracting the voltage from the voltage of the second terminal to determine the voltage at the capacitor point of the second T-type circuit. A current obtained by calculating the charging current of the second line based on the voltage at the capacitor point of the second T-type circuit, and subtracting the charging current of the second line from the current of the second terminal. And the second specific point voltage is calculated based on the voltage at the capacitor point of the second T-type circuit. A current differential relay provided at a first terminal of a power transmission line,
An analog / digital converter configured to generate current data and voltage data by sampling current and voltage of the first terminal of the transmission line;
A receiver for receiving current data and voltage data of the second terminal from a second current differential relay provided at a second terminal of the power transmission line;
By simulating a line connecting the first terminal and the second terminal as a single T-type circuit or a plurality of T-type circuits connected in series, the voltage of the second terminal from the current data and the voltage data of the first terminal. A voltage calculator for calculating
A phase difference calculator which calculates a phase difference between the voltage of the second terminal calculated by the voltage calculator and the voltage of the actual second terminal;
And a synchronization processing unit for adjusting the sampling time of the current and the voltage of the first terminal based on the time corresponding to the phase difference. The method of claim 4, wherein
The line connecting the first terminal and the second terminal is simulated as a single T-type circuit,
The voltage calculating section calculates the voltage at the condenser point of the T-type circuit by subtracting the voltage drop from the first terminal to the condenser point of the T-type circuit from the voltage of the first terminal. The charging current of the line is calculated based on the voltage at the condenser point of the circuit, and based on the current obtained by subtracting the charging current of the line from the current of the first terminal and the voltage at the condenser point of the T-type circuit. Calculating a voltage at the second terminal. A current differential relay provided at a first terminal of a power transmission line,
An analog / digital converter configured to generate current data and voltage data by sampling current and voltage of the first terminal of the transmission line;
A receiver for receiving current data and voltage data of the second terminal from a second current differential relay provided at a second terminal of the power transmission line;
By simulating a line connecting the first terminal and the second terminal as a single T-type circuit or a plurality of T-type circuits connected in series, the voltage of the first terminal from the current data and voltage data of the second terminal. A voltage calculator for calculating
A phase difference calculator which calculates a phase difference between the voltage of the first terminal calculated by the voltage calculator and the voltage of the actual first terminal;
And a synchronization processing unit for adjusting the sampling time of the current and the voltage of the first terminal based on the time corresponding to the phase difference. The method according to any one of claims 1 to 6,
The current differential relay further comprises a transmitter for transmitting a first timing signal to the second current differential relay together with current data and voltage data of the first terminal,
The receiver receives a second timing signal from the second current differential relay along with current data and voltage data of the second terminal,
The synchronization processing unit,
A first time interval between the transmitter transmitting the first timing signal and the receiver receiving the second timing signal, and the second current differential relay outputs the second timing signal. A first step of controlling the sampling time of the current and the voltage of the first terminal such that the second time interval from transmitting to receiving the first timing signal is equal;
A second step of storing, as a third time interval, a time corresponding to the phase difference calculated by the phase difference calculating unit when the first time interval and the second time interval are equal;
Be configured to execute a third step of controlling the sampling time of the current and voltage of the first terminal such that the first time interval and the second time interval differ by two times the third time interval. A current differential relay. The method of claim 7, wherein
The synchronization processing unit uses the time corresponding to the phase difference calculated by the phase difference calculating unit when the first time interval and the second time interval differ by two times the third time interval, and the third time interval is determined. Is configured to further execute a fourth step of correcting a time interval of
In the third step, the third time interval corrected by the fourth step is used. The method of claim 8,
The synchronization processing unit is configured to continuously correct the third time interval by repeatedly executing the fourth step when the power transmission line is normal,
The synchronization processing unit is configured to execute the third step by using the third time interval corrected immediately before the occurrence of the failure of the transmission line, without executing the fourth step when the transmission line fails. A current differential relay. The method of claim 7, wherein
The synchronous processing unit executes the first step and the second step when the power transmission line is normal, and then the current of the first terminal and the current of the first terminal so that the time corresponding to the phase difference calculated by the phase difference calculating unit becomes zero. Configured to execute a fifth step of controlling the sampling time of the voltage,
And the synchronization processing unit is configured to execute the third step in place of the fifth step when the power transmission line fails. Sampling current and voltage at the first terminal of the transmission line to generate current data and voltage data;
Sampling current and voltage of the second terminal of the transmission line to generate current data and voltage data;
Calculating a voltage at a specific point between the first terminal and the second terminal of the power transmission line as a first specific point voltage from current data and voltage data of the first terminal;
Calculating a voltage at the specific point as a second specific point voltage from current data and voltage data of the second terminal,
In the step of calculating the first specific point voltage and the second specific point voltage, each of the first line connecting the first terminal and the specific point and the second line connecting the second terminal and the specific point, respectively. Is simulated as an L-type circuit which is part of the π-type circuit when the entire transmission line is a single π-type circuit, as a single T-type circuit, or as a plurality of T-type circuits connected in series,
Calculating a phase difference between the first specific point voltage and the second specific point voltage as a first phase difference;
And a step of adjusting the sampling time of the current and the voltage of the first terminal based on the time corresponding to the first phase difference. The method of claim 11,
The power transmission line further includes a third terminal connected through the specific point and a third line,
The sampling synchronization method is also,
Sampling current and voltage of the third terminal to generate current data and voltage data;
By simulating the third line as a single L-type circuit which is part of a π-type circuit, as a single T-type circuit or as a plurality of T-type circuits connected in series, the current data and voltage data of the third terminal are Calculating the voltage at the specific point as the third specific point voltage,
Calculating a phase difference between the second specific point voltage and the third specific point voltage as a second phase difference;
And adjusting the sampling time of the current and voltage of the third terminal based on the time corresponding to the second phase difference. The method of claim 11 or 12,
The sampling synchronization method,
Transmitting a first timing signal together with current data and voltage data of the first terminal from a first transceiver provided at the first terminal to a second transceiver provided at the second terminal;
And transmitting a second timing signal from the second transceiver to the first transceiver together with current data and voltage data of the second terminal,
The step of adjusting the sampling time of the current and the voltage of the first terminal,
A first time interval between the first transceiver transmitting the first timing signal and the second timing signal receiving the second timing signal, and the second transceiver transmitting the second timing signal A first step of controlling the sampling time of the current and the voltage of the first terminal so that the second time interval until the first timing signal is equalized;
A second step of storing, as a third time interval, a time corresponding to the first phase difference when the first time interval and the second time interval are equal;
And a third step of controlling the sampling time of the current and the voltage of the first terminal such that the first time interval and the second time interval differ by twice the third time interval. Sampling synchronization method. The method of claim 13,
The step of adjusting the sampling time of the current and the voltage of the first terminal,
Correcting the third time interval by using a time corresponding to the first phase difference calculated when the first time interval and the second time interval differ by two times the third time interval. Including a fourth step,
In the third step, the third time interval corrected by the fourth step is used. The method of claim 14,
In the step of adjusting the sampling time of the current and the voltage of the first terminal,
When the transmission line is normal, the third time interval is continuously corrected by repeatedly executing the fourth step,
And the fourth step is not executed at the time of failure of the transmission line, and the third step is executed using the third time interval corrected just before the occurrence of the failure of the transmission line. The method of claim 13,
In the step of adjusting the sampling time of the current and the voltage of the first terminal,
Controlling the sampling time of the current and voltage of the first terminal so that the time corresponding to the first phase difference becomes zero after the first step and the second step are executed at the time of the transmission line normal; 5 steps are executed,
And the third step is executed in place of the fifth step at the time of abnormality of the power transmission line.

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