KR102373804B1 - 반도체 패키지 및 그 제조 방법 - Google Patents
반도체 패키지 및 그 제조 방법 Download PDFInfo
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- KR102373804B1 KR102373804B1 KR1020190159073A KR20190159073A KR102373804B1 KR 102373804 B1 KR102373804 B1 KR 102373804B1 KR 1020190159073 A KR1020190159073 A KR 1020190159073A KR 20190159073 A KR20190159073 A KR 20190159073A KR 102373804 B1 KR102373804 B1 KR 102373804B1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H01L23/528—Geometry or layout of the interconnection structure
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/732—Location after the connecting process
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Heterocyclic Carbon Compounds Containing A Hetero Ring Having Oxygen Or Sulfur (AREA)
- Led Device Packages (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/213,769 | 2018-12-07 | ||
US16/213,769 US10497674B2 (en) | 2016-01-27 | 2018-12-07 | Semiconductor package and fabricating method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20200071014A KR20200071014A (ko) | 2020-06-18 |
KR102373804B1 true KR102373804B1 (ko) | 2022-03-14 |
Family
ID=71023329
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020190159073A KR102373804B1 (ko) | 2018-12-07 | 2019-12-03 | 반도체 패키지 및 그 제조 방법 |
Country Status (3)
Country | Link |
---|---|
KR (1) | KR102373804B1 (zh) |
CN (1) | CN111293112B (zh) |
TW (3) | TW202401593A (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11424191B2 (en) * | 2020-06-30 | 2022-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices and methods of manufacture |
WO2022252087A1 (en) * | 2021-05-31 | 2022-12-08 | Huawei Technologies Co., Ltd. | Method of manufacturing active reconstructed wafers |
EP4362086A1 (en) * | 2021-08-19 | 2024-05-01 | Huawei Technologies Co., Ltd. | Chip package structure and electronic apparatus |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011515842A (ja) | 2008-03-31 | 2011-05-19 | インテル・コーポレーション | 高密度インターコネクトのためのシリコンパッチ含有マイクロエレクトロニクスパッケージおよびその製造方法 |
JP2014140022A (ja) | 2012-12-20 | 2014-07-31 | Intel Corp | 高密度有機ブリッジデバイスおよび方法 |
US20150084210A1 (en) * | 2013-09-25 | 2015-03-26 | Chia-Pin Chiu | High density substrate interconnect using inkjet printing |
US20160141234A1 (en) * | 2014-11-17 | 2016-05-19 | Qualcomm Incorporated | Integrated device package comprising silicon bridge in photo imageable layer |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7868440B2 (en) * | 2006-08-25 | 2011-01-11 | Micron Technology, Inc. | Packaged microdevices and methods for manufacturing packaged microdevices |
JP2011151185A (ja) * | 2010-01-21 | 2011-08-04 | Shinko Electric Ind Co Ltd | 配線基板及び半導体装置 |
JP6230794B2 (ja) * | 2013-01-31 | 2017-11-15 | 新光電気工業株式会社 | 電子部品内蔵基板及びその製造方法 |
US9275955B2 (en) * | 2013-12-18 | 2016-03-01 | Intel Corporation | Integrated circuit package with embedded bridge |
US20150364422A1 (en) * | 2014-06-13 | 2015-12-17 | Apple Inc. | Fan out wafer level package using silicon bridge |
US9633939B2 (en) * | 2015-02-23 | 2017-04-25 | Amkor Technology, Inc. | Semiconductor package and manufacturing method thereof |
TWI652778B (zh) * | 2016-01-27 | 2019-03-01 | 艾馬克科技公司 | 半導體封裝以及其製造方法 |
US10833052B2 (en) * | 2016-10-06 | 2020-11-10 | Micron Technology, Inc. | Microelectronic package utilizing embedded bridge through-silicon-via interconnect component and related methods |
-
2019
- 2019-11-25 TW TW112131724A patent/TW202401593A/zh unknown
- 2019-11-25 TW TW111123848A patent/TWI815521B/zh active
- 2019-11-25 TW TW108142689A patent/TWI770440B/zh active
- 2019-11-27 CN CN201911177940.7A patent/CN111293112B/zh active Active
- 2019-12-03 KR KR1020190159073A patent/KR102373804B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011515842A (ja) | 2008-03-31 | 2011-05-19 | インテル・コーポレーション | 高密度インターコネクトのためのシリコンパッチ含有マイクロエレクトロニクスパッケージおよびその製造方法 |
JP2014140022A (ja) | 2012-12-20 | 2014-07-31 | Intel Corp | 高密度有機ブリッジデバイスおよび方法 |
US20150084210A1 (en) * | 2013-09-25 | 2015-03-26 | Chia-Pin Chiu | High density substrate interconnect using inkjet printing |
US20160141234A1 (en) * | 2014-11-17 | 2016-05-19 | Qualcomm Incorporated | Integrated device package comprising silicon bridge in photo imageable layer |
Also Published As
Publication number | Publication date |
---|---|
CN111293112A (zh) | 2020-06-16 |
TW202105534A (zh) | 2021-02-01 |
TW202240720A (zh) | 2022-10-16 |
KR20200071014A (ko) | 2020-06-18 |
TWI770440B (zh) | 2022-07-11 |
TWI815521B (zh) | 2023-09-11 |
CN111293112B (zh) | 2024-05-03 |
TW202401593A (zh) | 2024-01-01 |
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