KR102357600B1 - Controll device and liquid crystal display device using the same - Google Patents

Abstract

The present invention relates to a control device and a liquid crystal display device using the same, and in particular, a liquid crystal display device driven at a low frequency of 30 Hz or less, a frame period is divided into a charging period and a blanking period, and the length of the blanking period is variable for each frame And it is a technical task to provide a control device applied thereto. In order to achieve the above technical object, in the liquid crystal display according to the present invention, one frame period is divided into a charging period in which data voltages are charged to the pixels and a blanking period in which the data voltages charged in the pixels are held, , when the liquid crystal panel is driven at (P) Hz, the length between the chargers corresponds to the length of one frame period of the liquid crystal display driven at (2P) Hz (P is a natural number), and each one of the frames The average of the lengths of the frame periods of , corresponds to the lengths of the two frame periods of the liquid crystal display driven at (2P) Hz.

Description

Control device and liquid crystal display using the same

The present invention relates to a control device and a liquid crystal display using the same.

The flat panel display includes a liquid crystal display device (LCD), a plasma display panel (PDP), and an organic light emitting display device (OLED).

Among flat panel display devices, a liquid crystal display is a device that displays an image by using the optical anisotropy of liquid crystal, and is widely used because it has advantages such as thinness, small size, low power consumption, and high quality.

1 is a graph illustrating a driving method and luminance of a conventional liquid crystal display driven at 30 Hz. In particular, (a) shows a timing diagram of a gate start pulse applied to a conventional liquid crystal display driven at 60 Hz, and (b) is a timing diagram of a gate start pulse applied to a conventional liquid crystal display driven at 30 Hz. (c) shows the amount of change in luminance when the conventional liquid crystal display driven at 30 Hz is normally driven, and (d) is the amount of change in luminance when the conventional liquid crystal display driven at 30 Hz is abnormally driven. indicates

As the driving frequency of the liquid crystal display device is changed from 60 Hz as shown in (a) to 30 Hz as shown in (b), in the conventional liquid crystal display device driven at 30 Hz, as shown in (b) Likewise, one frame period is divided into a charging period and a blanking period.

In the charging period, as shown in (c) and (d), the luminance increases, and in the discharging period, that is, in the blanking period, the luminance decreases.

When the conventional liquid crystal display driven at 30 Hz is normally driven, as shown in (c), the range of change in luminance is not large. Accordingly, flicker does not occur.

However, when the conventional liquid crystal display driven at 30 Hz is not driven normally, as shown in (d), a large change in luminance occurs, and thus, flicker having a frequency of 30 Hz may be generated.

In particular, when a data voltage having a '+' polarity and a data voltage having a '-' polarity are asymmetric, flicker having a frequency of 15 Hz may be generated.

More specifically, in the conventional liquid crystal display driven at 30 Hz, as shown in (b), the charging period is halved as compared to the liquid crystal display driven at 60 Hz. Accordingly, even if an oxide TFT having excellent holding characteristics is applied, flicker as shown in (d) may occur.

The present invention proposed to solve the above problems is a liquid crystal display device that is driven at a low frequency of 30 Hz or less, a frame period is divided into a charging period and a blanking period, and the length of the blanking period is variable for each frame, and applied thereto It is a technical task to provide a control device.

In the liquid crystal display device according to the present invention for achieving the above technical problem, one frame period is divided into a charging period in which data voltages are charged to the pixels and a blanking period in which the data voltages charged in the pixels are held, , when the liquid crystal panel is driven at (P) Hz, the length between the chargers corresponds to the length of one frame period of the liquid crystal display driven at (2P) Hz (P is a natural number), and each one of the frames The average of the lengths of the frame periods of , corresponds to the lengths of the two frame periods of the liquid crystal display driven at (2P) Hz.

According to an aspect of the present invention, there is provided a control device comprising: an input circuit for receiving input image data and a timing signal; a storage circuit for storing information about a charging period in which data voltages are charged in the pixels and a blanking period in which data voltages charged in the pixels are held and the input image data; a control signal generating circuit for generating a gate control signal for controlling the gate driver and a data control signal for controlling the data driver by using the timing signal; and an alignment circuit that rearranges the input image data for each frame to generate image data, and outputs the image data to a data driver so that the data voltage is output between the chargers, wherein the control signal generating circuit comprises: The gate control signal and the data control signal are generated using the timing signal so that the length of the interval is kept constant in all frames and the length of the blanking period is varied for at least one frame.

According to the present invention, the length of the blanking period varies for each frame, so that the flicker of the harmonic component is dispersed, and thus, the defect rate due to the flicker can be reduced.

More specifically, in the present invention, the frame period of the liquid crystal display driven at 30 Hz is divided into a charging period and a blanking period, data is held during the blanking period, and the length of the blanking period is varied for each frame. Accordingly, the difference in luminance generated by driving at 30 Hz is irregularly changed, and thus flicker may be reduced.

1 is a graph illustrating a driving method and luminance of a conventional liquid crystal display driven at 30 Hz;
2 is a block diagram of an embodiment of a liquid crystal display device according to the present invention.
3 is a configuration diagram of an embodiment of a control device applied to a liquid crystal display according to the present invention.
4 is an exemplary view showing the lengths of frame periods applied to the liquid crystal display according to the present invention.
5 is an exemplary view illustrating a relationship between a charging period and a blanking period applied to a liquid crystal display according to the present invention.
6 is another exemplary view for explaining the relationship between the charging period and the blanking period applied to the liquid crystal display according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a configuration diagram of a liquid crystal display device according to an embodiment of the present invention. 3 is a configuration diagram of a control device applied to a liquid crystal display according to an embodiment of the present invention. 4 is an exemplary view showing the lengths of frame periods applied to the liquid crystal display according to the present invention.

As shown in FIG. 2, the liquid crystal display according to the present invention includes a liquid crystal panel 100 in which pixels defined by data lines DL1 to DLd and gate lines GL1 to GLg are disposed; The gate driver 200 sequentially supplies a gate pulse to the gate lines GL1 to GLg, and a data voltage generated by image data while the gate pulse is supplied to any one of the gate lines A data driver 300 for supplying the data to the data lines and a gate start pulse for sequentially outputting the gate pulses to the gate lines are generated for each frame and transmitted to the gate driver, and the input image and a control device 400 that converts data into the image data RGB and transmits the data to the data driver 300 .

The frame period is divided into a charging period in which the data voltages are charged in the pixels and a blanking period in which the data voltages charged in the pixels are held.

The frame period means a period in which one image is output through the liquid crystal panel.

The frame corresponds to the single image. In this case, the frame may mean a group of input image data corresponding to the one image, a group of image data, or a group of data voltages.

When the liquid crystal panel is driven at (P) Hz, the length between the chargers corresponds to the length of one frame period of the liquid crystal display driven at (2P) Hz (P is a natural number), and each of the frames The average of the lengths of one frame period corresponds to the length of two frame periods of a liquid crystal display driven at (2P) Hz.

First, the panel 100 is formed by bonding a first substrate (thin film transistor substrate) and a second substrate (color filter substrate) together. A liquid crystal layer is formed between the first substrate and the second substrate. The first substrate and the second substrate may be manufactured using a base substrate such as glass, plastic, or metal.

Next, the data driver 300 converts the image data input from the control device 400 into analog data voltages, and data corresponding to one horizontal line is provided for each horizontal period in which the gate pulse is supplied to the gate line. voltages are supplied to the data lines.

The configuration and function of the data driver 300 are the same as those of the data driver applied to a general liquid crystal display device.

However, the output period of the data control signals transmitted from the control device 400 to the data driver 200 may be changed for at least one frame.

For example, as the blanking period is varied, the timing at which data voltages are output to the data lines may be changed. Accordingly, the timing at which a data control signal for outputting data voltages to the data lines, for example, a source output enable signal, is supplied to the data driver 300 may be changed.

In more detail, the configuration of the data driver 300 applied to the present invention is not changed compared to the conventional one. However, the timing at which the data control signals transmitted from the control device 400 to the data driver 300 are input to the data driver 300 may be changed. The timing input to the data driver 300 is controlled by the control device 400 .

Next, the gate driver 200 sequentially supplies gate pulses to the gate lines GL1 to GLg of the panel 100 in response to a gate control signal GCS input from the control device 400 . . Accordingly, switching transistors formed in each pixel of the corresponding horizontal line to which the gate pulse is input may be turned on, and the data voltage may be charged to each pixel.

For example, the gate driver 200 shifts a gate start pulse (GSP) transmitted from the control device 400 according to a gate shift clock (GSC), and enables a gate output. According to a gate output enable (GOE) signal, the gate pulses are sequentially supplied to the gate lines GL1 to GLg during the charging period.

The gate driver 200 supplies a gate-off signal to the gate lines GL1 to GL2g during the remaining period in which the gate pulse is not supplied. The switching transistor is turned off by the gate-off signal. During the blanking period after the switching transistor is turned off, the data voltage charged in the pixel is maintained as it is. The gate pulse and the gate-off signal are collectively referred to as a gate signal.

The gate driver 200 may be formed independently of the panel 100 and may be configured to be electrically connected to the panel 100 in various ways, but a gate mounted in the panel 100 . It may be configured in a Gate In Panel (GIP) method. A gate start signal corresponding to the gate start pulse GSP may be transmitted from the control device 400 to the gate driver 200 configured in the GIP method.

The configuration and function of the gate driver 200 are the same as those of a gate driver applied to a general liquid crystal display device.

However, the period of the gate start pulse transmitted from the control device 400 to the gate driver 200 and the period of the reset signal for resetting the gate driver 200 may be changed for at least one frame. .

In detail, the configuration and function of the gate driver 200 applied to the present invention is the same as that of the gate driver applied to a general liquid crystal display device. However, the period of the gate control signals transmitted from the control device 400 to the gate driver 200 , for example, the gate start pulse and the reset signal may be changed for at least one frame.

In other words, the configuration of the gate driver 200 applied to the present invention is not changed compared to the conventional one. However, the timing at which the gate control signals transmitted from the control device 400 to the gate driver 200 are input to the gate driver 200 may be changed. The timing input to the gate driver 200 is controlled by the control device 400 .

Finally, the control device 400 according to the present invention uses a vertical synchronization signal, a horizontal synchronization signal, and a clock CLK supplied from an external system (not shown) (hereinafter simply referred to as a 'timing signal') using A gate control signal GCS for controlling the gate driver 200 and a data control signal DCS for controlling the data driver 300 are output.

The gate control signals GCS generated by the control device 400 include the gate start pulse GSP, a gate shift clock, a gate output enable signal, and the reset signal.

The data control signals DCS generated by the control device 400 include a source start pulse, a source shift clock signal, a source output enable signal, a polarity control signal, and the like.

The control device 400 samples the input image data (Input RGB) input from the external system, rearranges them, and supplies the rearranged image data RGB to the data driver 300 .

In particular, the control device 400 maintains the length between the chargers constant in all frames, and varies the length of the blanking period for at least one frame by using the timing signal.

For example, when the length of the blanking period in the first frame period corresponding to the first frame corresponds to the period in which the 2408 clocks CLK are output, the control device 400 corresponds to the second frame. The length of the blanking period in the second frame period may be set to a period in which 2534 clocks CLK are output.

Also, the control device 400 may set the length of the blanking period in the third frame period corresponding to the third frame to the period in which the 266 clocks CLK are output.

The control device 400 transmits the gate start pulse to the gate driver when the charging period starts during one frame period, and the gate driver 200 transmits the gate pulse only during the charging period. supplied to the gate lines.

Accordingly, in the charging period, the data voltages are charged to the pixels, and in the blanking period after the charging period, the data voltages of the pixels are maintained.

The control device 400 may sequentially increase and then sequentially decrease the length of the blanking period for each frame.

As described above, the control device 400 may change the length of the blanking period for at least one frame.

In particular, the control device 400 may sequentially increase the length of the blanking period and then sequentially decrease it again.

In this case, the control device 400 may sequentially increase and then sequentially decrease the length of the blanking period in cycles of nP frames. Here, n is a natural number greater than or equal to 1.

For example, when P is 30, that is, when the liquid crystal display is driven at 30 Hz, and the length between the chargers corresponds to a period in which 2048 clocks CLK are output, the first frame The length of the blanking period in the first frame period corresponding to may correspond to the period in which the 2408 clocks CLK are output. In this case, the length of the first frame period may correspond to a period in which 4456 clocks CLK are output as shown in FIG. 4A .

In this case, the control device 400 may increase the length of the blanking period in the second frame period by the period in which the nine clocks are output. Accordingly, the length of the second frame period is As shown in (a), 4465 clocks CLK may correspond to the output period. The length between chargers in the second frame period is the same as the length between chargers in the first frame period.

Thereafter, the control device 400 may increase the length of the blanking period in the third frame period to the thirtieth frame period by a preset length. In this case, the length between the chargers in all frame periods is maintained at a length corresponding to the length at which the 2048 clocks CLK are output, as described above.

Accordingly, the length of the first frame period to the third frame period is 4,708 clocks CLKI output from the length of the period in which 4456 clocks CLK are output, as shown in FIG. 4A It can be increased by the length of the period to be

When the period from the first frame period to the 30th frame period is referred to as a first period, the period from the first frame period to the 30th frame period continuous after the 30th frame is referred to as a second period.

In the second period, the control device 400 determines the length of the first frame period to the thirtieth frame period, as shown in FIG. 4B , during which 4708 clocks CLK are output. It is possible to reduce the length of the period in which 4456 clocks CLKI are output from the length of .

Accordingly, the control device 400 may sequentially increase and then sequentially decrease the length of the blanking period with a cycle of 60 frames. In this case, n becomes 2.

If, in each of the first period and the second period, the blanking period sequentially decreases (or increases) and then sequentially increases (or decreases) again during the first frame period to the thirtieth frame period, The length of the blanking period is changed with a cycle of 30 frames. In this case, n becomes 1.

In order to perform the function as described above, the control device 400, as shown in FIG. 3, includes an input circuit 410 for receiving the input image data (Input RGB) and a timing signal, the charging period and A storage circuit 440 for storing information about the blanking period and the input image data, and the reset signal and the gate start pulse are generated using the timing signal, and for each frame, when the charging period starts, the gate The control signal generating circuit 420 and the storage circuit 440 for outputting a start pulse to the gate driver 200 and outputting the reset signal to the gate driver 200 when the charging period ends and an alignment circuit 430 for generating image data by rearranging the input image data for each frame, and outputting the image data to the data driver 300 so that the data voltage is output between the chargers.

In this case, the image data RGB and the data control signal DCS may be transmitted to the data driver 300 through the output unit 450 , and the gate control signal GCS may be transmitted to the output unit ( may be transmitted to the gate driver 300 through 450 .

First, the input circuit 410 transmits the input image data received from the external system (not shown) to the storage circuit 440 , and transmits the timing signal to the control signal generation circuit 420 . . However, the input circuit 410 may transmit the input image data to the alignment circuit 430 .

Second, the storage circuit 440 stores the input image data received from the input circuit 410 or the image data received from the alignment circuit 430 .

The storage circuit 440 stores information on the length of the blanking period.

Third, the control signal generating circuit 430 generates the gate control signal and the data control signal by using the timing signal and information on the length of the blanking period.

Fourth, the alignment circuit 430 converts the input image data (Input RGB) into the image data (RGB).

The alignment circuit 430 may output the image data RGB to the data driver in accordance with the chargers.

Also, the alignment circuit 430 may transmit the image data RGB to the storage circuit 440 . In this case, the storage circuit 440 transmits the image data RGB to the data driver 300 according to a control signal transmitted from the alignment circuit 430 or the input circuit 410 . In this case, the alignment circuit 430 or the input circuit 410 controls the output timing of the storage circuit 440 so that the image data RGB can be transmitted to the data driver in accordance with the chargers. can

In more detail, the alignment circuit 430 or the input circuit 410 uses the information on the length of the blanking period stored in the storage circuit 440 and the length between the chargers, When the charging period starts, the image data is transmitted to the data driver 300 .

In addition, the control signal generating circuit 430 transmits the gate pulse to the gate driver 200 when the charging period starts, and transmits the reset signal to the gate driver 200 when the charging period ends. send.

Also, the control signal generating circuit 430 transmits the source output enable signal to the data driver 200 when the charging period starts.

5 is an exemplary view for explaining the relationship between the charging period and the blanking period applied to the liquid crystal display according to the present invention. (a) shows the waveforms of the gate start pulse and data voltage when the length of the blanking period is shorter than the length of the reference blanking period, (b) shows the gate start pulse and data voltage when the length of the blanking period is the same as the length of the reference blanking period The waveform of the voltage is shown, and (c) shows the waveform of the gate start pulse and the data voltage when the length of the blanking period is longer than the length of the reference blanking period.

(a), (b) and (c) show the characteristics that the blanking periods of each of the frame periods applied to the present invention are different from each other.

As described above, the control device 400 maintains the length of the charging period constant in all frame periods, and adjusts the length of the blanking period by at least one using the timing signal. Variable for each frame.

For example, the length of the charging period in each of the frame periods shown in (a), (b) and (c) corresponds to a period in which 2048 clocks are output. That is, the charging lengths in each of the frame periods shown in (a), (b) and (c) are the same.

However, the length of the blanking period in the frame period shown in (a) corresponds to the period in which 2408 clocks are output, and the length of the blanking period in the frame period shown in (b) is the period in which 2534 clocks are output. and the length of the blanking period in the frame period shown in (c) corresponds to a period in which 2660 clocks are output.

Accordingly, the length of the frame period shown in (a) corresponds to the period in which 4456 clocks are output, the length of the frame period shown in (b) corresponds to the period in which 4582 clocks are output, and in (c) The illustrated frame period corresponds to a period in which 4708 clocks are output.

When the length of the frame period shown in (b) is the length of the frame period applied to a liquid crystal display driven at 30 Hz, the length of the blanking period shown in (b) becomes the length of the reference blanking period.

The length of the blanking period shown in (a) is 5% smaller than the length of the reference blanking period shown in (b). Therefore, the interval of the gate start pulses shown in (a) is smaller than the interval of the gate start pulses shown in (b).

The length of the blanking period shown in (c) has a value 5% greater than the length of the reference blanking period shown in (b). Therefore, the interval of the gate start pulses shown in (c) is larger than the interval of the gate start pulses shown in (b).

In the liquid crystal display according to the present invention, gate start pulses having the intervals shown in (a) to (c) may be sequentially transmitted to the gate driver 200, and in this case, (a) to (c) Data voltages having timing as shown in FIG. 1 may be supplied to the data lines.

In more detail, in the liquid crystal display device according to the present invention, the gate start pulse for generating the length of the frame period shown in (a) to (c) may be supplied to the gate driver.

In other words, in the liquid crystal display device according to the present invention, the length of the frame period shown in (a) to (c) may be repeated every 3 frames.

In addition, in the liquid crystal display device according to the present invention, the gate start pulse for generating a more subdivided frame period length than the frame period lengths shown in (a) to (c) may be supplied to the gate driver. .

For example, in the liquid crystal display device according to the present invention, the gate start pulses for generating the frame period lengths shown in FIG. 4 may be supplied to the gate driver.

In this case, in the liquid crystal display according to the present invention, the length of the frame period shown in FIGS. 4A and 4B may be repeated every 60 frames.

In addition, the length of the blanking period is sequentially increased (or decreased) and then sequentially decreased (or increased) again, and returns to the original length. Accordingly, the average of the lengths of the blanking period becomes the length of the reference blanking period.

In detail, when the length of the blanking period driven at 30Hz is the length of the reference blanking period, as shown in FIG. 5(b), the length of the blanking period is When sequentially increasing or decreasing, the average of the blanking periods becomes equal to the length of the reference blanking period.

6 is another exemplary view for explaining the relationship between the charging period and the blanking period applied to the liquid crystal display according to the present invention. Fig. 5 shows the characteristic that the length of the blanking period in each frame period is different from each other, and Fig. 6 shows the characteristic that the length of the blanking period in successive frame periods is sequentially changed. Also, in FIG. 6 , a triangle drawn with a solid line indicates the timing at which the gate pulse is output to the liquid crystal panel. For example, during a period corresponding to the length between the chargers, the gate pulses are sequentially output from a gate line disposed at an upper end of the liquid crystal panel to a gate line disposed at a lower end of the liquid crystal panel. In the blanking period after the charging period, the gate pulse is not output to the gate line. Accordingly, the triangle is not shown in the period corresponding to the length of the blanking period.

In addition, a triangle indicated by a dotted line in FIG. 6 indicates the timing at which the gate pulse is output when the length of the blanking period is the same.

Also, in FIG. 6, X represents the length between the reference chargers, Y represents the length of the reference blanking period, and α represents the error between the lengths of the blanking periods. In FIG. 5 , α corresponds to a period in which 26 clocks are output, and in FIG. 4 , α corresponds to a period in which approximately 9 clocks are output.

5 shows an example in which the blanking period is changed to a period of 3 frame periods, and FIG. 4 shows an example in which the blanking period is changed to a period of 60 frame periods. 6 shows an example in which the blanking period is changed to a period of six frame periods.

First, referring to FIG. 6A , the interval between the gate start pulses GSP has a magnitude corresponding to X+Y-α in one frame period and corresponds to X+Y+α in two frame periods. It has a size corresponding to X+Y in three frame periods, a size corresponding to X+Y+α in four frame periods, and a size corresponding to X+Y-α in five frame periods. , has a size corresponding to X+Y in 6 frame periods.

In more detail, the intervals between the gate start pulses GSP are sequentially increased (or decreased) and then sequentially decreased (or increased). Accordingly, the time point at which the image is output continuously changes, and accordingly, flicker does not occur.

Next, referring to FIG. 6B, assuming that the length of the reference frame period has a size corresponding to X+Y, since the length of one frame period is reduced to X+Y-α, the blanking period The length is reduced to Y-α. The length between chargers in two frame periods is the same as the length between chargers in one frame period, and the length of two frame periods corresponds to X+Y+α. That is, the length of two frame periods is longer than the length of one frame period. Accordingly, the length of the blanking period in the two frame period is increased to Y+α. The length between chargers in the three frame period is equal to the length (X) between the reference chargers, and the length of the blanking period in the three frame period is equal to the length (Y) of the reference blanking period.

From the 4 frame period to the 6 frame period, the length of the blanking period changes from X+Y+α to X+Y through X+Y-α.

In this case, it can be seen that the length of the average blanking period for 6 frame periods is X+Y.

According to the present invention as described above, since the time point at which an image is output continuously changes, flicker does not occur, and since the average of the lengths of the blanking period and the length of the frame period has a constant value, the liquid crystal display It can be operated stably.

The features of the present invention are briefly summarized as follows.

The present invention reduces the difference in luminance generated in a liquid crystal panel driven at a low frequency of 30 Hz or less by varying the length of the blanking period, which is a period in which the data voltage is maintained in the pixel, during the charging period and the blanking period constituting the frame period. can

The magnitude of the flicker reduction varies according to the degree of change in the length of the blanking period.

When the length of the blanking period is increased or decreased at the level of 5% of the length of the reference blanking period, it was confirmed through the simulation results that the flicker can be improved to a level of approximately 7.8 dB.

In order to realize a liquid crystal display device using low power consumption, the present invention drives a liquid crystal panel using a low frequency such as 30 Hz. In this case, as shown in FIG. 5 , the charging period and the blanking period are approximately They alternate half and half.

In this case, the present invention can variously change the length of the blanking period, and thus flicker can be reduced.

In other words, when an oxide thin film transistor is used instead of a thin film transistor using amorphous silicon, the leakage current in the blanking period can be reduced. However, when the liquid crystal display using the oxide thin film transistor is driven at a low frequency for low power consumption, flicker may still occur.

To prevent this, in the present invention, as described above, one frame period is divided into a charging period and a blanking period, and the length of the blanking period is variously changed.

Those skilled in the art to which the present invention pertains will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential characteristics thereof. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the following claims rather than the above detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. do.

100: panel 200: gate driver
300: data driver 400: control device

Claims (10)

a liquid crystal panel on which pixels are disposed;
a gate driver sequentially supplying gate pulses to gate lines disposed on the liquid crystal panel;
a data driver supplying data voltages generated by image data to data lines disposed in the liquid crystal panel while the gate pulse is supplied to one of the gate lines; and
A gate start pulse that causes the gate pulse to be sequentially output to the gate lines is generated for each frame, transmitted to the gate driver, and input image data is converted into the image data and transmitted to the data driver including a control device;
One frame period is divided into a charging period in which the data voltages are charged in the pixels and a blanking period in which the data voltages charged in the pixels are held,
The length between the chargers is kept constant in all frames,
With an nP frame cycle, the length of the blanking period in successive frame periods is sequentially increased and then decreased sequentially,
When the liquid crystal panel is driven at (P) Hz, the length between the chargers corresponds to the length of one frame period of the liquid crystal display driven at (2P) Hz (n and P are natural numbers),
The average of the lengths of one frame period of each of the frames corresponds to the length of two frame periods of the liquid crystal display driven at (2P) Hz. The method of claim 1,
wherein P is 30,
The control device drives the liquid crystal panel at 30 Hz. The method of claim 1,
The control device is
A liquid crystal display for varying the length of the blanking period for at least one frame by using a timing signal. The method of claim 1,
The control device transmits the gate start pulse to the gate driver when the charging period starts during one frame period,
The gate driver supplies the gate pulse to the gate lines only during the charging period. The method of claim 1,
When X denotes the length between the reference chargers, Y denotes the length of the reference blanking period, and α denotes the error between the lengths of the blanking periods,
In one continuous frame period to six frame periods,
The interval between the gate start pulse output in one frame period and the gate start pulse output in two frame periods has a magnitude corresponding to X+Y-α, and the gate start pulse output in the second frame period and the gate start pulse output in the third frame period are Each interval of the gate start pulses has a magnitude corresponding to X+Y+α, and the interval between the gate start pulse output in the 3rd frame period and the gate start pulse output in the 4th frame period has a magnitude corresponding to X+Y,
The interval between the gate start pulse output in the 4 frame period and the gate start pulse output in the 5 frame period has a magnitude corresponding to X+Y+α, and the gate start pulse output in the 5 frame period and the gate start pulse output in the 6 frame period are An interval between the gate start pulses is a liquid crystal display having a magnitude corresponding to X+Y-α. The method of claim 1,
When X represents the length between the reference chargers, Y represents the length of the reference blanking period, α represents the error between the lengths of the blanking periods, and the length of the reference frame period has a size corresponding to X+Y,
In one continuous frame period to five frame periods,
The length of one frame period corresponds to X+Y-α, the length of two frame periods has a size corresponding to X+Y+α, the length of three frame periods has a size corresponding to X+Y,
The length of the 4 frame period has a size corresponding to X+Y+α, and the length of the 5 frame period has a size corresponding to X+Y-α. an input circuit for receiving input image data and a timing signal;
a storage circuit for storing information about a charging period in which data voltages are charged in the pixels and a blanking period in which data voltages charged in the pixels are held and the input image data;
a control signal generating circuit for generating a gate control signal for controlling the gate driver and a data control signal for controlling the data driver by using the timing signal; and
and an alignment circuit for generating image data by rearranging the input image data for each frame, and outputting the image data to a data driver so that the data voltage is output between the chargers;
The control signal generating circuit generates the gate control signal and the data control signal, the timing signal so that the length between the chargers is kept constant in all frames and the length of the blanking period is varied for at least one frame. created using
With an nP frame cycle, the length of the blanking period in successive frame periods is sequentially increased and then decreased sequentially,
When the liquid crystal panel provided with the pixels is driven at (P) Hz, the length between the chargers corresponds to the length of one frame period of the liquid crystal display driven at (2P) Hz (n and P are natural numbers) ,
The average of the lengths of one frame period of each of the frames corresponds to the length of two frame periods of the liquid crystal display driven at (2P) Hz. 8. The method of claim 7,
The control signal generating circuit,
A reset signal and a gate start pulse are generated by using the timing signal, the gate start pulse is output to the gate driver when the charging period starts every frame, and the reset signal is applied to the gate when the charging period ends output to the driver,
A control device for varying an interval of the gate start pulse every at least one frame. 8. The method of claim 7,
The alignment circuit is
The control device converts the input image data transmitted from the storage circuit into the image data, and outputs the image data to the data driver when the charging period starts. 8. The method of claim 7,
The alignment circuit is
converting the input image data transmitted from the input circuit into the image data, and transmitting the image data to the storage circuit;
The storage circuit is
A control device for transmitting the image data to the data driver when the charging period starts according to a control signal transmitted from the alignment circuit or the input circuit.

Images