KR20160141204A - Controll device and liquid crystal display device using the same - Google Patents

Abstract

The present invention relates to a control device and a liquid crystal display device using the same. In particular, the present invention relates to a liquid crystal display device which operates at a low frequency equal to or lower than 30 Hz, each frame period of which is divided into a charging period and a blanking period, and a blanking period of which varies for each frame and also relates to a control device applied to the liquid crystal display device. For this purpose, in the liquid crystal display device according to the present invention, each frame period is divided into a charging period during which pixels are charged with data voltages and a blanking period during which the data voltages stored in the pixels are held, a length of the charging period corresponds to a length of the corresponding frame period of the liquid crystal display device operating at 2P Hz (P is a natural number) when a liquid crystal panel operates at P Hz, and an average of the frame periods of respective frames corresponds to a length of two frame periods of the liquid crystal display device operating at 2P Hz.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display (LCD)

The present invention relates to a control apparatus and a liquid crystal display apparatus using the same.

The flat panel display device includes a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED).

Of the flat panel display devices, a liquid crystal display device is an apparatus for displaying an image using the optical anisotropy of a liquid crystal and is widely used because of its advantages such as thinness, small size, low power consumption and high image quality.

1 is a graph illustrating a driving method and luminance of a conventional liquid crystal display device driven at 30 Hz. Particularly, (a) shows a timing chart of a gate start pulse applied to a conventional liquid crystal display device driven at 60 Hz, (b) shows a timing chart of a gate start pulse applied to a conventional liquid crystal display device driven at 30 Hz (C) shows the amount of change in luminance when the conventional liquid crystal display device driven at 30 Hz is normally driven, and (d) shows the change amount of the luminance when the conventional liquid crystal display device driven at 30 Hz is abnormally driven .

In the conventional liquid crystal display device driven at 30 Hz as the driving frequency of the liquid crystal display device is changed from 60 Hz as shown in (a) to 30 Hz as shown in (b), as shown in (b) Similarly, one frame period is divided into a charging period and a blanking period.

In the charging period, the luminance increases as shown in (c) and (d), and the luminance decreases in the discharge period, that is, the blanking period.

When the conventional liquid crystal display device driven at 30 Hz is normally driven, the variation width of the luminance is not large as shown in (c). Therefore, flicker is not generated.

However, if the conventional liquid crystal display device driven at 30 Hz is not normally driven, as shown in (d), a large variation width of the brightness is generated, and thus flicker having a frequency of 30 Hz can be generated.

Particularly, if the data voltage having the '+' polarity and the data voltage having the '-' polarity are asymmetric, a flicker having a frequency of 15 Hz may be generated.

In other words, in the conventional liquid crystal display device driven at 30 Hz, as compared with the liquid crystal display device driven at 60 Hz, the charging period is reduced to half as shown in (b). Therefore, even when an oxide thin film transistor (oxide TFT) having excellent holding characteristics is applied, a flicker as shown in (d) can be generated.

According to an aspect of the present invention, there is provided a liquid crystal display device driven at a low frequency of 30 Hz or less, wherein the frame period is divided into a charge period and a blanking period, And a control device.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display (LCD) device including a first frame period and a second frame period, wherein the first frame period is divided into a charge period in which data voltages are charged in the pixels and a blanking period in which data voltages charged in the pixels are held , When the liquid crystal panel is driven at (P) Hz, the length between the chargers corresponds to the length of one frame period of the liquid crystal display device driven at (2P) Hz (P is a natural number) Corresponds to the length of two frame periods of the liquid crystal display driven by (2P) Hz.

According to an aspect of the present invention, there is provided a control apparatus including: an input circuit for receiving input image data and a timing signal; A storage circuit for storing information on a charging period in which data voltages are charged in the pixels, information on a blanking period in which data voltages charged in the pixels are held, and the input image data; A control signal generation circuit for generating a gate control signal for controlling the gate driver and a data control signal for controlling the data driver using the timing signal; And an alignment circuit for generating image data by rearranging the input image data frame by frame and outputting the image data to a data driver so that the data voltage is outputted during the charging period, Wherein the gate control signal and the data control signal are generated using the timing signal so that the length of the blanking period is constant in all the frames and the length of the blanking period is variable in every at least one frame.

According to the present invention, the length of the blanking period varies for each frame, and the flicker of the harmonic component is dispersed, so that the defect rate due to the flicker can be reduced.

To be more specific, in the present invention, the frame period of the liquid crystal display device driven at 30 Hz is divided into a charging period and a blanking period, data is held in the blanking period, and the length of the blanking period is varied frame by frame. Therefore, the luminance difference generated by driving at 30 Hz is irregularly changed, and thus the flicker can be reduced.

1 is a graph illustrating a driving method and luminance of a conventional liquid crystal display device driven at 30 Hz.
2 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.
3 is a block diagram of a control device applied to a liquid crystal display device according to an embodiment of the present invention.
4 is a view illustrating lengths of frame periods applied to a liquid crystal display device according to the present invention;
FIG. 5 is a view for explaining a relationship between a charging period and a blanking period applied to a liquid crystal display device according to the present invention. FIG.
FIG. 6 is another exemplary diagram illustrating the relationship between the charging period and the blanking period applied to the liquid crystal display device according to the present invention. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a liquid crystal display device according to an embodiment of the present invention. 3 is a block diagram of a control device applied to a liquid crystal display device according to an embodiment of the present invention. 4 is an exemplary view showing lengths of frame periods applied to the liquid crystal display device according to the present invention.

2, the liquid crystal display according to the present invention includes a liquid crystal panel 100 in which pixels defined by data lines DL1 to DLd and gate lines GL1 to GLg are arranged, A gate driver 200 for sequentially supplying gate pulses to the gate lines GL1 to GLg, a gate driver 200 for applying a gate voltage to the gate lines GL1 to GLg, A data driver 300 for supplying the gate driver with the gate pulses to the data lines, and a gate start pulse for sequentially outputting the gate pulses to the gate lines, And a control unit 400 for converting the data into the image data RGB and transmitting the data to the data driver 300.

The frame period is divided into a charge period in which the data voltages are charged to the pixels and a blanking period in which the data voltages charged in the pixels are held.

The frame period is a period during which one image is output through the liquid crystal panel.

The frame corresponds to the one image. In this case, the frame may denote a group of input image data or a group of image data or a group of data voltages corresponding to the one image.

When the liquid crystal panel is driven at (P) Hz, the length between the chargers corresponds to the length of one frame period of the liquid crystal display device driven at (2P) Hz (P is a natural number) The average of the lengths of one frame period corresponds to the length of two frame periods of the liquid crystal display driven by (2P) Hz.

First, the panel 100 is formed by laminating a first substrate (thin film transistor substrate) and a second substrate (color filter substrate). A liquid crystal layer is formed between the first substrate and the second substrate. The first substrate and the second substrate may be manufactured using a base substrate such as glass, plastic, or metal.

Next, the data driver 300 converts the image data input from the control device 400 into analog data voltages, and supplies data of one horizontal line per one horizontal period in which the gate pulse is supplied to the gate line Voltages to the data lines.

The configuration and function of the data driver 300 are the same as those of a data driver applied to a general liquid crystal display device.

However, the output period of the data control signals transmitted from the controller 400 to the data driver 200 may be changed every at least one frame.

For example, as the blanking period is varied, the time at which the data voltages are output to the data lines may be changed. Thus, the timing at which a data control signal, for example, a source output enable signal, to be supplied to the data driver 300 so that the data voltages are output to the data lines may be changed.

In other words, the configuration of the data driver 300 applied to the present invention is not changed as compared with the conventional one. However, the timing at which data control signals transmitted from the controller 400 to the data driver 300 are input to the data driver 300 may be changed. The timing to be input to the data driver 300 is controlled by the control device 400.

The gate driver 200 sequentially supplies gate pulses to the gate lines GL1 to GLg of the panel 100 in response to a gate control signal GCS input from the controller 400 . Accordingly, the switching transistors formed in each pixel of the corresponding horizontal line to which the gate pulse is input are turned on, so that the data voltage can be charged to each pixel.

For example, the gate driver 200 shifts a gate start pulse (GSP) transmitted from the control device 400 according to a gate shift clock (GSC) Supplies the gate pulse to the gate lines GL1 to GLg sequentially in accordance with a gate output enable (GOE) signal during the charging period.

The gate driver 200 supplies gate off signals to the gate lines GL1 to GL2g during the remaining period when no gate pulse is supplied. The switching transistor is turned off by the gate off signal. During the blanking period after the switching transistor is turned off, the data voltage charged in the pixel remains unchanged. The gate pulse and the gate off signal are generically referred to as a gate signal.

The gate driver 200 may be formed independently from the panel 100 and may be electrically connected to the panel 100 in various ways, (Gate In Panel: GIP) method. A gate start signal corresponding to the gate start pulse GSP may be transmitted from the control device 400 to the gate driver 200 configured in the GIP method.

The configuration and function of the gate driver 200 are the same as those of a gate driver applied to a general liquid crystal display device.

However, the period of the gate start pulse transmitted from the control device 400 to the gate driver 200 and the period of the reset signal for resetting the gate driver 200 may be changed every at least one frame .

In addition, the configuration and function of the gate driver 200 applied to the present invention are the same as those of a gate driver applied to a general liquid crystal display device. However, the gate control signals transmitted from the control device 400 to the gate driver 200, for example, the period of the gate start pulse and the reset signal may be changed at least every one frame.

In other words, the configuration of the gate driver 200 applied to the present invention is not changed as compared with the conventional one. However, the timing at which the gate control signals transmitted from the controller 400 to the gate driver 200 are input to the gate driver 200 may be changed. The timing input to the gate driver 200 is controlled by the control device 400. [

Finally, the control device 400 according to the present invention uses a vertical synchronizing signal, a horizontal synchronizing signal, and a clock (CLK) supplied from an external system (not shown) (hereinafter simply referred to as a "timing signal" And outputs a gate control signal (GCS) for controlling the gate driver (200) and a data control signal (DCS) for controlling the data driver (300).

The gate control signals GCS generated in the controller 400 include the gate start pulse GSP, the gate shift clock, the gate output enable signal, the reset signal, and the like.

The data control signals DCS generated by the controller 400 include a source start pulse, a source shift clock signal, a source output enable signal, a polarity control signal, and the like.

The controller 400 rearranges the input image data (Input RGB) input from the external system and supplies the rearranged image data RGB to the data driver 300.

In particular, the controller 400 maintains the length between the chargers in all frames constantly, and uses the timing signal to vary the length of the blanking period for each at least one frame.

For example, when the length of the blanking period in the first frame period corresponding to the first frame corresponds to the period in which 2408 clocks (CLK) are output, the control device 400 corresponds to the second frame The length of the blanking period in the second frame period may be set to a period in which 2534 clocks CLK are output.

In addition, the controller 400 may set the length of the blanking period in the third frame period corresponding to the third frame to a period in which 266 clocks (CLK) are output.

The control device 400 transmits the gate start pulse to the gate driver at the start of the charging period in one frame period, and the gate driver 200 applies the gate pulse only between the charger Gate lines.

Thus, between the chargers, the data voltages are charged with the pixels, and during the blanking period after the charging period, the data voltages of the pixels are maintained.

The control device 400 can sequentially increase the length of the blanking period for each frame, and sequentially decrease the length of the blanking period.

As described above, the control device 400 can change the length of the blanking period for each at least one frame.

In particular, the controller 400 may sequentially increase the length of the blanking period, and then sequentially reduce the length of the blanking period.

In this case, the controller 400 may sequentially increase the length of the blanking period, and sequentially reduce the length of the blanking period, in units of nP frames. Here, n is a natural number of 1 or more.

For example, when P is 30, that is, when the liquid crystal display is driven at 30 Hz, and when the length between the chargers corresponds to a period in which 2048 clocks (CLK) are output, The length of the blanking period in the first frame period corresponding to the first clock period CLK may correspond to the period in which 2408 clocks CLK are output. In this case, the length of the first frame period may correspond to a period in which 4456 clocks (CLK) are output, as shown in FIG. 4 (a).

In this case, the control device 400 can increase the length of the blanking period in the second frame period by the period in which the nine clocks are outputted, and accordingly, the length of the second frame period is as shown in FIG. 7A, the period corresponding to the output of 4465 clocks (CLK). The length between the chargers in the second frame period is the same as the length between the chargers in the first frame period.

Thereafter, the control device 400 may increase the length of the blanking period in the third frame period to the thirtieth frame period by a predetermined length. In this case, the length between the chargers in all the frame periods is maintained at a length corresponding to the output length of 2048 clocks (CLK), as described above.

Therefore, as shown in FIG. 4A, the lengths of the first frame period to the third frame period are such that 4708 clocks (CLKI) are output from the length of the period in which 4456 clocks (CLK) are output Lt; RTI ID = 0.0 > period. ≪ / RTI >

The period from the first frame period to the 30th frame period is referred to as a first period, and the period from the first frame period to the 30th frame period subsequent to the 30 < th > frame is referred to as a second period.

In the second period, the controller 400 sets the lengths of the first frame period to the 30th frame period to a period during which 4708 clocks (CLK) are outputted, as shown in FIG. 4 (b) To the length of a period during which 4456 clocks (CLKI) are outputted from the length of the clock signal CLKI.

Accordingly, the controller 400 sequentially increases the length of the blanking period, and sequentially reduces the length of the blanking period at intervals of 60 frames. In this case, n is 2.

If the blanking periods are sequentially decreased (or increased) and then sequentially increased (or decreased) during the first frame period to the 30th frame period in each of the first period and the second period, The length of the blanking period is changed in a period of 30 frames. In this case, n becomes 1.

3, the control device 400 includes an input circuit 410 for receiving the input image data Input RGB and a timing signal, A storage circuit 440 for storing the information on the blanking period and the input image data, the reset signal and the gate start pulse using the timing signal, and for each frame, A control signal generation circuit 420 for outputting a start pulse to the gate driver 200 and outputting the reset signal to the gate driver 200 at the end of the charging period, The image data is generated by rearranging the input image data frame by frame, And outputting to the emitter driver 300 includes an alignment circuit 430.

In this case, the image data RGB and the data control signal DCS may be transmitted to the data driver 300 via the output unit 450, and the gate control signal GCS may be transmitted to the output unit 450 to the gate driver 300.

First, the input circuit 410 transmits the input image data received from the external system (not shown) to the storage circuit 440, and transmits the timing signal to the control signal generation circuit 420 . However, the input circuit 410 may transmit the input image data to the sorting circuit 430.

Second, the storage circuit 440 stores the input image data received from the input circuit 410 or the image data received from the sorting circuit 430.

The storage circuit 440 stores information on the length of the blanking period.

Third, the control signal generation circuit 430 generates the gate control signal and the data control signal using the timing signal and information on the length of the blanking period.

Fourth, the alignment circuit 430 converts the input image data Input RGB into the image data RGB.

The alignment circuit 430 may output the image data RGB to the data driver in accordance with the charging period.

In addition, the alignment circuit 430 may transmit the image data RGB to the storage circuit 440. In this case, the storage circuit 440 transmits the image data RGB to the data driver 300 according to a control signal transmitted from the alignment circuit 430 or the input circuit 410. In this case, the alignment circuit 430 or the input circuit 410 controls the output timing of the storage circuit 440 so that the image data RGB can be transmitted to the data driver in accordance with the charging period .

The sorting circuit 430 or the input circuit 410 may use the information about the length of the blanking period stored in the storage circuit 440 and information on the length between the chargers, And transmits the image data to the data driver 300 at the start of the charging period.

Also, the control signal generation circuit 430 transmits the gate pulse to the gate driver 200 when the charging period starts, and outputs the reset signal to the gate driver 200 when the charging period ends send.

In addition, the control signal generation circuit 430 transmits the source output enable signal to the data driver 200 when the charging period starts.

FIG. 5 is a diagram illustrating a relationship between a charging period and a blanking period applied to a liquid crystal display device according to the present invention. (a) shows the waveforms of the gate start pulse and the data voltage when the length of the blanking period is shorter than the length of the reference blanking period, (b) shows the waveforms of the gate start pulse and data when the length of the blanking period is the same as the reference blanking period (C) shows waveforms of the gate start pulse and the data voltage when the length of the blanking period is longer than the length of the reference blanking period.

(a), (b), and (c) show that the blanking periods of each of the frame periods applied to the present invention are different from each other.

As described above, the control device 400 may be configured such that the length of the charging period is maintained constant in all the frame periods, and the length of the blanking period is determined using at least one Variable for each frame.

For example, the length of charging in each of the frame periods shown in (a), (b), and (c) corresponds to a period in which 2048 clocks are output. That is, the lengths of charging in each of the frame periods shown in (a), (b) and (c) are the same.

However, the length of the blanking period in the frame period shown in (a) corresponds to the period in which 2408 clocks are output, the length of the blanking period in the frame period shown in (b) corresponds to the period in which 2534 clocks are output And the length of the blanking period in the frame period shown in (c) corresponds to a period in which 2660 clocks are output.

Therefore, the length of the frame period shown in (a) corresponds to a period in which 4456 clocks are output, the length of the frame period shown in (b) corresponds to a period in which 4582 clocks are output, The length of the illustrated frame period corresponds to a period in which 4,708 clocks are output.

the length of the blanking period shown in (b) is the length of the reference blanking period, assuming that the length of the frame period shown in (b) is the length of the frame period applied to the liquid crystal display device driven at 30 Hz.

the length of the blanking period shown in (a) is 5% smaller than the length of the reference blanking period shown in (b). Therefore, the interval of the gate start pulses shown in (a) is smaller than the interval of the gate start pulses shown in (b).

the length of the blanking period shown in (c) is 5% larger than the length of the reference blanking period shown in (b). Therefore, the interval of the gate start pulses shown in (c) is larger than the interval of the gate start pulses shown in (b).

In the liquid crystal display according to the present invention, gate start pulses having intervals shown in (a) to (c) may be sequentially transmitted to the gate driver 200, in which case (a) to (c) The data voltages having the timing as shown in Fig.

To be more specific, in the liquid crystal display device according to the present invention, the gate start pulse for causing the length of the frame period shown in (a) to (c) to be generated can be supplied to the gate driver.

In other words, in the liquid crystal display device according to the present invention, the lengths of the frame periods shown in (a) to (c) can be repeated every three frames.

Further, in the liquid crystal display device according to the present invention, the gate start pulse may be supplied to the gate driver so that a length of a frame period more subdivided than the length of the frame period shown in (a) to (c) is generated .

For example, in the liquid crystal display according to the present invention, the gate start pulses for causing the lengths of the frame periods shown in Fig. 4 to be generated can be supplied to the gate driver.

In this case, in the liquid crystal display device according to the present invention, the length of the frame period shown in Figs. 4A and 4B can be repeated every 60 frames.

In addition, the length of the blanking period is sequentially increased (or decreased), and then decreased (or increased) sequentially again to return to the original length. Thus, the average of the lengths of the blanking period is the length of the reference blanking period.

5 (b), when the length of the blanking period driven at 30 Hz is assumed to be the length of the reference blanking period, the length of the blanking period is set to be longer than the length of the reference blanking period If sequentially increased or decreased, the average of the blanking periods becomes equal to the length of the reference blanking period.

FIG. 6 is another example illustrating the relationship between the charging period and the blanking period applied to the liquid crystal display device according to the present invention. FIG. 5 shows that the lengths of the blanking periods in the respective frame periods are different from each other, and FIG. 6 shows a characteristic in which the lengths of the blanking periods in successive frame periods are sequentially changed. In Fig. 6, the triangle drawn by the solid line indicates the timing at which the gate pulse is output to the liquid crystal panel. For example, during a period corresponding to the length between the chargers, the gate pulse is sequentially output from the gate line arranged at the upper end of the liquid crystal panel to the gate line arranged at the lower end. And the gate pulse is not output to the gate line in the blanking period after the charging period. Therefore, the triangle is not shown in the period corresponding to the length of the blanking period.

The triangle shown by a dotted line in Fig. 6 indicates the timing at which the gate pulse is output when the length of the blanking period is the same.

Further, in Fig. 6, X represents the length between the reference chargers, Y represents the length of the reference blanking period, and a represents the error between the lengths of the blanking periods. In FIG. 5, a corresponds to a period in which 26 clocks are output, and in FIG. 4, a corresponds to a period in which approximately nine clocks are output.

5 shows an example in which the blanking period is changed in a period of three frame periods, and Fig. 4 shows an example in which the blanking period is changed in a period of 60 frame periods. 6 shows an example in which the blanking period is changed in a period of six frame periods.

6A, the interval of the gate start pulses GSP has a magnitude corresponding to X + Y- alpha in one frame period and corresponds to X + Y + alpha in two frame periods And has a size corresponding to X + Y in a three-frame period, a size corresponding to X + Y + alpha in a four-frame period, and a size corresponding to X + Y- , And has a size corresponding to X + Y in the 6-frame period.

To be more specific, the intervals of the gate start pulses GSP are sequentially increased (or decreased) and sequentially decreased (or increased). Therefore, the time point at which the image is output is continuously changed, so that flicker is not generated.

6B, assuming that the length of the reference frame period has a size corresponding to X + Y, since the length of one frame period is reduced to X + Y- ?, the length of the blanking period The length is reduced to Y-a. The length between the chargers in the two-frame period is equal to the length between the chargers in one frame period, and the length of the two-frame period corresponds to X + Y + alpha. That is, the length of two frame periods is longer than the length of one frame period. Therefore, the length of the blanking period in the two-frame period is increased to Y + alpha. The length between the chargers in the three-frame period is equal to the length X between the reference chargers, and the length of the blanking period in the three-frame period is equal to the length Y in the reference blanking period.

From the 4 frame period to the 6 frame period, the length of the blanking period changes from X + Y + alpha to X + Y through X + Y-alpha.

In this case, it can be seen that the length of the average blanking period during six frame periods is X + Y.

According to the present invention as described above, flicker is not generated because the time at which an image is output is continuously changed, and since the lengths of the blanking period and the average lengths of the frame periods have a constant value, And can be stably driven.

The characteristics of the present invention are briefly summarized as follows.

By varying the length of the blanking period, which is a period during which the data voltage is held in the pixels during the charging period and the blanking period that constitute the frame period, the luminance difference generated in the liquid crystal panel driven at a low frequency of 30 Hz or less is reduced .

The magnitude of the decrease in the flicker varies depending on the degree of change in the length of the blanking period.

Simulation results confirm that flicker can be improved to a level of approximately 7.8 dB when the length of the blanking period is increased or decreased at a level of 5% of the length of the reference blanking period.

In order to realize a liquid crystal display device using low power consumption, the present invention drives a liquid crystal panel using a low frequency such as 30 Hz. In this case, as shown in FIG. 5, the charging period and the blanking period are roughly It is alternated by half.

In this case, the present invention can change the length of the blanking period in various ways, whereby the flicker can be reduced.

In other words, if an oxide thin film transistor is used instead of a thin film transistor using amorphous silicon, the leakage current in the blanking period can be reduced. However, if a liquid crystal display device using an oxide thin film transistor is driven at a low frequency for low power consumption, flicker may still be generated.

In order to prevent this, the present invention divides one frame period into a charge period and a blanking period, as described above, and changes the length of the blanking period variously.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: panel 200: gate driver
300: Data driver 400: Control device

Claims (10)

A liquid crystal panel in which pixels are arranged;
A gate driver sequentially supplying gate pulses to the gate lines arranged in the liquid crystal panel;
A data driver for supplying the data voltages generated by the image data to the data lines arranged in the liquid crystal panel while the gate pulse is supplied to any one of the gate lines; And
Generating a gate start pulse for sequentially outputting the gate pulse to the gate lines, transmitting the generated gate pulse to the gate driver, changing input image data to the image data, and transmitting the image data to the data driver A control device,
One frame period is divided into a charge period in which the data voltages are charged to the pixels and a blanking period in which data voltages charged in the pixels are held,
When the liquid crystal panel is driven at (P) Hz, the length between the chargers corresponds to the length of one frame period of the liquid crystal display device driven at (2P) Hz (P is a natural number)
Wherein an average of lengths of one frame period of each of the frames corresponds to a length of two frame periods of a liquid crystal display device driven at (2P) Hz. The method according to claim 1,
P is 30,
Wherein the control device drives the liquid crystal panel at 30 Hz. The method according to claim 1,
The control device includes:
Wherein the length of the blanking period is varied for every at least one frame by using the timing signal. The method according to claim 1,
The control device transmits the gate start pulse to the gate driver at the start of the charging period during one frame period,
Wherein the gate driver supplies the gate pulse to the gate lines only between the chargers. The method according to claim 1,
The control device includes:
Sequentially increasing the length of the blanking period for each frame, and sequentially decreasing the length of the blanking period. 6. The method of claim 5,
The control device includes:
(n is a natural number) for sequentially increasing the length of the blanking period, and sequentially decreasing the length of the blanking period at intervals of nP frames. An input circuit for receiving input image data and a timing signal;
A storage circuit for storing information on a charging period in which data voltages are charged in the pixels, information on a blanking period in which data voltages charged in the pixels are held, and the input image data;
A control signal generation circuit for generating a gate control signal for controlling the gate driver and a data control signal for controlling the data driver using the timing signal; And
And an alignment circuit for generating image data by rearranging the input image data frame by frame and outputting the image data to the data driver so that the data voltage is output during the charging period,
Wherein the control signal generation circuit controls the gate control signal and the data control signal so that the length between the charger is kept constant in all the frames and the length of the blanking period varies for each at least one frame, To generate a control signal. 8. The method of claim 7,
The control signal generation circuit includes:
Generating a reset signal and a gate start pulse using the timing signal, outputting the gate start pulse to the gate driver at the start of the charging period for each frame, and outputting the reset signal to the gate Driver,
And the interval of the gate start pulse is varied for each at least one frame. 8. The method of claim 7,
The alignment circuit comprises:
Converts the input image data transmitted from the storage circuit into the image data, and outputs the image data to the data driver when the charging period starts. 8. The method of claim 7,
The alignment circuit comprises:
Wherein the input circuit converts the input image data transmitted from the input circuit into the image data, transmits the image data to the storage circuit,
The storage circuit comprising:
And transmits the image data to the data driver at the start of the charging period according to a control signal transmitted from the alignment circuit or the input circuit.

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