KR102350538B1 - Ddr 메모리 에러 복구 - Google Patents

Ddr 메모리 에러 복구 Download PDF

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Publication number
KR102350538B1
KR102350538B1 KR1020197003840A KR20197003840A KR102350538B1 KR 102350538 B1 KR102350538 B1 KR 102350538B1 KR 1020197003840 A KR1020197003840 A KR 1020197003840A KR 20197003840 A KR20197003840 A KR 20197003840A KR 102350538 B1 KR102350538 B1 KR 102350538B1
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memory
command
error
queue
response
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Korean (ko)
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KR20190019209A (ko
Inventor
제임스 알. 마그로
루이후아 펭
안소니 아사로
케다나스 발라크리쉬난
스콧 피. 머피
유빈 야오
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G06F9/3855—
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Retry When Errors Occur (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System (AREA)
KR1020197003840A 2016-07-15 2017-07-11 Ddr 메모리 에러 복구 Active KR102350538B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662363075P 2016-07-15 2016-07-15
US62/363,075 2016-07-15
US15/375,076 2016-12-09
US15/375,076 US11675659B2 (en) 2016-07-15 2016-12-09 DDR memory error recovery
PCT/US2017/041559 WO2018013584A1 (en) 2016-07-15 2017-07-11 Ddr memory error recovery

Publications (2)

Publication Number Publication Date
KR20190019209A KR20190019209A (ko) 2019-02-26
KR102350538B1 true KR102350538B1 (ko) 2022-01-14

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KR1020197003840A Active KR102350538B1 (ko) 2016-07-15 2017-07-11 Ddr 메모리 에러 복구

Country Status (6)

Country Link
US (1) US11675659B2 (https=)
EP (1) EP3270290B1 (https=)
JP (1) JP7155103B2 (https=)
KR (1) KR102350538B1 (https=)
CN (1) CN109478158A (https=)
WO (1) WO2018013584A1 (https=)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019074500A1 (en) * 2017-10-11 2019-04-18 Hewlett-Packard Development Company, L.P. MEMORY DEVICES COMPRISING EXECUTION TRACING PADS
KR20190042970A (ko) * 2017-10-17 2019-04-25 에스케이하이닉스 주식회사 메모리 시스템 및 그의 동작방법
KR102485411B1 (ko) * 2018-03-02 2023-01-06 에스케이하이닉스 주식회사 메모리 시스템 및 그것의 동작 방법
CN110729006B (zh) * 2018-07-16 2022-07-05 超威半导体(上海)有限公司 存储器控制器中的刷新方案
US11200106B2 (en) 2019-08-12 2021-12-14 Advanced Micro Devices, Inc. Data integrity for persistent memory systems and the like
CN110727530B (zh) * 2019-09-12 2021-02-19 无锡江南计算技术研究所 基于窗口的错误访存请求重传系统及方法
US11768701B2 (en) * 2019-09-17 2023-09-26 Western Digital Technologies, Inc. Exception analysis for data storage devices
CN112835734A (zh) * 2019-11-25 2021-05-25 深圳市中兴微电子技术有限公司 一种异常处理装置及ddr存储系统
US11392441B2 (en) * 2019-12-30 2022-07-19 Advanced Micro Devices, Inc. Error reporting for non-volatile memory modules
US11531601B2 (en) * 2019-12-30 2022-12-20 Advanced Micro Devices, Inc. Error recovery for non-volatile memory modules
US11137941B2 (en) 2019-12-30 2021-10-05 Advanced Micro Devices, Inc. Command replay for non-volatile dual inline memory modules
US11099786B2 (en) * 2019-12-30 2021-08-24 Advanced Micro Devices, Inc. Signaling for heterogeneous memory systems
US20210357336A1 (en) * 2020-05-14 2021-11-18 Advanced Micro Devices, Inc. Efficient memory bus management
US11561862B2 (en) 2020-05-29 2023-01-24 Advanced Micro Devices, Inc. Refresh management for DRAM
US11625352B2 (en) * 2020-06-12 2023-04-11 Advanced Micro Devices, Inc. DRAM command streak management
US11249839B1 (en) * 2020-08-14 2022-02-15 Rockwell Automation Technologies, Inc. Method and apparatus for memory error detection
MY206628A (en) * 2020-11-20 2024-12-27 Skyechip Sdn Bhd A memory sequencer system and a method of memory sequencing using thereof
US11636054B2 (en) * 2021-03-31 2023-04-25 Advanced Micro Devices, Inc. Memory controller power states
TWI807919B (zh) * 2022-07-14 2023-07-01 群聯電子股份有限公司 資料重讀方法、記憶體儲存裝置及記憶體控制電路單元
CN115629901A (zh) * 2022-10-26 2023-01-20 北京奥星贝斯科技有限公司 日志回放方法及装置、数据恢复方法及装置、电子设备
US12158827B2 (en) * 2022-12-29 2024-12-03 Advanced Micro Devices, Inc. Full dynamic post-package repair
CN116302659B (zh) * 2023-04-27 2023-08-08 摩尔线程智能科技(北京)有限责任公司 Gpu显存错误处理方法及装置、电子设备和存储介质
CN116701256A (zh) * 2023-06-05 2023-09-05 牛芯半导体(深圳)有限公司 多通道仲裁器电路、接口芯片及数据访问方法
WO2025096946A1 (en) * 2023-11-03 2025-05-08 Advanced Micro Devices, Inc. Error alert encoding for improved error mitigation
CN119938146A (zh) * 2023-11-03 2025-05-06 腾讯科技（深圳）有限公司 包括重发队列的芯片、计算机设备和重发指令的处理方法
CN119537088B (zh) * 2025-01-21 2025-04-11 芯思原微电子有限公司 一种ddr控制器校验错误重传系统

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6128747A (en) * 1997-01-28 2000-10-03 Hewlett Packard Company System for delaying propagation of wake-up signal to processor through the sleep control means until the memory is awakened
US20040153769A1 (en) * 1999-12-28 2004-08-05 Yung-Hsiang Lee Technique for synchronizing faults in a processor having a replay system
US20110040924A1 (en) * 2009-08-11 2011-02-17 Selinger Robert D Controller and Method for Detecting a Transmission Error Over a NAND Interface Using Error Detection Code

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3875749B2 (ja) * 1996-08-08 2007-01-31 富士通株式会社 マルチプロセッサ装置及びそのメモリアクセス方法
US6256745B1 (en) * 1998-06-05 2001-07-03 Intel Corporation Processor having execution core sections operating at different clock rates
US6772324B2 (en) * 1997-12-17 2004-08-03 Intel Corporation Processor having multiple program counters and trace buffers outside an execution pipeline
US6625756B1 (en) 1997-12-19 2003-09-23 Intel Corporation Replay mechanism for soft error recovery
US6952764B2 (en) * 2001-12-31 2005-10-04 Intel Corporation Stopping replay tornadoes
US7587625B2 (en) * 2006-02-16 2009-09-08 Intel Corporation Memory replay mechanism
US7852867B2 (en) * 2007-07-06 2010-12-14 Integrated Deoice Technology, Inc. Integrated memory for storing egressing packet data, replay data and to-be egressed data
US7770064B2 (en) * 2007-10-05 2010-08-03 International Business Machines Corporation Recovery of application faults in a mirrored application environment
US8132048B2 (en) * 2009-08-21 2012-03-06 International Business Machines Corporation Systems and methods to efficiently schedule commands at a memory controller
US8307270B2 (en) * 2009-09-03 2012-11-06 International Business Machines Corporation Advanced memory device having improved performance, reduced power and increased reliability
US8738995B2 (en) * 2009-09-10 2014-05-27 Hewlett-Packard Development Company, L.P. Memory subsystem having a first portion to store data with error correction code information and a second portion to store data without error correction code information
US8677203B1 (en) * 2010-01-11 2014-03-18 Apple Inc. Redundant data storage schemes for multi-die memory systems
EP2378452B1 (en) * 2010-04-16 2012-12-19 Thomson Licensing Method, device and computer program support for verification of checksums for self-modified computer code
US8365015B1 (en) 2010-08-09 2013-01-29 Nvidia Corporation Memory-based error recovery
US8549383B2 (en) * 2011-08-24 2013-10-01 Oracle International Corporation Cache tag array with hard error proofing
US8549154B2 (en) * 2011-09-09 2013-10-01 Oracle International Corporation Recovering stateful read-only database sessions
US9202577B2 (en) * 2012-03-30 2015-12-01 Intel Corporation Solid state drive management in power loss recovery
US9575892B2 (en) 2013-03-15 2017-02-21 Nvidia Corporation Replaying memory transactions while resolving memory access faults
CN103258820B (zh) * 2013-04-09 2016-12-28 北京兆易创新科技股份有限公司 SPI接口的增强型Flash芯片及芯片封装方法
GB2513333A (en) * 2013-04-23 2014-10-29 Ibm Method and apparatus for testing a storage system
US9250995B2 (en) 2013-05-29 2016-02-02 Seagate Technology Llc Protection of data in memory
US9767044B2 (en) * 2013-09-24 2017-09-19 Intel Corporation Secure memory repartitioning
US10270705B1 (en) * 2013-12-18 2019-04-23 Violin Systems Llc Transmission of stateful data over a stateless communications channel
US9342402B1 (en) * 2014-01-28 2016-05-17 Altera Corporation Memory interface with hybrid error detection circuitry for modular designs
US9229885B2 (en) * 2014-05-21 2016-01-05 Freescale Semiconductor, Inc. Adaptive scheduling queue control for memory controllers based upon page hit distance determinations
JP6439363B2 (ja) 2014-10-06 2018-12-19 富士通株式会社 記憶制御装置および記憶制御装置の制御方法
FR3027176B1 (fr) * 2014-10-13 2016-12-09 Oberthur Technologies Rejeu d'un batch de commandes securisees dans un canal securise
US20180081691A1 (en) * 2016-09-21 2018-03-22 Qualcomm Incorporated REPLAYING SPECULATIVELY DISPATCHED LOAD-DEPENDENT INSTRUCTIONS IN RESPONSE TO A CACHE MISS FOR A PRODUCING LOAD INSTRUCTION IN AN OUT-OF-ORDER PROCESSOR (OoP)
US10642536B2 (en) * 2018-03-06 2020-05-05 Western Digital Technologies, Inc. Non-volatile storage system with host side command injection
US10572185B2 (en) * 2018-06-01 2020-02-25 Western Digital Technologies, Inc. Non-volatile storage system with command replay
US12321622B2 (en) * 2021-08-25 2025-06-03 Intel Corporation Deferred ECC (error checking and correction) memory initialization by memory scrub hardware

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6128747A (en) * 1997-01-28 2000-10-03 Hewlett Packard Company System for delaying propagation of wake-up signal to processor through the sleep control means until the memory is awakened
US20040153769A1 (en) * 1999-12-28 2004-08-05 Yung-Hsiang Lee Technique for synchronizing faults in a processor having a replay system
US20110040924A1 (en) * 2009-08-11 2011-02-17 Selinger Robert D Controller and Method for Detecting a Transmission Error Over a NAND Interface Using Error Detection Code

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Publication number Publication date
EP3270290A1 (en) 2018-01-17
CN109478158A (zh) 2019-03-15
WO2018013584A1 (en) 2018-01-18
US20180018221A1 (en) 2018-01-18
JP2019527424A (ja) 2019-09-26
JP7155103B2 (ja) 2022-10-18
US11675659B2 (en) 2023-06-13
KR20190019209A (ko) 2019-02-26
EP3270290B1 (en) 2021-03-24

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