KR102336909B1 - Method of inspecting a wafer - Google Patents

Abstract

A wafer inspection method is disclosed. The method includes imaging a wafer including a plurality of semiconductor dies to obtain a wafer image, comparing the semiconductor dies with a reference image to perform a pass/fail decision on the semiconductor dies, and using the determination result generating a wafer map using the method; comparing the die arrangement of the generated wafer map with the die arrangement of a reference wafer map provided from an inspection server; and, as a result of the comparison, the die arrangement of the generated wafer map and the and stopping the inspection process if the die arrangement of the reference wafer map is different.

Description

Method of inspecting a wafer

Embodiments of the present invention relate to a wafer inspection method. More particularly, it relates to a method of inspecting a wafer divided into a plurality of dies by a dicing process in a semiconductor manufacturing process.

Semiconductor devices, such as integrated circuit devices, can be generally formed by repeatedly performing a series of processing processes on a substrate such as a silicon wafer. For example, a deposition process for forming a film on a wafer, an etching process for forming the film into patterns having electrical characteristics, an ion implantation process or diffusion process for implanting or diffusing impurities into the patterns, and a process in which the patterns are formed The semiconductor devices may be formed on the wafer by repeatedly performing cleaning and rinsing processes for removing impurities from the wafer.

The wafer may be thinned through a back grinding process and a dicing process, and may be divided into a plurality of individualized semiconductor dies. The semiconductor dies may be attached to a dicing tape mounted on a mount frame having a substantially circular ring shape, and may be manufactured into a semiconductor package through a die bonding process and a molding process.

The wafer attached to the dicing tape may be inspected for a divided state and external defects through an inspection device, and subsequent processes such as a die bonding process may be selectively performed on dies determined as good products as a result of the inspection. .

As an example, Korean Patent Application Laid-Open Nos. 10-2010-0029532 and 10-2013-0130510 disclose an inspection device having a camera and an oblique illumination, and the Korean Patent Application No. 10-2014-0063117 discloses a wafer inspection apparatus including a chuck for supporting a wafer, an inspection unit for inspecting the wafer, and the like.

The wafer inspection apparatus may acquire a wafer image by imaging a wafer including a plurality of semiconductor dies, and may compare each semiconductor dies with a reference image to determine whether or not the semiconductor dies are acceptable. Also, the wafer inspection apparatus may generate a wafer map using the inspection result and transmit the inspection result to the inspection server. However, when the defect rate is abnormally high, that is, when an error in which non-defective semiconductor dies are determined to be defective occurs, there is no countermeasure for this, and thus, there may be a problem in that non-defective semiconductor dies are discarded in a subsequent process.

SUMMARY An object of the present invention is to provide a wafer inspection method capable of improving inspection reliability for semiconductor dies.

According to embodiments of the present invention, a wafer inspection method includes: acquiring a wafer image by imaging a wafer including a plurality of semiconductor dies; and comparing the semiconductor dies with a reference image to determine whether the semiconductor dies are acceptable or not. performing, generating a wafer map by using the determination result, comparing the die arrangement of the generated wafer map with the die arrangement of a reference wafer map provided from an inspection server, and the comparison result The method may include stopping the inspection process when the die arrangement of the generated wafer map and the die arrangement of the reference wafer map are different from each other.

According to embodiments of the present disclosure, the method may further include transmitting an inspection result to an inspection server when, as a result of the comparison, the die arrangement of the generated wafer map and the die arrangement of the reference wafer map are identical to each other. have.

According to embodiments of the present invention, the generated wafer map may be converted into one character string and then compared with the reference wafer map.

According to embodiments of the present invention, the generated wafer map consists of numbers or letters arranged in the form of a plurality of columns and rows, and numbers or letters corresponding to areas other than the wafer can be compared with the reference wafer map. have.

According to embodiments of the present invention, the method includes calculating the defective rate of the semiconductor dies, comparing the calculated defective rate with a preset defective rate, and when the calculated defective rate is higher than the preset defective rate The method may further include stopping the inspection process.

According to embodiments of the present invention, the wafer may be loaded into the inspection apparatus while being mounted on a ring-shaped mount frame by a dicing tape.

According to the embodiments of the present invention as described above, pass/fail determination is performed on semiconductor dies using a wafer image, a wafer map is generated using the determination result, and a die arrangement state of the generated wafer map can be confirmed by comparing with the reference wafer map. Accordingly, problems in which a defective rate is abnormally increased or defective semiconductor dies are recorded as defective due to an error in the die arrangement of the generated wafer map can be sufficiently solved.

In addition, by calculating the defective rate of the semiconductor dies and comparing the calculated defective rate with a preset defective rate, it is possible to quickly respond to a case in which the defective rate is abnormally increased. In particular, it is possible to quickly perform improvement work, such as identifying the cause of the abnormal increase in the defect rate and taking action on the identified cause.

As a result, the reliability of the wafer inspection process may be greatly improved, and problems such as scrapping of non-defective semiconductor dies in a subsequent process may be sufficiently resolved.

1 is a flowchart illustrating a wafer inspection method according to an embodiment of the present invention.
FIG. 2 is a schematic configuration diagram for explaining an inspection apparatus for performing the wafer inspection method illustrated in FIG. 1 .

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention should not be construed as being limited to the embodiments described below and may be embodied in various other forms. The following examples are provided to sufficiently convey the scope of the present invention to those skilled in the art, rather than being provided so that the present invention can be completely completed.

In embodiments of the present invention, when an element is described as being disposed or connected to another element, the element may be directly disposed or connected to the other element, and other elements may be interposed therebetween. it might be Conversely, when one element is described as being directly disposed on or connected to another element, there cannot be another element between them. Although the terms first, second, third, etc. may be used to describe various items such as various elements, compositions, regions, layers and/or portions, the items are not limited by these terms. will not

The terminology used in the embodiments of the present invention is only used for the purpose of describing specific embodiments, and is not intended to limit the present invention. Further, unless otherwise limited, all terms including technical and scientific terms have the same meaning as understood by one of ordinary skill in the art of the present invention. The above terms, such as those defined in ordinary dictionaries, shall be interpreted as having meanings consistent with their meanings in the context of the related art and description of the present invention, ideally or excessively outwardly intuitive, unless clearly defined. will not be interpreted.

Embodiments of the present invention are described with reference to schematic diagrams of ideal embodiments of the present invention. Accordingly, changes from the shapes of the diagrams, eg, changes in manufacturing methods and/or tolerances, are those that can be fully expected. Accordingly, the embodiments of the present invention are not to be described as being limited to the specific shapes of the areas described as diagrams, but rather to include deviations in the shapes, and the elements described in the drawings are purely schematic and their shapes It is not intended to describe the precise shape of the elements, nor is it intended to limit the scope of the present invention.

1 is a flowchart illustrating a wafer inspection method according to an embodiment of the present invention, and FIG. 2 is a schematic configuration diagram illustrating an inspection apparatus for performing the wafer inspection method illustrated in FIG. 1 .

1 and 2 , the wafer inspection method according to an embodiment of the present invention may be preferably used to perform an inspection process on a wafer 10 including semiconductor dies. In particular, it can be preferably used for a wafer 10 divided into a plurality of dies by a dicing process, wherein the wafer 10 is provided in a state mounted on a ring-shaped mount frame by a dicing tape. can

The inspection apparatus 100 for performing the wafer inspection method includes a load port 110 for supporting a cassette 40 in which a plurality of wafers 10 are accommodated, and a wafer for supporting the wafer 10 . A chuck 120 , a wafer transfer unit 140 for transferring the wafer 10 in a horizontal direction between the cassette 40 and the wafer chuck 120 , and a wafer supported on the wafer chuck 120 . It may include an inspection unit 150 for inspecting (10). In particular, guide rails 160 extending in a horizontal direction to guide the wafer 10 transferred by the wafer transfer unit 140 between the cassette 40 and the wafer chuck 120 are connected to the load port ( 110) may be disposed adjacent to.

In addition, the wafer inspection apparatus 100 includes an alignment unit 170 for aligning the wafer 10 supported on the wafer chuck 120 , and the wafer 10 supported on the wafer chuck 120 . It may include an inspection unit 150 for inspection and an electrical unit 102 for operating the wafer inspection apparatus 100 .

The wafer chuck 120 includes a load and unload area for loading and unloading of the wafer 10 , and an alignment for alignment of the wafer 10 for loading and unloading and alignment and inspection of the wafer 10 . It may be configured to be movable in the horizontal direction by the horizontal driving unit 130 between the region and the inspection region for inspection of the wafer 10 . As an example, the load and unload regions may be positioned on opposite sides of the cassette 40 with respect to the guide rails 160 , and the alignment region and the inspection region may be positioned adjacent to the load and unload regions. can

As an example, a pair of guide rails 160 may extend in parallel with each other between the cassette 40 and the load and unload areas, and are transferred from the cassette 40 by the wafer transfer unit 140 . The loaded wafer 10 may be loaded on the wafer chuck 120 positioned in the load and unload areas. In addition, the wafer 10 on which the inspection process has been completed may be accommodated in the cassette 40 from the load and unload areas by the wafer transfer unit 140 .

Although not shown in detail, the inspection unit 150 may include an inspection camera to acquire an image of the wafer 10 . As an example, the inspection unit 150 may include a line scan camera for acquiring a wafer image. The horizontal driving unit 130 may move the wafer chuck 120 to the inspection area under the inspection camera, and then move the wafer chuck 120 in the inspection area in the horizontal direction to obtain an inspection image. can

Since the above-described wafer inspection apparatus 100 is disclosed in more detail in Korean Patent Application No. 10-2014-0063117 filed by the present applicant, an additional detailed description thereof will be omitted.

Hereinafter, a wafer inspection method according to an embodiment of the present invention will be described with reference to the accompanying drawings.

First, a wafer image is obtained by imaging the wafer 10 including a plurality of semiconductor dies in step S100 . The wafer image may be acquired by the inspection camera, and the horizontal driving unit 130 may horizontally move the wafer 10 to acquire the wafer image.

In operation S110 , the semiconductor dies are compared with a reference image to determine whether the semiconductor dies are acceptable or not. The comparison may be sequentially performed in a die-to-die comparison method. In this case, the inspection apparatus 100 may receive the reference wafer map and information on the semiconductor dies from the inspection server. The reference wafer map may have the form of one character string, and the character string may be composed of a space and numbers or letters. In addition, the inspection apparatus 100 may receive information on the number of rows and columns for constituting the wafer map, and may generate a wafer map in a subsequent step using the information.

As an example, in the reference wafer map, areas other than the wafer may be displayed as blank, and the dies to be inspected may be represented by the number '1'. In addition, the wafer edge regions and the dies previously determined to be defective in the previous process may be indicated by different numbers or letters, respectively.

In step S120, a wafer map is generated according to the determination result in step S110. As an example, regions other than the wafer may be indicated by the number '0', and non-defective semiconductor dies may be indicated by the number '1'. In addition, the wafer edge regions and the semiconductor dies determined to be defective may be indicated by different numbers or letters, respectively. In this case, when the information of the dies provided from the inspection server and the determination result are different, the information provided from the inspection server may be applied first. For example, when a die previously determined to be defective in the information provided from the inspection server is determined to be good in step S110, the die may be recorded as defective according to information provided from the inspection server. However, when the die previously determined to be good in the information provided from the inspection server is determined to be defective in step S110, the die may be recorded as defective.

In operation S130 , a defective rate of the semiconductor dies is calculated. The defective rate may indicate a ratio of defective semiconductor dies to all semiconductor dies or good semiconductor dies, and may be used to detect an abnormal defective rate.

As an example, the state in which the semiconductor dies are attached to the dicing tape is poor, that is, each semiconductor die is attached to the dicing tape in a state that is inclined to one side, or the front or rear surface of the dicing tape is contaminated by foreign substances. When this occurs, a large amount of defects can be detected. That is, dies determined to be defective may be generated even though the semiconductor dies themselves are not defective.

In addition, if there is an error in the die arrangement of the wafer map generated using the determination result, a large amount of defects may occur. For example, when the wafer map is generated, row and column information is incorrectly applied, so that the determination result for dies in a row or column partially or entirely is not recorded in an appropriate position and is pushed to one side. In this case, defective semiconductor dies may be recorded as defective, and accordingly, the defective rate may be abnormally increased.

According to an embodiment of the present invention, the calculated defective rate may be compared with a preset defective rate in step S140, and when the calculated defective rate is higher than the preset defective rate in step S150, the inspection process may be stopped.

When the inspection process is stopped in step S150, after solving the cause of the abnormally high defective rate, the inspection process may be performed again. For example, if the attachment state of the semiconductor dies is poor or the dicing tape is contaminated, steps such as correcting the attachment state to the wafer or replacing the dicing tape are performed, and then the inspection process of the wafer can be performed again.

However, the cause may be a die arrangement error of the wafer map, and according to an embodiment of the present invention, the die arrangement state of the wafer map may be inspected to confirm this. In addition, even when the calculated defect rate is lower than the preset defect rate, there is a possibility that a defective semiconductor die may be recorded as defective due to a die arrangement error of the wafer map, so it is necessary to sufficiently check the die arrangement error of the wafer map.

According to an embodiment of the present invention, the die arrangement of the generated wafer map and the die arrangement of the reference wafer map may be compared in step S160. As an example, the generated wafer map may be converted into the same format as the reference wafer map, that is, into a single string, and then compared with the reference wafer map. In particular, numbers or letters corresponding to areas other than the wafer in the converted wafer map may be compared with the reference wafer map. For example, when regions corresponding to the number '0' in the converted wafer map are not blank in the reference wafer map, it may be determined that an error has occurred in the die arrangement of the generated wafer map.

As described above, when an error in the arrangement of dies occurs in the wafer map generated according to the inspection result, that is, when the die arrangement of the generated wafer map and the reference wafer map are different from each other, the inspection process may be stopped in step S170 .

Unlike the above, when the die arrangement of the generated wafer map and the reference wafer map in step S180 is the same, the inspection result may be transmitted to the inspection server.

Meanwhile, when a die arrangement error of the wafer map occurs as described above, the wafer map may be regenerated after rechecking the information on the rows and columns of the semiconductor dies, and the steps after step S130 may be performed again.

In addition, according to the above description, the defect rate according to the inspection result of the semiconductor dies is first checked and then the arrangement error of the wafer map is checked. Alternatively, the defect rate may be confirmed after first checking the arrangement error of the wafer map.

According to the embodiments of the present invention as described above, the inspection result for the semiconductor dies may be more accurately obtained by checking the arrangement error of the wafer map, and abnormal inspection results may be obtained by checking the defect rate of the semiconductor dies. can be prevented in advance. As a result, the reliability of the wafer inspection process can be greatly improved, and the problem of discarding non-defective semiconductor dies in a subsequent process can be sufficiently solved.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention as set forth in the claims below. You will understand that it can be done.

10: substrate 100: wafer inspection device
110: load port 120: wafer chuck
130: horizontal driving unit 140: wafer transfer unit
150: inspection unit 160: guide rail
170: alignment unit

Claims (6)

acquiring a wafer image by imaging a wafer including a plurality of semiconductor dies;
comparing the semiconductor dies with a reference image to determine whether the semiconductor dies are acceptable;
generating a wafer map using the determination result;
comparing the die arrangement of the generated wafer map with the die arrangement of a reference wafer map provided from an inspection server; and
Comprising the step of stopping the inspection process when the die arrangement of the generated wafer map and the die arrangement of the reference wafer map are different from each other as a result of the comparison,
The reference wafer map has the form of one string, and the wafer map consists of numbers or letters arranged in the form of a plurality of rows and columns,
A wafer inspection method, characterized in that after converting the wafer map into the same string form as the reference wafer map, numbers or letters corresponding to areas other than the wafer are compared with the reference wafer map. The method of claim 1 , further comprising: transmitting the inspection result to an inspection server when the die arrangement of the generated wafer map and the die arrangement of the reference wafer map are identical to each other as a result of the comparison. delete delete The method of claim 1 , further comprising: calculating a defective rate of the semiconductor dies;
comparing the calculated defective rate with a preset defective rate; and
The method of claim 1, further comprising stopping the inspection process when the calculated defect rate is higher than the preset defect rate. The method of claim 1, wherein the wafer is mounted on a ring-shaped mount frame by a dicing tape.

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