KR102315965B1 - Scan Driver and Display Device Using the same - Google Patents

Abstract

The present invention provides a display device including a display panel, a data driver, a scan driver, and a timing controller. The display panel displays an image. The data driver supplies a data signal to the display panel. The scan driver supplies a scan signal to the display panel. The timing controller controls the data driver and the scan driver. The scan driver includes a first scan circuit unit for outputting a scan signal in response to the first control signal output from the timing control unit, and a plurality of scan signals output from the first scan circuit unit in response to the second control signal output from the timing control unit. and a second scan circuit unit that separates and outputs the scan lines.

Description

Scan Driver and Display Device Using the same

The present invention relates to a scan driver and a display device using the same.

As information technology develops, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, the use of display devices such as an organic light emitting display (OLED), a liquid crystal display (LCD), and a plasma display panel (PDP) is increasing.

Some of the above-described display devices, for example, a liquid crystal display device or an organic light emitting display device, include a display panel including a plurality of sub-pixels arranged in a matrix form and a driving unit for driving the display panel. The driver includes a scan driver that supplies a scan signal (or a gate signal) to the display panel and a data driver that supplies a data signal to the display panel.

In the display device as described above, when a scan signal and a data signal are supplied to sub-pixels arranged in a matrix form, the selected sub-pixel emits light to display an image.

The scan driver that outputs the scan signal is an integrated circuit (IC) (non-GIP type) type that is mounted on an external substrate of a display panel and a gate in panel (GIP type) type that is formed with a thin film transistor process. It is divided into a built-in type formed in the display panel.

In the current market, high-resolution models such as UHD (Ultra High Definition) are in the spotlight. According to this trend, the resolution of the display panel will gradually increase in the future. Accordingly, in the case of a display device using an external scan driver, as the resolution increases, the number of scan drivers will also increase, which will lead to an increase in manufacturing cost, and thus improvement is required.

The present invention for solving the problems of the above-described background art can reduce the number of scan drivers required for realizing a large screen and high resolution, as well as provide a scan driver with a high degree of freedom in design to reduce manufacturing costs.

As a means for solving the above problems, the present invention provides a display device including a display panel, a data driver, a scan driver, and a timing controller. The display panel displays an image. The data driver supplies a data signal to the display panel. The scan driver supplies a scan signal to the display panel. The timing controller controls the data driver and the scan driver. The scan driving unit includes a first scan circuit unit for outputting a scan signal in response to a first control signal output from the timing control unit, and a plurality of scan signals output from the first scan circuit unit in response to a second control signal output from the timing control unit. and a second scan circuit unit that separates and outputs the scan lines.

The second scan circuit unit may delay and separate the scan signal output from the first scan circuit unit and output it to a plurality of scan lines.

The second scan circuit unit may separate the scan signal output from the first scan circuit unit and output it to a plurality of scan lines.

The first scan circuit unit and the second scan circuit unit may be composed of 1:K (K is an integer greater than or equal to 2).

The first scan circuit unit may be mounted in the form of an integrated circuit on a flexible film connected to the display panel, and the second scan circuit unit may be formed in the form of a gate-in-panel in a non-display area of the display panel.

The second scan circuit unit may include a first circuit unit that is activated in response to a gate output control signal and a second circuit unit that is deactivated.

The second scan circuit unit outputs a scan-on voltage that turns on the transistors of the sub-pixels included in the display panel when the first circuit unit is activated, and turns off the transistors of the sub-pixels included in the display panel when the second circuit unit is activated. A scan-off voltage can be output.

In another aspect, the present invention provides a first scan circuit unit for outputting a scan signal in response to a first control signal supplied from an external device, and a scan signal output from the first scan circuit unit in response to a second control signal supplied from an external device. Provided is a scan driving unit including a second scan circuit unit that separates and outputs the .

The first scan circuit unit and the second scan circuit unit may be composed of 1:K (K is an integer greater than or equal to 2).

The second scan circuit unit outputs a scan-on voltage that turns on the transistors of the sub-pixels included in the display panel when the first circuit unit is activated, and turns off the transistors of the sub-pixels included in the display panel when the second circuit unit is activated. A scan-off voltage can be output.

The present invention has an effect of reducing the number of integrated circuits required for realizing a large screen and high resolution because the scan driver is configured using a circuit unit composed of at least one integrated circuit and a circuit unit for separating (or distributing) a scan signal output therefrom. have. In addition, according to the present invention, since a circuit generating a scan signal and a circuit dividing (or distributing) a plurality of scan signals are separated, the degree of freedom in design is high in response to the resolution of the display device, and manufacturing cost can be reduced. .

1 is a block diagram schematically showing a display device;
FIG. 2 is a configuration diagram schematically illustrating a sub-pixel shown in FIG. 1;
3 is a schematic diagram illustrating a conventionally proposed scan driver.
4 is a view showing a display device implemented using a conventionally proposed scan driver.
5 is a diagram schematically illustrating a scan driver according to an embodiment of the present invention;
6 is a view showing a display device implemented using a scan driver according to an embodiment of the present invention.
7 is a diagram illustrating a connection relationship for each configuration of a scan driving unit according to an embodiment of the present invention.
8 is a waveform diagram showing a scan signal output from a first scan circuit unit;
9 is a waveform diagram for explaining a control timing of a second scan circuit unit;
10 is a waveform diagram showing a scan signal output from a second scan circuit unit;
11 is a circuit configuration diagram showing a part of a second scan circuit unit;
12 is a view showing a display device implemented using a scan driver according to an embodiment of the present invention;

Hereinafter, specific details for carrying out the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram schematically illustrating a display device, and FIG. 2 is a configuration diagram schematically illustrating a sub-pixel illustrated in FIG. 1 .

As shown in FIG. 1 , the display device includes an image supply unit 110 , a timing controller 120 , a scan driver 130 , a data driver 140 , and a display panel 150 .

The image supply unit 110 processes the data signal and outputs it together with a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. The image supply unit 110 supplies a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a clock signal, and a data signal to the timing control unit 120 .

The timing control unit 120 receives a data signal from the image supply unit 110 , and includes a first control signal (hereinafter referred to as a gate timing control signal) (GDC) for controlling the operation timing of the scan driver 130 , A second control signal (hereinafter referred to as a gate output control signal) GCS and a data timing control signal DDC for controlling the operation timing of the data driver 140 are output. The timing controller 120 supplies the data signal DATA together with the data timing control signal DDC to the data driver 140 .

The scan driver 130 outputs a scan signal (or gate) while shifting the level of the gate voltage in response to the gate timing control signal GDC and the gate output control signal GCS supplied from the timing controller 120 . The scan driver 130 supplies a scan signal to the sub-pixels SP included in the display panel 150 through the gate lines GL1 to GLm.

The data driver 140 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120 , and converts the digital signal into an analog signal in response to the gamma reference voltage and outputs it . The data driver 140 supplies the data signal DATA to the sub-pixels SP included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 is formed in the form of an integrated circuit (IC).

The display panel 150 displays an image corresponding to the gate signal supplied from the scan driver 130 and the data signal DATA supplied from the data driver 140 . The display panel 150 includes sub-pixels SP that emit light by itself or control external light to display an image.

As shown in FIG. 2 , one sub-pixel is supplied through the switching thin film transistor SW and the switching thin film transistor SW connected to (or formed at the intersection of) the scan line GL1 and the data line DL1. A pixel circuit PC operating in response to the data signal DATA is included. The sub-pixels SP are composed of a liquid crystal display panel including a liquid crystal element or an organic light emitting display panel including an organic light emitting element according to the configuration of the pixel circuit PC.

When the display panel 150 is configured as a liquid crystal display panel, it is a TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS (Fringe Field Switching) mode, or ECB (Electrically Controlled Birefringence) mode. implemented in mode. When the display panel 150 is configured as an organic light emitting display panel, it is implemented in a top-emission method, a bottom-emission method, or a dual-emission method.

In the display device as described above, when a scan signal and a data signal are supplied to sub-pixels arranged in a matrix form, the selected sub-pixel emits light to display an image.

On the other hand, the scan driver that outputs the scan signal is an integrated circuit (IC) (non-GIP type) type that is mounted on an external substrate of a display panel and a gate in panel (GIP type) formed together with a thin film transistor process. ) in the form of a built-in type formed on the display panel.

In the current market, high-resolution models such as UHD (Ultra High Definition) are in the spotlight. According to this trend, the resolution of the display panel will gradually increase in the future. Accordingly, in the case of a display device using an external scan driver, as the resolution increases, the number of scan drivers will also increase, which will lead to an increase in manufacturing cost, and thus improvement is required.

Hereinafter, the scan driver according to the present invention will be described in comparison with the conventionally proposed scan driver.

3 is a diagram schematically illustrating a conventionally proposed scan driver, and FIG. 4 is a diagram illustrating a display device implemented using a conventionally proposed scan driver.

[Conventional structure]

As shown in FIG. 3 , the conventionally proposed scan driver 130 performs the steps from the scan driver 130a of the first stage to the third stage in response to the gate timing control signal GDC output from the timing controller 120 . It sequentially operates up to the scan driver 130c.

The scan driver 130a of the first stage to the scan driver 130c of the third stage output a scan signal based on the carry signals C1 to C2 output from the scan driver of the previous stage and other clock signals. The scan driver 130a of the first stage to the scan driver 130c of the third stage are formed in the form of an integrated circuit (IC).

The scan driver 130a of the first stage to the scan driver 130c of the third stage formed in the form of an integrated circuit require carry signals C1 to C2 output from the scan driver of the previous stage.

As shown in FIG. 4 , the scan drivers 130a to 130d formed in the form of an integrated circuit are mounted on the first flexible films 131a to 131d attached to the display panel 150 . The data drivers 140a to 140f are mounted on the second flexible films 141a to 141f attached to the display panel 150 . That is, the scan drivers 130a to 130d formed in the form of an integrated circuit are mounted on a film and electrically connected to the display panel 150 like the data drivers 140a to 140f.

In the case of the conventional structure, when the horizontal resolution of the display panel 150 is 1920 and the vertical resolution is 1080, four integrated circuit-type scan drivers 130a to 130d corresponding to the 270 channel (ch) specification are used. should be used However, when the vertical resolution of the display panel 150 is further increased, the number of scan drivers 130a to 130d should be greater than four.

In FIG. 4, undescribed G1, G2 to Gm mean scan signals output from the scan drivers 130a to 130d, DL1, DL2, and DL3 mean first, second and third data lines, etc. SP stands for sub-pixel.

[Structure of the embodiment]

5 is a diagram schematically illustrating a scan driver according to an embodiment of the present invention, and FIG. 6 is a diagram illustrating a display device implemented using the scan driver according to an embodiment of the present invention.

As shown in FIG. 5 , the scan driver 130 according to an embodiment of the present invention includes a first scan circuit unit 133 for outputting a scan signal and a plurality of scan signals output from the first scan circuit unit 133 . A second scan circuit unit 135 that separates (or distributes) the output to the scan line is included.

The first scan circuit unit 133 includes at least one first scan circuit unit, and the second scan circuit unit 135 includes K (K is an integer greater than or equal to 2) more than this number. That is, the first scan circuit unit 133 and the second scan circuit unit 135 are composed of 1:K (K is an integer greater than or equal to 2). If the scan drivers 133 and 135 are disposed on the left and right sides of the display panel, the first scan circuit unit 133 and the second scan circuit unit 135 may be composed of 2 : 2K (K is an integer greater than or equal to 2). will be.

The first scan circuit unit 133 outputs M (M is an integer greater than or equal to 2) scan signals based on the gate timing control signal GDC output from the timing controller 120 . The first scan circuit unit 133 may be formed in the form of an integrated circuit (IC) or a gate in panel (Gate In Panel) form.

Therefore, the first scan circuit unit 133 generates and outputs a scan signal in response to the gate timing control signal GDC output from the timing controller 120 as well as a signal output from the level shifter or the like.

The second scan circuit unit 135 may be formed in a gate-in-panel shape. The first scan circuit unit 133 and the second scan circuit unit 135 have a mixed form of an integrated circuit (IC) form and a gate in panel form or a gate in panel form. can be formed.

The second scan circuit unit 135 separates (or distributes) the scan signal output from the first scan circuit unit 133 to a plurality of scan lines based on the gate output control signal GCS output from the timing control unit 120 . print out

For example, the 1a scan circuit unit 135a performs a plurality of scans on the first to Mth scan signals output from the first scan circuit unit 133 based on the gate output control signal GCS output from the timing control unit 120 . The first to N-th (N is a number equal to or greater than M) are output by separating (or distributing) the lines.

The 1b scan circuit unit 135b applies the first to Mth scan signals output from the first scan circuit unit 133 to a plurality of scan lines based on the gate output control signal GCS output from the timing control unit 120 . Separate (or distribute) and output the first to Nth (N is a number equal to or greater than M). However, the 1b scan circuit unit 135b starts outputting after all outputs of the 1a scan circuit unit 135a are finished by the gate output control signal GCS.

The 1c scan circuit unit 135c applies the first to Mth scan signals output from the first scan circuit unit 133 to a plurality of scan lines based on the gate output control signal GCS output from the timing control unit 120 . Separate (or distribute) and output the first to Nth (N is a number equal to or greater than M). However, the 1c scan circuit unit 135c starts outputting after all outputs of the 1b scan circuit unit 135b are finished by the gate output control signal GCS.

As shown in FIG. 6 , the first scan circuit unit 133 is formed in the form of an integrated circuit and mounted on the first flexible film 131 attached to the display panel 150 . On the other hand, the second scan circuit unit 135 is formed in the form of a gate in panel in the non-display area of the display panel 150 . The data drivers 140a to 140f are mounted on the second flexible films 141a to 141f attached to the display panel 150 . That is, the scan drivers 133 and 135 are divided into a portion formed in the form of an integrated circuit and a portion formed in the form of a gate-in-panel, unlike the data drivers 140a to 140f.

In the case of the same structure as in the embodiment, when the vertical resolution of the display panel 150 is 1080, one integrated circuit type first scan circuit unit 133 corresponding to a 270 channel (ch) specification and four gate-in panels The type second scan circuit unit 135 may be used. In addition, when the vertical resolution of the display panel 150 is further increased, only the number of the second scan circuit units 135 needs to be increased.

Therefore, in the embodiment, even if the vertical resolution of the display panel 150 is increased, only one integrated circuit type first scan circuit unit 133 is used, and only the number of the second scan circuit units 135 is increased for the remaining insufficient parts.

Unlike the external type of integrated circuit (IC) (non-GIP type) type, the method of using the built-in type of the gate in panel (GIP type) is a circuit through a thin film process when designing and manufacturing the display panel 150 . can be configured. Therefore, the mixed use of the external type and the internal type can reduce the burden of increasing the integrated circuit by the increase in the resolution of the display panel 150 .

Hereinafter, descriptions related to the operation of the scan driver according to an embodiment of the present invention will be further detailed.

7 is a view showing a connection relationship for each configuration of a scan driver according to an embodiment of the present invention, FIG. 8 is a waveform diagram showing a scan signal output from a first scan circuit unit, and FIG. 9 is a control view of a second scan circuit unit It is a waveform diagram for explaining timing, FIG. 10 is a waveform diagram showing a scan signal output from the second scan circuit unit, FIG. 11 is a circuit diagram showing a part of the second scan circuit unit, and FIG. It is a diagram showing a display device implemented using a scan driver according to an embodiment.

7 to 10 , the first scan circuit unit 133 outputs first to fourth scan signals (G1 to G4 in FIG. 8 ) in response to the gate timing control signal GDC. It has a fourth output channel (VG1 to GV4).

The second a scan circuit unit 135a is connected to the first to fourth output channels VG1 to GV4 of the first scan circuit unit 133 . The second scan circuit unit 135a is activated by the gate output control signal GCS to separate the scan signals supplied from the first to fourth output channels VG1 to GV4 of the first scan circuit unit 133 for a first time. Output to multiple scan lines while

For example, the second a scan circuit unit 135a is activated when the first gate output control signal CS1 is switched from a logic high (H) to a logic low (L). The activated 2a scan circuit unit 135a Enable separates the scan signals supplied from the first to fourth output channels VG1 to GV4 of the first scan circuit unit 133 to separate the first to fourth scan signals for the first time. (G1 ~ G4) output.

The 2b scan circuit unit 135b is connected to the first to fourth output channels VG1 to GV4 of the first scan circuit unit 133 . The 2b scan circuit unit 135b is activated by the gate output control signal GCS to separate the scan signals supplied from the first to fourth output channels VG1 to GV4 of the first scan circuit unit 133 for a first time. It outputs to a plurality of scan lines for the second time after that.

For example, the second b scan circuit unit 135b is activated when the second gate output control signal CS2 is switched from a logic high (H) to a logic low (L). The activated 2b scan circuit unit 135b Enable separates the scan signals supplied from the first to fourth output channels VG1 to GV4 of the first scan circuit unit 133 to separate the fifth to eighth scan signals for the first time. (G5 ~ G8).

The fifth to eighth scan signals G5 to G8 are formed based on the same waveform as the first to fourth scan signals G1 to G4. Therefore, the fifth to eighth scan signals G5 to G8 are the same as G1 to G4 in the shape of the waveform, but are different from the time axis (G1 to G4 ≠ G1' to G4') (the output time is determined by the 2b scan circuit unit) Because it was output after delay), it can be seen that

The second c scan circuit unit 135c is connected to the first to fourth output channels VG1 to GV4 of the first scan circuit unit 133 . The 2c scan circuit unit 135c is activated by the gate output control signal GCS to separate the scan signals supplied from the first to fourth output channels VG1 to GV4 of the first scan circuit unit 133 for a second time. It outputs to a plurality of scan lines for the third time after that.

For example, the second c scan circuit unit 135c is activated when the third gate output control signal CS3 is switched from a logic high (H) to a logic low (L). The activated 2c scan circuit unit 135c Enable separates the scan signals supplied from the first to fourth output channels VG1 to GV4 of the first scan circuit unit 133 to separate the ninth to twelfth scan signals for a third time period. (G9 ~ G12).

The ninth to twelfth scan signals G9 to G12 are formed based on the same waveform as the first to fourth scan signals G1 to G4. Therefore, the ninth to twelfth scan signals G9 to G12 are the same as G1 to G4 in the form of a waveform, but are different from the time axis (G1 to G4 ≠ G1'' to G4'') It can be seen that 2b is output after the output time delay is more delayed compared to the scan circuit unit).

11 , the second a to second c scan circuit units 135a to 135c include an inverter INV, a first transistor TH, and a second transistor TL, respectively.

The inverter INV activates the first transistor TH of the second to second scan circuit units 135a to 135c in response to the first to third gate output control signals GCS1 to GCS3, and the second transistor ( TL) to inactivate it.

When a logic low gate output control signal is supplied to the inverter INV, the first transistor TH of the second a to second c scan circuit units 135a to 135c is activated and the second transistor TL is deactivated.

When the first transistor TH is activated, the seconda to secondc scan circuit units 135a to 135c may normally output the scan signal supplied to its own channel. On the other hand, when the second transistor TL is activated, the 2a to 2c scan circuit units 135a to 135c use the low potential voltage supplied through the low potential voltage line instead of outputting the scan signal supplied to their own channel. will output

When the first transistor TH is activated, the seconda to secondc scan circuit units 135a to 135c output a scan-on voltage that turns on the transistor of the sub-pixel, so that it can be viewed as being activated. On the other hand, when the second transistor TL is activated, the seconda to secondc scan circuit units 135a to 135c output a scan-off voltage that does not turn on the transistors of the sub-pixels, and thus may be viewed as inactive.

On the other hand, unlike the 2a scan circuit unit 135a, the 2b and 2c scan circuit units 135b and 135c have to delay and output the previously output scan signal in response to the gate output control signal. circuit) should be included.

The delay unit may be implemented as a buffer or latch capable of delaying the scan signal output from the first scan circuit unit for a predetermined time. Methods of configuring the delayer are omitted and shown in various other ways.

As shown in FIG. 12 , in the display device, a free space in a bezel area that is a non-display area of the display panel 150 may exist.

For example, when a small display device or a display device that does not need to reduce the width of the bezel area for a special purpose is implemented, for example, an extra space in the bezel area corresponding to the area in which the scan driver is formed may exist.

In this case, the first scan circuit unit 133 and the second scan circuit unit 135 may be formed in a non-display area on the display panel 150 in the form of a gate in panel.

As described above, the present invention provides an output channel using only 1) an output control circuit unit (second scan circuit unit) capable of controlling the output of one scan circuit unit (first scan circuit unit), and 2) one scan circuit unit (first scan circuit unit) Output control circuit unit composed of multi so that the number of channels can be applied to multiple lines during one frame driving time, 3) On/off of control signal (gate output control signal) Circuit that can be driven separately (Line & Block) through ON/OFF) control, 4) Output control circuit part implemented with a material (preventing scan signal output delay) that ensures high mobility over oxide of transistors (TFTs).

As described above, since the present invention configures the scan driver using a circuit unit composed of at least one integrated circuit and a circuit unit for separating (or distributing) a scan signal output therefrom, it is possible to reduce the number of integrated circuits required for realizing a large screen and high resolution. there is In addition, according to the present invention, since a circuit generating a scan signal and a circuit dividing (or distributing) a plurality of scan signals are separated, the degree of freedom in design is high in response to the resolution of the display device, and manufacturing cost can be reduced. .

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention can be changed to other specific forms by those skilled in the art to which the present invention pertains without changing the technical spirit or essential features of the present invention. It will be appreciated that this may be practiced. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention.

110: image supply unit 120: timing control unit
130: scan driver 140: data driver
150: display panel 133: first scan circuit unit
135: second scan circuit unit GDC: gate timing control signal
GCS: Gate output control signal INV: Inverter
TH: first transistor TL: second transistor

Claims (12)

display panel;
a data driver supplying a data signal to the display panel;
a scan driver supplying a scan signal to the display panel; and
a timing controller for controlling the data driver and the scan driver,
The scan driver includes a first scan circuit unit configured to output a scan signal in response to a first control signal output from the timing control unit, and a first scan circuit unit outputted from the first scan circuit unit in response to a second control signal output from the timing control unit. and a second scan circuit unit that separates and outputs the scan signal to a plurality of scan lines,
The second scan circuit unit
The display device of claim 1, wherein the scan signal output from the first scan circuit unit is delayed and separated and outputted to a plurality of scan lines. delete According to claim 1,
The second scan circuit unit
The display device of claim 1, wherein the scan signal output from the first scan circuit unit is separated and output to a plurality of scan lines. According to claim 1,
The display device of claim 1, wherein the first scan circuit unit and the second scan circuit unit are composed of 1:K (K is an integer greater than or equal to 2). According to claim 1,
The first scan circuit unit is mounted in the form of an integrated circuit on a flexible film connected to the display panel,
and the second scan circuit part is formed in a gate-in-panel shape in a non-display area of the display panel. According to claim 1,
The second scan circuit unit
and a first circuit unit activated in response to a gate output control signal output from the timing controller and a second circuit unit deactivated. 7. The method of claim 6,
The second scan circuit unit
outputting a scan-on voltage for turning on a transistor of a sub-pixel included in the display panel when the first circuit unit is activated;
and outputting a scan-off voltage for turning off a transistor of a sub-pixel included in the display panel when the second circuit unit is activated. a first scan circuit unit for outputting a scan signal in response to a first control signal supplied from an external device;
a second scan circuit unit configured to separate and output the scan signal output from the first scan circuit unit to a plurality of scan lines in response to a second control signal supplied from the external device;
The second scan circuit unit
A scan driver for delaying and separating the scan signal output from the first scan circuit unit and outputting it to a plurality of scan lines. 9. The method of claim 8,
The scan driving unit, characterized in that the first scan circuit unit and the second scan circuit unit is composed of 1:K (K is an integer greater than or equal to 2). 9. The method of claim 8,
The second scan circuit unit
When the first circuit unit is activated, outputting a scan-on voltage that turns on a transistor of a sub-pixel included in the display panel,
The scan driver outputs a scan-off voltage that turns off a transistor of a sub-pixel included in the display panel when the second circuit unit is activated. According to claim 1,
The second scan circuit unit
a first transistor for outputting a scan-on voltage for turning on the transistor of the sub-pixel;
a second transistor for outputting a scan-off voltage that does not turn on the transistor of the sub-pixel;
and an inverter activating one of the first transistor and the second transistor in response to a gate output control signal output from the timing controller. 12. The method of claim 11,
The inverter has an input terminal connected to a line to which the gate output control signal is applied, and an output terminal connected to the gate electrode of the second transistor,
In the first transistor, a gate electrode is connected to a line to which the gate output control signal is applied, a first electrode is connected to a line to which the scan signal is applied, and a second electrode is connected to a line to which the scan signal is output,
In the second transistor, a gate electrode is connected to an output terminal of the inverter, a first electrode is connected to a low potential voltage line to which a low potential voltage is applied, and a second electrode is connected to a line through which the scan signal is output.

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