KR102290820B1 - Gate driver and display device including the same - Google Patents

Abstract

An embodiment of the present invention provides a gate driver capable of easily implementing multi-waveforms and a display device including the same, as well as preventing a delay in rising of a clock signal as the resolution of the display device increases and the area of the display device increases. it's about The gate driver according to an embodiment of the present invention includes a plurality of stages, wherein the stage includes first and second pull-up transistors and first and second pull-down transistors. The first pull-up transistor supplies a clock signal input to the first clock terminal to the second pull-up node according to the voltage of the first pull-up node. The first pull-down transistor supplies the first power voltage input to the first power voltage terminal according to the voltage of the first pull-down node to the second pull-up node. The second pull-up transistor supplies the second power voltage input to the second power voltage terminal to the output terminal according to the voltage of the second pull-up node. The second pull-down transistor supplies the first power voltage to the output terminal according to the voltage of the second pull-down node.

Description

Gate driver and display device including the same

Embodiments of the present invention relate to a gate driver and a display device including the same.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. Accordingly, various flat panel displays (FPDs) capable of reducing weight and volume, which are disadvantages of cathode ray tubes, have recently been developed and marketed. For example, various flat panel displays such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) are being used. .

Such a flat panel display includes data lines, gate lines, a display panel including a plurality of pixels connected to the data lines and gate lines, a gate driver supplying gate signals to the gate lines, and a data line to the data lines. A data driver for supplying voltages is provided. The gate driver may be formed in a non-display area of the display panel, and includes stages having a plurality of transistors and supplies gate signals swinging a gate high voltage and a gate low voltage to gate lines.

1A is an exemplary diagram briefly illustrating a stage of a first type. 1B is an exemplary diagram briefly illustrating a second type of stage. 1A and 1B , the stage is a pull-up transistor that is turned on when the pull-up node NQ, the pull-down node NQB, and the pull-up node NQ are charged to a gate high voltage. TU, the first pull-down transistor TD1 turned on when the pull-down node NQB is charged to the gate high voltage, and the pull-up node TU and the pull-down node TD and a node controller (NC) for controlling charging and discharging. The node controller NC discharges the pull-down node NQB to a gate-low voltage when the pull-up node NQ is charged to the gate-high voltage in order to stably control the output of the stage, and the pull-down node ( When NQB) is charged to the gate high voltage, the pull-up node NQ is discharged to the gate low voltage.

As shown in FIG. 1A , the pull-up transistor TU of the first type stage STT1 converts the clock signal input to the clock terminal CT to the gate signal when the pull-up node NQ is charged to the gate high voltage. print out In the first type stage STT1, as the resolution of the display device increases and the area of the display device increases, the load of the clock signal input to the clock terminal CT increases, so that the rising of the clock signal is delayed. ) has its drawbacks. In this case, a problem in that the rising of the gate signal output to the output terminal of the first type stage STT1 is delayed may occur.

As shown in FIG. 1B , the pull-up transistor TU of the second type stage STT2 applies the gate high voltage input to the gate high voltage terminal VGHT when the pull-up node NQ is charged to the gate high voltage. output as a gate signal. The second type stage STT2 has a disadvantage in that it is difficult to output a multi-waveform gate signal GS having pulses P1 and P2 of a plurality of gate high voltages VGH as shown in FIG. 2 .

Therefore, recently, a new stage capable of improving both the disadvantages of the first type stage STT1 and the disadvantages of the second type stage STT2 is required.

According to the embodiment of the present invention, as the resolution of the display device increases and the area of the display device increases, the gate signal not only prevents the delay of the rising of the gate signal due to the rising delay of the clock signal, but also can easily implement a multi-waveform gate. A driving unit and a display device including the same are provided.

The gate driver according to an embodiment of the present invention includes a plurality of stages, wherein the stage includes first and second pull-up transistors and first and second pull-down transistors. The first pull-up transistor supplies a clock signal input to the first clock terminal to the second pull-up node according to the voltage of the first pull-up node. The first pull-down transistor supplies the first power voltage input to the first power voltage terminal according to the voltage of the first pull-down node to the second pull-up node. The second pull-up transistor supplies the second power voltage input to the second power voltage terminal to the output terminal according to the voltage of the second pull-up node. The second pull-down transistor supplies the first power voltage to the output terminal according to the voltage of the second pull-down node.

A display device according to an embodiment of the present invention outputs gate signals to data lines, gate lines crossing the data lines, pixels connected to the data lines and the gate lines, and the gate lines. A display panel including a gate driver including stages to The first pull-up transistor supplies a clock signal input to the first clock terminal to the second pull-up node according to the voltage of the first pull-up node. The first pull-down transistor supplies the first power voltage input to the first power supply voltage terminal to the second pull-up node according to the voltage of the first pull-down node. The second pull-up transistor supplies the second power voltage input to the second power voltage terminal to the output terminal according to the voltage of the second pull-up node. The second pull-down transistor supplies the first power voltage to the output terminal according to the voltage of the second pull-down node.

An embodiment of the present invention controls the second pull-up node using a clock signal input to the first clock terminal. As a result, according to the embodiment of the present invention, the increase in the load of the clock signal input to the first clock terminal can be minimized even if the resolution of the display device is increased and the area of the display device is increased, and the clock signal is output as the gate signal. Therefore, it is possible to prevent the rising delay of the gate signal.

In addition, since the embodiment of the present invention controls the second pull-up node by the clock signal input to the first clock terminal, the gate signal can be supplied according to the waveform of the clock signal input to the first clock terminal. That is, in the embodiment of the present invention, when the clock signal input to the first clock terminal is implemented as a multi-waveform, a multi-waveform gate signal may be output.

1A is an exemplary view briefly showing a stage of a first type;
1B is an exemplary diagram briefly illustrating a second type of stage;
2 is a waveform diagram showing an example of a multi-waveform;
3 is a block diagram illustrating a display device according to an embodiment of the present invention;
4 is an exemplary view showing the pixel of FIG. 3;
FIG. 5 is another exemplary view showing the pixel of FIG. 3;
6 is a block diagram illustrating the gate driver of FIG. 3 in detail;
7 is a circuit diagram showing an example of a q-th stage in detail;
8 shows clock signals, q-2, q-th and q+2 gate signals, the voltage of the first pull-up node of the q-th stage of FIG. 7, the voltage of the first pull-down node, and the second A waveform diagram showing the voltage at the pull-up node, the voltage at the second pull-down node, and the voltage at the first node.
9A to 9E are circuit diagrams showing the operation of the q-th stage of FIG. 7 during first to fifth periods;

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. The component names used in the following description may be selected in consideration of the ease of writing the specification, and may be different from the component names of the actual product.

3 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention. Referring to FIG. 3 , a display device according to an embodiment of the present invention includes a display panel 10 , a data driver 20 , and a timing controller 30 .

The display device according to an embodiment of the present invention may include any display device that supplies data voltages to pixels through line sequential scanning in which gate signals are sequentially supplied to the gate lines G1 to Gn. For example, a display device according to an embodiment of the present invention includes a liquid crystal display, an organic light emitting display, a field emission display, and an electrophoresis display. display) may be implemented as any one of them.

The display panel 10 includes data lines D1 to Dm, where m is a positive integer greater than or equal to 2), gate lines G1 to Gn, and n is a positive integer greater than or equal to 2), and data lines D1 to Dm; It includes pixels P connected to the gate lines G1 to Gn, and first and second gate drivers 11 and 12 .

The pixel P may be connected to any one of the data lines D1 to Dm and to any one of the gate lines G1 to Gn. Accordingly, the pixel P receives the data voltage of the data line when the gate signal is supplied to the gate line, and emits light with a predetermined brightness according to the supplied data voltage.

When the display device is implemented as a liquid crystal display, each of the pixels P may include a transistor T, a pixel electrode 11, and a storage capacitor Cst as shown in FIG. 4 . Transistor T responds to the gate signal of the kth (k is a positive integer satisfying 1≤k≤n) gate line Gk (j is a positive integer satisfying 1≤j≤m) of the transistor T The data voltage of the data line Dj is supplied to the pixel electrode 11 . For this reason, each of the pixels P drives the liquid crystal of the liquid crystal layer 13 by an electric field generated by a potential difference between the data voltage supplied to the pixel electrode 11 and the common voltage supplied to the common electrode 12 . It is possible to adjust the amount of transmission of light incident from the backlight unit. The common electrode 12 receives a common voltage from the common voltage line VcomL, and the backlight unit is disposed under the display panel 10 to radiate light uniformly to the display panel 10 . In addition, the storage capacitor Cst is provided between the pixel electrode 11 and the common electrode 12 to maintain a constant voltage difference between the pixel electrode 11 and the common electrode 12 .

When the display device is implemented as an organic light emitting diode display, each of the pixels P includes an organic light emitting diode OLED, a scan transistor ST, a driving transistor DT, and a storage capacitor Cst as shown in FIG. 5 . can do. The scan transistor ST supplies the data voltage of the j-th data line Dj to the gate electrode of the driving transistor DT in response to the gate signal of the k-th gate line Gk. The driving transistor DT controls a driving current flowing from the high potential voltage line VDDL to the organic light emitting diode OLED according to the data voltage supplied to the gate electrode. The organic light emitting diode OLED is provided between the driving transistor DT and the low potential voltage line VSSL, and emits light with a predetermined brightness according to the driving current. The storage capacitor Cst may be provided between the gate electrode of the driving transistor DT and the high potential voltage line VDDL to keep the voltage of the gate electrode of the driving transistor DT constant.

The gate driver 11 is connected to the gate lines G1, G2, G3, ..., Gn-1, and Gn to supply gate signals. Specifically, the gate driver 11 receives the gate control signal GCS from the timing controller 30 , and generates gate signals according to the gate control signal GCS to form the gate lines G1, G2, G3, ..., Gn-1, Gn). A detailed description of the gate driver 11 will be described later with reference to FIG. 6 .

The display panel 10 may be divided into a display area DA and a non-display area NDA. The display area DA is an area in which pixels P are provided and an image is displayed. The non-display area NDA is an area provided around the display area DA and is an area in which no image is displayed. The gate driver 11 may be provided in the non-display area NDA using a gate driver in panel (GIP) method. 3 illustrates that the gate driver 11 is provided in the non-display area on one side of the display panel 10 , but it should be noted that the present invention is not limited thereto. That is, a plurality of gate drivers may be provided in the non-display area NDA of the display panel 10 . For example, one gate driver may be provided in one non-display area of the display panel 10 , and the other gate driver may be provided in the other non-display area of the display panel 10 .

The data driver 20 is connected to the data lines D1 to Dm. The data driver 20 receives digital video data DATA and a data control signal DCS from the timing controller 30 , and converts the digital video data DATA into analog data voltages according to the data control signal DCS. do. The data driver 20 supplies analog data voltages to the data lines D1 to Dm. The data driver 20 may include one source drive integrated circuit (hereinafter, referred to as “IC”) or a plurality of source drive ICs.

The timing controller 30 receives digital video data DATA and timing signals TS from an external system board (not shown). The timing signals TS may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock. The timing controller 30 includes a gate control signal GCS for controlling the operation timing of the gate driver 11 and a data control signal for controlling the operation timing of the data driver 20 based on the timing signals TS. DCS) is created. The gate control signal GCS may include a start signal and clock signals CLK1, CLK2, CLK3, CLK4, and the like, as shown in FIG. 8 .

The timing controller 30 supplies the digital video data DATA and the data control signal DCS to the data driver 20 . The timing controller 30 supplies the gate control signal GCS to the gate driver 11 .

6 is a detailed block diagram of the gate driver of FIG. 3 . Referring to FIG. 6 , the gate driver 11 includes a start signal line STL to which a start signal is supplied, and first to fourth clock lines CL1 , CL2 , CL3 and CL4 to which first to fourth clock signals are supplied. ), a first power voltage line VINT1 to which the first power voltage is supplied, and a second power voltage line VINT2 to which the second power voltage is supplied are provided. The start signal and the first to fourth clock signals may be supplied from the timing controller 30 of FIG. 3 , and the first and second power voltages may be supplied from a power supply source (not shown).

The gate driver 11 includes stages STA1 to STAn connected to the gate lines G1, G2, G3, ..., Gn-1, and Gn. The qth (q is a positive integer satisfying 1≤q≤n) stage STAq of the gate driver 11 is connected to the qth gate line Gq and outputs a gate signal. In FIG. 6 , only the first to fourth stages STA1 to STA4 connected to the first to fourth gate lines G1 to G4 are illustrated for convenience of description.

In the following description, "front stage" indicates a stage located in front of a stage serving as a reference. A "rear stage" indicates a stage located behind a stage serving as a reference. For example, the front stages of the third stage STA3 indicate the first and second stages STA1 and STA2 , and the rear stages of the third stage STA3 indicate the fourth to nth stages STA4 to . STAn) is indicated.

Each of the stages STA1 to STAn includes a start terminal ST, a reset terminal RT, first and second clock terminals CT1 and CT2, a first power voltage terminal VINT1, and a second power voltage terminal RT. VINT2), and an output terminal OT.

The start terminal ST of each of the stages STA1 to STAn may be connected to the start signal line STL or the output terminal OT of the second previous stage. The second previous stage of the q-th stage STAq indicates the q-2 th stage STAq-2. That is, the start terminal ST of the q-th stage STAq may be connected to the start signal line STL or the output terminal OT of the q-2 th stage STAq-2. In this case, the start signal of the start signal line STL or the output signal of the q-2 th stage STAq-2 may be input to the start terminal ST of the q-th stage STAq. For example, as shown in FIG. 6 , since the first and second stages STA1 and STA2 do not have a second front stage, the start terminal ST of each of the first and second stages STA1 and STA2 is a start It may be connected to the signal line STL to receive a start signal. In addition, as shown in FIG. 6 , the start terminal ST of each of the third to nth stages STA3 to STAn is connected to the output terminal OT of the second previous stage to receive the output signal of the second previous stage. have.

A reset terminal RT of each of the stages STA1 to STAn may be connected to an output terminal OT of a second subsequent stage. The second rear stage of the q-th stage STAq indicates the q+2 stage STAq+2. That is, the reset terminal RT of the q+2th stage STAq is connected to the output terminal OT of the q+2th stage STAq+2 to receive the output signal of the q+2th stage STAq+2. can

Each of the first and second clock terminals CT1 and CT2 of each of the stages STA1 to STAn is connected to any one of the first to fourth clock lines CL1 to CL4 . It is preferable that the clock signals are i-phase clock signals whose phases are sequentially delayed in order to secure sufficient charging time during high-speed driving (i is a positive integer greater than or equal to 4). In the embodiment of the present invention, as shown in FIG. 8 , the clock signals CLK1 to CLK4 have been mainly described as four-phase clock signals whose phases are sequentially delayed for each horizontal period, but it should be noted that the present invention is not limited thereto. Each of the clock signals has a predetermined period as shown in FIG. 8 and swings between the gate-on voltage Von and the gate-off voltage Voff.

The first and second clock terminals CT1 and CT2 of each of the stages STA1 to STAn are connected to different clock lines. Accordingly, different clock signals are input to the first and second clock terminals CT1 and CT2 of each of the stages STA1 to STAn. For example, as shown in FIG. 6 , the first clock terminal CT1 of the first stage STA1 is connected to the first clock line CL1 , and the second clock terminal CT2 is connected to the second clock line CL2 . may be connected, the first clock terminal CT1 of the second stage STA2 may be connected to the second clock line CL2 , and the second clock terminal CT2 may be connected to the third clock line CL3 . have.

Clock signals are sequentially supplied to each of the first and second clock terminals CT1 and CT2 of the stages STA1 to STAn. For example, as shown in FIG. 6 , the first clock terminal CT1 of the first stage STA1 is connected to the first clock line CL1 to receive the first clock signal, and the first clock terminal CT1 of the second stage STA2 is The clock terminal CT1 is connected to the second clock line CL2 to receive the second clock signal, and the first clock terminal CT1 of the third stage STA3 is connected to the third clock line CL3 to receive the second clock signal. The third clock signal may be input, and the first clock terminal CT1 of the fourth stage STA4 may be connected to the fourth clock line CL4 to receive the fourth clock signal. Also, as shown in FIG. 6 , the second clock terminal CT2 of the first stage STA1 is connected to the second clock line CL2 to receive the second clock signal, and the second clock terminal of the second stage STA2 . CT2 is connected to the third clock line CL3 to receive a third clock signal, and the second clock terminal CT2 of the third stage STA3 is connected to the fourth clock line CL4 to receive a fourth clock signal. A signal may be received, and the second clock terminal CT2 of the fourth stage STA4 may be connected to the first clock line CL1 to receive the first clock signal.

The first power supply voltage terminal VINT1 of each of the stages STA1 to STAn is connected to the first power supply voltage line VINL1 . Accordingly, the first power voltage is supplied to the first power voltage terminal VINT1 of each of the stages STA1 to STAn.

The second power supply voltage terminal VINT2 of each of the stages STA1 to STAn is connected to the second power supply voltage line VINL2 . Accordingly, the second power voltage is supplied to the second power voltage terminal VINT2 of each of the stages STA1 to STAn.

An output terminal OT of each of the stages STA1 to STAn is connected to a gate line to output a gate signal. In addition, the output terminal OT of each of the stages STA1 to STAn is connected to the start terminal ST of the second rear stage and the reset terminal RT of the second previous stage. The second preceding stage of the q-th stage STAq indicates the q-2 th stage STAq-2, and the second rear stage indicates the q+2 th stage STAq+2. That is, the output terminal OT of the q-th stage STAq is connected to the reset terminal RT of the q-2 th stage STAq-2 and the start terminal ST of the q+2 stage STAq+2. do.

7 is a circuit diagram illustrating an example of a q-th stage in detail. In FIG. 7 , for convenience of explanation, the first pull-up node is the first Q node (NQ1), the first pull-down node is the first QB node (NQB1), and the second pull-up node is the second Q The node NQ2 and the second pull-down node have been mainly described as the second QB node NQB2.

Referring to FIG. 7 , the q-th stage STAq includes a first pull-up transistor TU1 , a first pull-down transistor TD1 , a second pull-up transistor TU2 , and a second pull-down transistor TU1 . TD2), a first node control unit 100, a second node control unit 200, and a capacitor (C).

The first pull-up transistor TU1 is turned on by the gate-on voltage of the first Q node NQ1 and supplies a clock signal input to the first clock terminal CT1 to the second Q node NQ2 . When the first pull-up transistor TU1 is turned on by the gate-on voltage of the first Q node NQ1 and a clock signal of the gate-on voltage is input to the first clock terminal CT1, the second Q node Since the gate-on voltage is supplied to NQ2 , the second pull-up transistor TU2 may be turned on. The gate electrode of the first pull-up transistor TU1 is connected to the first Q node NQ1 , the first electrode is connected to the second Q node NQ2 , and the second electrode is connected to the first clock terminal CT1 . can be connected to

The first pull-down transistor TD1 is turned on by the gate-on voltage of the first QB node NQB1 and applies the first power voltage input to the first power voltage terminal VINT1 to the second Q node NQ2. supplied with When the first pull-down transistor TD1 is turned on by the gate-on voltage of the first QB node NQB1 , the gate-off voltage is supplied to the second Q node NQ2 , and thus the second pull-up transistor (TU2) may be turned off. The gate electrode of the first pull-down transistor TD1 is connected to the first QB node NQB1 , the first electrode is connected to the first power voltage terminal VINT1 , and the second electrode is connected to the second Q node NQ2 ) can be connected.

The second pull-up transistor TU2 is turned on by the gate-on voltage of the second Q node NQ2 and supplies the second power voltage input to the second power voltage terminal VIN2 to the output terminal OT. do. When the second pull-up transistor TU2 is turned on by the gate-on voltage of the second Q node NQ2, the gate-on voltage is supplied to the output terminal OT, and thus the gate signal of the gate-on voltage is applied to the gate line. can be output as The gate electrode of the second pull-up transistor TU2 is connected to the second Q node NQ2, the first electrode is connected to the output terminal OT, and the second electrode is connected to the second power supply voltage terminal VINT2. can be connected.

The second pull-down transistor TD2 is turned on by the gate-on voltage of the second QB node NQB2 and supplies the first power voltage input to the first power voltage terminal VINT1 to the output terminal OT. do. When the second pull-down transistor TD2 is turned on by the gate-on voltage of the second QB node NQB2 , the gate-off voltage is supplied to the output terminal OT, and thus the gate signal of the gate-off voltage is applied to the gate line. can be output as The gate electrode of the second pull-down transistor TD2 is connected to the second QB node NQB2 , the first electrode is connected to the first power voltage terminal VINT1 , and the second electrode is connected to the output terminal OT. can be connected.

In the exemplary embodiment of the present invention, the gate-off voltage is a voltage capable of turning off transistors provided in the display panel 10 , and the gate-on voltage is a voltage capable of turning on the transistors. When the transistors are formed of an N-type MOSFET as shown in FIGS. 4, 5, and 7, the gate-on voltage may be set to a gate-high voltage of about 20V or more, and the gate-off voltage may be set to a gate-low voltage of about -3V or less. . Further, in the embodiment of the present invention, the first power voltage input to the first power voltage terminal VINT1 is a gate-off voltage, and the second power voltage input to the second power voltage terminal VINT2 is a gate-on voltage.

The first node controller 100 controls charging and discharging of the second QB node NQB2. When the second Q node NQ2 is charged with the gate-on voltage Von, the first node controller 100 discharges the second QB node NQB2 to the gate-off voltage Voff, and the second Q node NQ2 ) serves to charge the second QB node NQB2 to the gate-on voltage Von when it is discharged to the gate-off voltage Voff. The first node controller 100 may include a second QB node discharging unit 110 and a second QB node charging unit 120 .

The second QB node discharge unit 110 discharges the second QB node NQB2 to a gate-off voltage according to the voltage of the second Q node NQ2 . The second QB node discharge unit 110 may include a first transistor T1 .

The first transistor T1 is turned on by the gate-on voltage of the second Q node NQ2 and supplies the first power voltage input to the first power voltage terminal VINT1 to the second QB node NQB2. . When the first transistor T1 is turned on, the gate-off voltage is applied to the second QB node NQB2 , so that the second pull-down transistor TD2 may be turned off. The gate electrode of the first transistor T1 is connected to the second Q node NQ2 , the first electrode is connected to the first power supply voltage terminal VINT1 , and the second electrode is connected to the second QB node NQB2 . can be

The second QB node charging unit 120 charges the second QB node NQB2 with a gate-off voltage according to the clock signal input to the second clock terminal CT2 and the voltage of the first QB node NQB1 . and a node charging unit 120 . The second QB node charging unit 120 may include second and third transistors T2 and T3 .

The second transistor T2 is turned on by the gate-on voltage of the first QB node NQB1 and supplies the second power voltage input to the second power voltage terminal VINT2 to the second QB node NQB2. . When the second transistor T2 is turned on, the gate-on voltage is supplied to the second QB node NQB2 , so that the second pull-down transistor TD2 may be turned on. The gate electrode of the second transistor T2 is connected to the first QB node NQB1 , the first electrode is connected to the second QB node NQB2 , and the second electrode is connected to the second power supply voltage terminal VINT2 . can be

The third transistor T3 is turned on by the clock signal of the gate-on voltage of the second clock terminal CT2 to supply the gate-on voltage to the second QB node NQB2. When the third transistor T3 is turned on, the gate-on voltage is supplied to the second QB node NQB2 , so that the second pull-down transistor TD2 may be turned on. The gate electrode and the second electrode of the third transistor T3 may be connected to the second clock terminal CT2 , and the first electrode may be connected to the second QB node NQB2 . That is, the third transistor T3 may be diode-connected.

The second node controller 200 controls charging and discharging of the first Q node NQ1 and the first QB node NQB1. The second node control unit 200 may include a first Q node charging/discharging unit 210 and a first QB node charging/discharging unit 220 .

The first Q node charging/discharging unit 210 charges the first Q node NQ1 with a gate-on voltage according to a start signal input to the start terminal ST or an output signal of the q-2 th stage STAq-2, and , the first Q node NQ1 is discharged to a gate-off voltage according to an output signal of the q+2 th stage STAq+2 input to the reset terminal RT. The first Q node charging/discharging unit 210 may include fourth to sixth transistors T4 to T6 .

The fourth transistor T4 is turned on by the gate-on voltage of the start signal input to the start terminal ST or the output signal of the q-2 th stage STAq - 2 to the second power supply voltage terminal VINT2 . The input second power voltage is supplied to the first Q node NQ1. When the fourth transistor T4 is turned on, the gate-on voltage is supplied to the first Q node NQ1 , so that the first pull-up transistor TU1 may be turned on. The gate electrode of the fourth transistor T4 may be connected to the start terminal ST, the first electrode may be connected to the first Q node NQ1 , and the second electrode may be connected to the second power supply voltage terminal VINT2. have.

The fifth transistor T5 is turned on by the gate-on voltage of the output signal of the q+2th stage STAq+2 input to the reset terminal RT, and the fifth transistor T5 is turned on by the first power voltage terminal VINT1. One power voltage is supplied to the first Q node NQ1. When the fifth transistor T5 is turned on, a gate-off voltage is applied to the first Q node NQ1 , so that the first pull-up transistor TU1 may be turned off. The gate electrode of the fifth transistor T5 may be connected to the reset terminal RT, the first electrode may be connected to the first power supply voltage terminal VINT1 , and the second electrode may be connected to the first Q node NQ1 . have.

The sixth transistor T6 is turned on by the gate-on voltage of the first QB node NQB1 and supplies the first power voltage input to the first power voltage terminal VINT1 to the first Q node NQ1 . . When the sixth transistor T6 is turned on, a gate-off voltage is supplied to the first Q node NQ1 , so that the first pull-up transistor TU1 may be turned off. The gate electrode of the sixth transistor T6 is connected to the first QB node NQB1 , the first electrode is connected to the first power voltage terminal VINT1 , and the second electrode is connected to the first Q node NQ1 . can be

The first QB node charging/discharging unit 220 discharges the first QB node NQB1 to a gate-off voltage according to a start signal input to the start terminal ST or an output signal of the q-2 th stage STAq-2, and , when the first Q node NQ1 is discharged to the gate-off voltage, the first QB node NQB1 is charged to the gate-on voltage. The first QB node charging/discharging unit 220 may include seventh to eleventh transistors T4 to T11 .

The seventh transistor T7 is turned on by the gate-on voltage of the first node N1 and supplies the second power voltage input to the second power voltage terminal VINT2 to the first QB node NQB1 . When the seventh transistor T7 is turned on, the gate-on voltage is supplied to the first QB node NQB1 , so that the first pull-down transistor TD1 may be turned on. The gate electrode of the seventh transistor T7 is connected to the first node N1, the first electrode is connected to the first QB node NQB1, and the second electrode is connected to the second power supply voltage terminal VINT2. can

The eighth transistor T8 is turned on by the gate-on voltage of the second power voltage terminal VINT2 to supply the gate-on voltage to the first node N1 . The gate electrode and the second electrode of the eighth transistor T8 may be connected to the second power supply voltage terminal VINT2 , and the first electrode may be connected to the first node N1 . That is, the eighth transistor T8 may be diode-connected.

The ninth transistor T9 is turned on by the gate-on voltage of the first Q node NQ1 and supplies the first power voltage input to the first power voltage terminal VINT1 to the first node N1 . The gate electrode of the ninth transistor T9 is connected to the first Q node NQ1 , the first electrode is connected to the first power supply voltage terminal VINT1 , and the second electrode is connected to the first node N1 . can

When the eighth transistor T8 is turned on and the ninth transistor T9 is turned off, the gate-on voltage is supplied to the first node N1 , and thus the seventh transistor T7 may be turned on. . Even when the eighth transistor T8 is turned on, when the ninth transistor T9 is turned off, the gate-off voltage is supplied to the first node N1, and thus the seventh transistor T7 may be turned off. have.

The tenth transistor T10 is turned on by the gate-on voltage of the first Q node NQ1 and supplies the second power voltage input to the first power voltage terminal VINT1 to the first QB node NQB1 . When the tenth transistor T10 is turned on, a gate-off voltage is applied to the first QB node NQB1 , so that the first pull-down transistor TD1 may be turned off. The gate electrode of the tenth transistor T10 is connected to the first Q node NQ1 , the first electrode is connected to the first power supply voltage terminal VINT1 , and the second electrode is connected to the first QB node NQB1 . can be

The eleventh transistor T11 is turned on by the gate-on voltage of the start signal input to the start terminal ST or the output signal of the q-2 th stage STAq-2 to be turned on to the first power supply voltage terminal VINT1. The input first power voltage is supplied to the first QB node NQB1. When the eleventh transistor T11 is turned on, a gate-off voltage is supplied to the first QB node NQB1 , so that the first pull-down transistor TU1 may be turned off. The gate electrode of the eleventh transistor T11 may be connected to the start terminal ST, the first electrode may be connected to the first power supply voltage terminal VINT1, and the second electrode may be connected to the first QB node NQB1. have.

The capacitor C is connected between the first Q node NQ1 and the second Q node NQ2. The capacitor CB maintains a voltage difference between the first Q node NQ1 and the second Q node NQ2.

The first pull-up transistor TU1 , the first pull-down transistor TD1 , the second pull-up transistor TU2 , the second pull-down transistor TD2 , and the first to eleventh transistors T1 . To T11), the first electrode may be a source electrode, and the second electrode may be a drain electrode, but is not limited thereto. That is, the first pull-up transistor TU1 , the first pull-down transistor TD1 , the second pull-up transistor TU2 , the second pull-down transistor TD2 , and the first to eleventh transistors The first electrode of (T1 to T11) may be a drain electrode, and the second electrode may be a source electrode.

In addition, the first pull-up transistor TU1 , the first pull-down transistor TD1 , the second pull-up transistor TU2 , the second pull-down transistor TD2 , and the first to eleventh transistors Each of the semiconductor layers (T1 to T11) may be formed of oxide, amorphous silicon (a-Si), or poly silicon (Poly-Si).

Meanwhile, although only the q-th stage STAq is illustrated in FIG. 7 for convenience of explanation, each of the stages STA1 to STAn of the gate driver 11 is substantially the same as the q-th stage STAq shown in FIG. 7 . can be formed.

As described above, the q-th stage STAq according to the embodiment of the present invention is turned on by the gate-on voltage of the first pull-up node NQ1 and the clock input to the first clock terminal CLK1 and a first pull-up transistor TU1 for supplying a signal to the second pull-up node NQ2 to control the second pull-up node NQ2. In addition, the q-th stage STAq according to the embodiment of the present invention is turned on by the gate-on voltage of the second pull-up node NQ2 and the second power voltage input to the second power voltage terminal VINT2 is output to the output terminal (OT). That is, in the embodiment of the present invention, the clock signal input to the first clock terminal CLK1 is not output as a gate signal, but serves to control the turn-on of the second pull-up transistor TU2. As a result, according to the embodiment of the present invention, the increase in the load of the clock signal input to the first clock terminal CT1 can be minimized even if the resolution of the display device is increased and the area of the display device is increased, and the clock signal is converted to the gate signal. Since it is not output, a rising delay of the gate signal can be prevented.

In addition, since the q-th stage STAq according to an embodiment of the present invention controls the second pull-up node NQ2 by the clock signal input to the first clock terminal CLK1, the first clock terminal CLK1 The gate signal may be supplied according to the waveform of the clock signal input to the . That is, when the clock signal input to the first clock terminal CLK1 has multiple waveforms as shown in FIG. 2 , the q-th stage STAq according to an embodiment of the present invention may output a multi-waveform gate signal.

As a result, the embodiment of the present invention not only prevents the delay of the rising of the gate signal due to the rising delay of the clock signal as the resolution of the display device increases and the area of the display device increases, but also makes it possible to easily implement multi-waveforms. have. A detailed description of the operation of the q-th stage STAq according to an embodiment of the present invention will be described later with reference to FIGS. 8 and 9A to 9E .

8 shows clock signals, q-2, q-th and q+2 gate signals, the voltage of the first pull-up node of the q-th stage of FIG. 7, the voltage of the first pull-down node, and the second It is a waveform diagram showing the voltage of the pull-up node, the voltage of the second pull-down node, and the voltage of the first node. In FIG. 8 , first to fourth clock signals CLK1 to CLK4 , a q-2 th gate signal GSq - 2 input to the start terminal ST of the q th stage STAq, and a q th stage STAq A qth gate signal GSq output to the output terminal OT of , and a q+2th gate signal GSq+2 inputted to the reset terminal RT of the qth stage STAq are shown. Also, in FIG. 8 , the voltage VQ1 of the first Q node NQ1, the voltage VQB1 of the first QB node NQB1, the voltage VQ2 of the second Q node NQ2, and the second QB node NQB2 ) voltage VQB2 and the voltage VN1 of the first node N1 are shown. A start signal may be input to the start terminal ST of the qth stage STAq instead of the q-2th gate signal GSq-2. 8 illustrates that the clock signals CLK1 to CLK4 are four-phase clock signals whose phases are sequentially delayed, but it should be noted that the present invention is not limited thereto.

The clock signals CLK1 to CLK4 swing between the gate-on voltage Von and the gate-off voltage Voff. Each of the clock signals CLK1 to CLK4 may have a gate-on voltage Von for one horizontal period and a gate-off voltage Voff for three horizontal periods. One horizontal period indicates one horizontal line scanning period in which data voltages are supplied to pixels connected to one gate line of the display panel 10 .

The operation period of the qth stage STAq may be divided into first to sixth periods t1 to t6 as shown in FIG. 8 . In the first to fourth periods t1 to t4 , the first pull-up node NQ1 of the q-th stage STAq is charged to the gate-on voltage Von, so that the first pull-up transistor TU1 is This is the pull-up period, which is the turn-on period. In the fifth and sixth periods t5 and t6 , the first pull-up node NQ1 of the q-th stage STAq is discharged to the gate-off voltage Voff and the first pull-down node NQB1 is gated The pull-down period is a period in which the first pull-down transistor TD1 is turned on by being charged to the on voltage Von. The q-th stage STAq outputs the gate signal of the gate-on voltage Von during the pull-up period and outputs the gate signal of the gate-off voltage Voff during the pull-down period.

Meanwhile, the first pull-up transistor TU1 , the first pull-down transistor TD1 , the second pull-up transistor TU2 , the second pull-down transistor TD2 , and the first to eleventh transistors When (T1 to T11) is implemented as a P-type MOS-FET, the signals of FIG. 8 will have to be modified to match the characteristics of the P-type MOS-FET. Hereinafter, the operation of the q-th stage STAq during the first to sixth periods t1 to t6 will be described in detail with reference to FIGS. 9A to 9E .

9A to 9E are circuit diagrams illustrating the operation of the q-th stage of FIG. 7 during first to fifth periods. Hereinafter, the operation of the q-th stage STAq during the first to sixth periods t1 to t6 will be described in detail with reference to FIGS. 8 and 9A to 9E .

9A to 9E , the q-2th gate signal GSq-2 is input to the start terminal ST of the qth stage STAq, and the q+2th gate signal GSq+2 is input to the reset terminal RT. ) is input, the first power supply voltage supplied to the first power supply voltage terminal VINT1 is the gate-off voltage Voff, and the second power supply voltage supplied to the second power supply voltage terminal VINT2 is the gate-on voltage Von. ) was mainly explained. In addition, although it has been mainly described that the third clock signal CLK3 is input to the first clock terminal CT1 and the fourth clock signal CLK4 is input to the second clock terminal CT2, the present invention is not limited thereto. Care should be taken. That is, when the r-th clock signal (r is a positive integer) is input to the first clock terminal CT1, the r+a (a is greater than i), the phase is delayed from the r-th clock signal, to the second clock terminal CT2. A small positive integer) clock signal may be input.

First, the q-2 th gate signal GSq-2 of the gate-on voltage Von is input to the start terminal ST during the first period t1. Accordingly, the fourth and eleventh transistors T4 and T11 are turned on during the first period t1. Due to the turn-on of the fourth transistor T4 , the first Q node NQ1 is charged to the gate-on voltage Von as shown in FIG. 9A . Due to the turn-on of the eleventh transistor T11, the first QB node NQB1 is discharged to the gate-off voltage Voff as shown in FIG. 9A .

During the first period t1 , the first pull-up transistor TU1 is turned on by the gate-on voltage Von of the first Q node NQ1 . Due to the turn-on of the first pull-up transistor TU1, the second Q node NQ2 has a gate-off voltage Voff of the third clock signal CLK3 input to the first clock terminal CT1 as shown in FIG. 9A . ) is discharged. Accordingly, the second pull-up transistor TU2 and the first transistor T1 are turned off.

Also, during the first period t1 , the ninth and tenth transistors T9 and T10 are turned on by the gate-on voltage Von of the first Q node NQ1 . As the ninth transistor T9 is turned on, the first node N1 is discharged to the gate-off voltage Voff as shown in FIG. 9A , and thus the seventh transistor T7 is turned off. Since the first QB node NQB1 is discharged to the gate-off voltage Voff as shown in FIG. 9A due to the turn-on of the tenth transistor T10, the first pull-down transistor TD1 is turned off.

Furthermore, since the second QB node NQB2 maintains the gate-on voltage Von supplied during the previous sixth period t6 during the first period t1, the second pull-down transistor TD2 is turned on. do. Due to the turn-on of the second pull-down transistor TD2 , the output terminal OT is discharged to the gate-off voltage Voff as shown in FIG. 9A . That is, during the first period t1 , the q-th stage STAq outputs the q-th gate signal GSq of the gate-off voltage Voff to the output terminal OT.

During the first period t1, the first to third and fifth to seventh transistors T1, T2, T3, T5, T6, and T7, the first pull-down transistor TD1, and the second pull-up transistor (TU2) is turned off.

Second, the first Q node NQ1 maintains the gate-on voltage Von by the capacitor C during the second period t2.

During the second period t2 , the first pull-up transistor TU1 is turned on by the gate-on voltage Von of the first Q node NQ1 . Due to the turn-on of the first pull-up transistor TU1, the second Q node NQ2 has a gate-off voltage Voff of the third clock signal CLK3 input to the first clock terminal CT1 as shown in FIG. 9B . ) is discharged. Accordingly, the second pull-up transistor TU2 and the first transistor T1 are turned off.

Also, during the second period t2 , the ninth and tenth transistors T9 and T10 are turned on by the gate-on voltage Von of the first Q node NQ1 . As the ninth transistor T9 is turned on, the first node N1 is discharged to the gate-off voltage Voff as shown in FIG. 9B , and thus the seventh transistor T7 is turned off. Since the first QB node NQB1 is discharged to the gate-off voltage Voff as shown in FIG. 9B due to the turn-on of the tenth transistor T10, the first pull-down transistor TD1 is turned off.

Furthermore, since the second QB node NQB2 maintains the gate-on voltage Von supplied during the previous sixth period t6 during the second period t2, the second pull-down transistor TD2 is turned on. do. Due to the turn-on of the second pull-down transistor TD2 , the output terminal OT is discharged to the gate-off voltage Voff as shown in FIG. 9B . That is, during the second period t2 , the q-th stage STAq outputs the q-th gate signal GSq of the gate-off voltage Voff to the output terminal OT.

During the second period t2 , the first to seventh and eleventh transistors T1 , T2 , T3 , T4 , T5 , T6 , T7 , and T11 , the first pull-down transistor TD1 and the second pull-up transistor TD1 . Transistor TU2 is turned off.

Third, the third clock signal CLK3 of the gate-on voltage Von is input to the first clock terminal CT1 during the third period t3 . In particular, in a state in which the first pull-up transistor TU1 is turned on by the gate-on voltage Von of the first Q node NQ1 during the third period t3, the gate is turned on to the first clock terminal CT1. When the third clock signal CLK3 of the voltage Von is input, the first Q node NQ1 has a higher level than the gate-on voltage Von as shown in FIG. 8 by bootstrapping the capacitor C. Since it is charged with the voltage Von', the first pull-up transistor TU1 may be completely turned on. For this reason, as shown in FIG. 9C , the gate-on voltage Von is supplied to the second Q node NQ2 during the third period t3 . Accordingly, the second pull-up transistor TU2 and the first transistor T1 are turned on during the third period t3 .

Due to the turn-on of the second pull-up transistor TU2 during the third period t3, the output terminal OT is charged to the gate-on voltage Von as shown in FIG. 9C . That is, during the third period t3 , the q-th stage STAq outputs the q-th gate signal GSq of the gate-on voltage Von to the output terminal OT. In addition, since the second QB node NQB2 is discharged to the gate-off voltage Voff as shown in FIG. 9C due to the turn-on of the first transistor T1 during the third period t3, the second pull-down transistor ( TD2) is turned off.

Also, during the third period t2 , the ninth and tenth transistors T9 and T10 are turned on by a level voltage Von′ higher than the gate-on voltage Von of the first Q node NQ1 . . As the ninth transistor T9 is turned on, the first node N1 is discharged to the gate-off voltage Voff as shown in FIG. 9C , and thus the seventh transistor T7 is turned off. Since the first QB node NQB1 is discharged to the gate-off voltage Voff as shown in FIG. 9C due to the turn-on of the tenth transistor T10, the first pull-down transistor TD1 is turned off.

During the third period t3, the second to seventh and eleventh transistors T2, T3, T4, T5, T6, T7, and T11, the first pull-down transistor TD1 and the second pull-down transistor ( TD2) is turned off.

Fourth, the fourth clock signal CLK4 of the gate-on voltage Von is input to the second clock terminal CT2 during the fourth period t4 . Accordingly, the third transistor T3 is turned on during the fourth period t4. Due to the turn-on of the third transistor T3 , the second QB node NQB2 is charged to the gate-on voltage Von as shown in FIG. 9D , and thus the second pull-down transistor TD2 is turned on. Due to the turn-on of the second pull-down transistor TD2 , the output terminal OT is discharged to the gate-off voltage Voff as shown in FIG. 9D . As a result, during the fourth period t4 , the q-th stage STAq may output the q-th gate signal GSq of the gate-off voltage Voff to the output terminal OT.

Since the third clock signal CLK3 of the gate-off voltage Voff is input to the first clock terminal CT1 during the fourth period t4, the first Q node NQ1 is gated-on voltage by the capacitor C It falls to (Von), and the first pull-up transistor TU1 is turned on by the gate-on voltage Von of the first Q node NQ1 . Due to the turn-on of the first pull-up transistor TU1, the second Q node NQ2 has a gate-off voltage Voff of the third clock signal CLK3 input to the first clock terminal CT1 as shown in FIG. 9D . ) is discharged. Accordingly, the second pull-up transistor TU2 and the first transistor T1 are turned off.

Also, during the fourth period t4 , the ninth and tenth transistors T9 and T10 are turned on by the gate-on voltage Von of the first Q node NQ1 . As the ninth transistor T9 is turned on, the first node N1 is discharged to the gate-off voltage Voff as shown in FIG. 9D , and thus the seventh transistor T7 is turned off. Since the first QB node NQB1 is discharged to the gate-off voltage Voff as shown in FIG. 9D due to the turn-on of the tenth transistor T10, the first pull-down transistor TD1 is turned off.

During the fourth period t4 , the first, second, fourth to seventh and eleventh transistors T2 , T3 , T4 , T5 , T6 , T7 , T11 , the first pull-down transistor TD1 and the first 2 The pull-up transistor TU2 is turned off.

Fifth, the q+2th gate signal GSq+2 of the gate-on voltage Von is input to the reset terminal RT during the fifth period t5. Accordingly, the fifth transistor T5 is turned on during the fifth period t5. Due to the turn-on of the fifth transistor T5, the first Q node NQ1 is discharged to the gate-off voltage Voff as shown in FIG. 9E .

During the fifth period t5 , the first pull-up transistor TU1 is turned off by the gate-off voltage Voff of the first Q node NQ1 . Also, during the fifth period t5 , the ninth and tenth transistors T9 and T10 are turned off by the gate-off voltage Voff of the first Q node NQ1 .

As the ninth transistor T9 is turned off, the first node N1 is charged to the gate-on voltage Von as shown in FIG. 9E , and thus the seventh transistor T7 is turned on. Due to the turn-on of the seventh transistor T7 , the first QB node NQB1 is charged to the gate-on voltage Von as shown in FIG. 9E . Therefore, the first pull-down transistor TD1 is turned on. Due to the turn-on of the first pull-down transistor TD1 , the second Q node NQ2 is discharged to the gate-off voltage Voff as shown in FIG. 9E , so that the second pull-up transistor TU2 and the first Transistor T1 is turned off.

Also, the second and sixth transistors T2 and T6 are turned on by the gate-on voltage Von of the first QB node NQB1. Due to the turn-on of the second transistor T2 , the second QB node NQB2 is charged to the gate-on voltage Von as shown in FIG. 9E . Therefore, the second pull-down transistor TD2 is turned on. Due to the turn-on of the second pull-down transistor TD2 , the output terminal NO is discharged to the gate-off voltage Voff as shown in FIG. 9E . That is, during the fourth period t4 , the q-th stage STAq outputs the q-th gate signal GSq of the gate-off voltage Voff to the output terminal OT. Due to the turn-on of the sixth transistor T6 , the first Q node NQ1 is discharged to the gate-off voltage Voff.

During the fifth period t5 , the first, third, fourth, ninth to eleventh transistors T1 , T3 , T4 , T9 , T10 , T11 , the first pull-up transistor TU1 and the second pull-up transistor TU1 . The -up transistor TU2 is turned off.

Sixth, during the sixth period t6 , the first QB node NQB1 maintains the gate-on voltage Von due to the turn-on of the seventh transistor T7 .

During the sixth period t6 , the first pull-down transistor TD1 is turned on by the gate-on voltage Von of the first QB node NQB1 . Due to the turn-on of the first pull-down transistor TD1 , the second Q node NQ2 is discharged to the gate-off voltage Voff, and thus the second pull-up transistor TU2 and the first transistor T1 is turned off.

Also, during the sixth period t6 , the second and sixth transistors T2 and T6 are turned on by the gate-on voltage Von of the first QB node NQB1 . Due to the turn-on of the second transistor T2 , the second QB node NQB2 is charged to the gate-on voltage Von. Therefore, the second pull-down transistor TD2 is turned on. Due to the turn-on of the second pull-down transistor TD2 , the output terminal NO is discharged to the gate-off voltage Voff. That is, during the sixth period t6 , the q-th stage STAq outputs the q-th gate signal GSq of the gate-off voltage Voff to the output terminal OT. Due to the turn-on of the sixth transistor T6 , the first Q node NQ1 is discharged to the gate-off voltage Voff.

Also, whenever the fourth clock signal CLK4 of the gate-on voltage Von is supplied to the second clock terminal CT2 during the sixth period t6, the third transistor T3 is turned on. When the third transistor T3 is turned on, the second QB node NQB2 is charged to the gate-on voltage Von.

During the sixth period t6, the first, third, fourth, fifth, ninth to eleventh transistors T1, T3, T4, T5, T9, T10, T11, and the first pull-up transistor TU1 ) and the second pull-up transistor TU2 are turned off.

As described above, in the embodiment of the present invention, the first pull-up transistor is charged by charging the first pull-up node NQ1 to the gate-on voltage Von during the first to fourth periods t1 to t4. Since TU1 can be turned on, the second pull-up node NQ2 can be controlled by the clock signal input to the first clock terminal CT1 . In addition, in the embodiment of the present invention, the second pull-up node NQ2 is charged to the gate-on voltage Von by the clock signal input to the first clock terminal CT1 during the third period t3. Since the pull-up transistor TU2 may be turned on, the gate-on voltage Von input to the second power supply voltage terminal VIN2 may be output to the output terminal OT. That is, in the embodiment of the present invention, the clock signal of the gate-on voltage input to the first clock terminal CLK1 is not output as a gate signal, but serves to control the turn-on of the second pull-up transistor TU2. do As a result, according to the embodiment of the present invention, the increase in the load of the clock signal input to the first clock terminal CT1 can be minimized even if the resolution of the display device is increased and the area of the display device is increased, and the clock signal is converted to the gate signal. Since it is not output, a rising delay of the gate signal can be prevented.

In addition, since the q-th stage STAq according to an embodiment of the present invention controls the second pull-up node NQ2 by the clock signal input to the first clock terminal CLK1, the first clock terminal CLK1 The gate signal may be supplied according to the waveform of the clock signal input to the . That is, when the clock signal input to the first clock terminal CLK1 has multiple waveforms as shown in FIG. 2 , the q-th stage STAq according to an embodiment of the present invention may output a multi-waveform gate signal.

As a result, the embodiment of the present invention not only prevents the delay of the rising of the gate signal due to the rising delay of the clock signal as the resolution of the display device increases and the area of the display device increases, but also makes it possible to easily implement multi-waveforms. have.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: gate driver
20: data driver 30: timing controller
100: first node control unit 110: second QB node discharge unit
120: second QB node charging unit 200: second node control unit
210: first Q node charging/discharging unit 220: first QB node charging/discharging unit

Claims (10)

having a plurality of stages,
The stage is
a first pull-up transistor for supplying a clock signal input to a first clock terminal to a second pull-up node according to the voltage of the first pull-up node;
a first pull-down transistor configured to supply a first power supply voltage input to a first power supply voltage terminal to the second pull-up node according to the voltage of the first pull-down node;
a second pull-up transistor for supplying a second power voltage input to the second power voltage terminal to the output terminal according to the voltage of the second pull-up node; and
and a second pull-down transistor configured to supply the first power voltage to the output terminal according to a voltage of a second pull-down node. The method of claim 1,
The second pull-down node further comprises a first node control unit for controlling the charging and discharging,
The first node control unit,
a first transistor for supplying the second power supply voltage to the second pull-down node according to the voltage of the first pull-down node; and
and a second transistor configured to supply the first power voltage to the second pull-down node according to the voltage of the second pull-up node. 3. The method of claim 2,
The first node control unit,
a third transistor turned on by the gate-on voltage of the clock signal input to the second clock terminal and supplying the gate-on voltage of the clock signal input to the second clock terminal to the second pull-down node; gate driver. The method of claim 1,
The stage is
and a capacitor connected between the first pull-up node and the second pull-up node. The method of claim 1,
Further comprising a second node control unit for controlling the charging and discharging of the first pull-up node and the first pull-down node,
The second node control unit,
When the first power supply voltage is supplied to the first pull-up node, the second power supply voltage is supplied to the first pull-down node, and the first power supply voltage is supplied to the first pull-down node. a gate driver supplying the second power voltage to the first pull-up node. The method of claim 1,
a gate electrode of the first pull-up transistor is connected to the first pull-up node, a first electrode is connected to the second pull-up node, and a second electrode is connected to the first clock terminal;
A gate electrode of the first pull-down transistor is connected to the first pull-down node, a first electrode is connected to the first power supply voltage terminal, a second electrode is connected to the second pull-up node, and ,
a gate electrode of the second pull-up transistor is connected to the second pull-up node, a first electrode is connected to the output terminal, and a second electrode is connected to the second power supply voltage terminal;
A gate electrode of the second pull-down transistor is connected to the second pull-down node, a first electrode is connected to the first power supply voltage terminal, and a second electrode is connected to the output terminal. 3. The method of claim 2,
a gate electrode of the first transistor is connected to the first pull-down node, a first electrode is connected to the second pull-down node, and a second electrode is connected to the second power supply voltage terminal;
A gate electrode of the second transistor is connected to the second pull-up node, a first electrode is connected to the first power supply voltage terminal, and a second electrode is connected to the second pull-down node. 4. The method of claim 3,
A gate electrode and a second electrode of the third transistor are connected to the second clock terminal, and a first electrode of the third transistor is connected to the second pull-down node. 4. The method of claim 3,
When an r-th clock signal (r is a positive integer) is input to the first clock terminal, an r+a (a is a positive integer) clock signal delayed in phase from the r-th clock signal to the second clock terminal The gate driver to which is input. and a gate driver including data lines, gate lines crossing the data lines, pixels connected to the data lines and the gate lines, and stages outputting gate signals to the gate lines. A display panel is provided,
The stage is
a first pull-up transistor for supplying a clock signal input to a first clock terminal to a second pull-up node according to the voltage of the first pull-up node;
a first pull-down transistor configured to supply a first power supply voltage input to a first power supply voltage terminal to the second pull-up node according to the voltage of the first pull-down node;
a second pull-up transistor for supplying a second power voltage input to the second power voltage terminal to the output terminal according to the voltage of the second pull-up node; and
and a second pull-down transistor configured to supply the first power voltage to the output terminal according to a voltage of a second pull-down node.

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