KR102411044B1 - Gate driver and organic light emitting display device including the same - Google Patents

Abstract

An example of the present application relates to a gate driver in which an area is reduced by reducing the number of stages while generating the same number of scan signals, and an organic light emitting diode display including the same. The gate driver according to an example of the present application includes a plurality of stages for outputting two different scan signals. Each stage receives a plurality of gate clock signals to set the voltage of the internal Q node, and a GIP circuit for outputting a first scan signal set according to the voltage of the Q node, a first of the plurality of clock signals The first transistor receives the first scan signal according to the gate clock signal to set the voltage of the P node, and receives the second gate clock signal from among the plurality of clock signals according to the voltage of the P node to output the second scan signal and a second transistor to

Description

A gate driver and an organic light emitting display including the same

The present application relates to a gate driver and an organic light emitting display device including the same.

In the information society, many technologies in the field of display devices for displaying visual information as images or images are being developed. Among display devices, an organic light emitting diode display displays an image using an organic light emitting diode that generates light by recombination of electrons and holes. The organic light emitting display device has a fast response speed and at the same time is able to express low grayscale according to self-luminescence, so it is in the spotlight as a next-generation display.

An organic light emitting diode display includes a display panel having a display area in which pixels displaying an image are provided and a non-display area disposed outside the display area to not display an image. Each of the pixels is driven by a scan signal and emits light with a brightness corresponding to the size of the data voltage.

An organic light emitting diode display includes data lines, gate lines, a display panel including a plurality of pixels connected to the data lines and gate lines, a gate driver supplying scan signals to the gate lines, and data to the data lines. A data driver for supplying voltages is provided. The gate driver may be formed of a gate driver in panel (hereinafter referred to as “GIP”) circuit in which a gate driver is embedded in a non-display area of the display panel. The gate driver includes a plurality of stages. Each stage supplies scan signals swinging between a gate high voltage and a gate low voltage to gate lines.

In the case of the conventional GIP circuit, one stage is required to generate one scan signal. Each stage consists of a plurality of transistors. Accordingly, in the case of a high-resolution model in which the number of pixel columns is increased, the number of scan signals also increases. Accordingly, the number of stages also increases, thereby increasing the area of the gate driver. When the area of the gate driver increases, it becomes difficult to implement a narrow bezel that reduces the thickness of the non-display area.

An example of the present application is to provide a gate driver in which the area is reduced by reducing the number of stages while generating the same number of scan signals, and an organic light emitting display device including the same.

The gate driver according to an example of the present application includes a plurality of stages for outputting two different scan signals. Each stage receives a plurality of gate clock signals to set the voltage of the internal Q node, and a GIP circuit for outputting a first scan signal set according to the voltage of the Q node, a first of the plurality of clock signals The first transistor receives the first scan signal according to the gate clock signal to set the voltage of the P node, and receives the second gate clock signal from among the plurality of clock signals according to the voltage of the P node to output the second scan signal and a second transistor to

An organic light emitting display device according to an example of the present application includes data lines, gate lines crossing the data lines, pixels connected to the data lines and the gate lines, and a stage for outputting scan signals to the gate lines A display panel including a gate driver including The stage according to the present application includes a GIP circuit for outputting a first scan signal, a first transistor receiving a first scan signal according to a first gate clock signal to set a voltage of a P node, and a second transistor according to the voltage of the P node and a second transistor receiving the gate clock signal and outputting a second scan signal.

An example of the present application may implement a gate driver in which the area is reduced by reducing the number of stages while generating the same number of scan signals, and an organic light emitting display device including the same.

1 is a block diagram illustrating an organic light emitting display device according to the present application.
2 is an internal circuit diagram of a pixel according to an example of the present application.
3 is a waveform diagram showing an active period and a blank period at a frame frequency of 60 Hz.
4 is a waveform diagram showing an active period and a blank period at a frame frequency of 1 Hz.
5 is a detailed circuit diagram illustrating a stage included in the first gate driver according to an example of the present application.
6 is a plan view illustrating an arrangement relationship of GIP circuits in first and second gate drivers of an organic light emitting diode display according to an example of the present application.
7 is a waveform diagram illustrating a previous output signal, first and second gate clock signals, a Q node voltage, a first scan signal, a P node voltage, and a second scan signal of a stage according to an example of the present application.
8 is a block diagram of a stage according to another example of the present application.
9 is a circuit diagram showing in detail a GIP circuit according to another example of the present application.
10 is a waveform diagram showing signals input to a start terminal, a previous stage output signal input terminal, clock signals, voltages of a pull-up node, and gate signals according to another example of the present application.

Advantages and features of the present application, and a method for achieving them will become apparent with reference to examples described below in detail in conjunction with the accompanying drawings. However, the present application is not limited to the examples disclosed below, but will be implemented in various different forms, and only examples of the present application allow the disclosure of the present application to be complete, and common knowledge in the technical field to which this application belongs It is provided to fully inform those who have the scope of the invention, and the present application is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining an example of the present application are exemplary, and thus the present application is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present application, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present application, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, cases including the plural are included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present application.

"First horizontal axis direction", "second horizontal axis direction" and "vertical axis direction" should not be construed only as a geometric relationship in which the relationship between each other is vertical, and the range in which the configuration of the present application can function functionally It may mean to have a broader direction than within.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of “at least one of the first, second, and third items” means that each of the first, second, or third items as well as two of the first, second and third items It may mean a combination of all items that can be presented from more than one.

Each feature of the various examples of the present application may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each example may be implemented independently of each other or may be implemented together in a related relationship. .

1 is a block diagram illustrating an organic light emitting display device according to the present application. 2 is an internal circuit diagram of a pixel P according to an example of the present application.

Referring to FIG. 1 , the organic light emitting display device according to the present application includes a display panel 10 , a data driver 20 , and a timing controller 30 .

The organic light emitting diode display according to the present application supplies data voltages to pixels through line sequential scanning in which scan signals are sequentially supplied to the gate lines G1 to Gn.

The display panel 10 includes data lines D1 to Dm, where m is a positive integer greater than or equal to 2), gate lines G1 to Gn, and n is a positive integer greater than or equal to 2), and data lines D1 to Dm; It includes pixels P connected to the gate lines G1 to Gn, and first and second gate drivers 11 and 12 .

The pixel P may be connected to any one of the data lines D1 to Dm and to any one of the gate lines G1 to Gn. Accordingly, the pixel P receives the data voltage of the data line when the scan signal is supplied to the gate line, and emits light with a predetermined brightness according to the supplied data voltage.

Each of the pixels P may be connected to any one of the gate lines GL1 to GLp, any one of the data lines DL1 to DLq, and any one of the sensing lines SL1 to SLq. As shown in FIG. 2 , the pixel P according to an example of the present application includes a driving transistor DT, a light emitting device EL, a storage capacitor Cst, and first to sixth switching transistors ST1 to ST6. include those In the following description, the driving transistor DT and the first to sixth switching transistors ST1 to ST6 according to an example of the present application include a gate electrode, a source electrode, and a drain electrode. It is assumed that it is implemented with a P-type MOSFET having

The gate electrode of the driving transistor DT is a first node (Node) to which one electrode of the storage capacitor Cst, the drain electrode of the first switching transistor ST1, and the drain electrode of the fifth switching transistor ST5 are connected connected to N1). The source electrode of the driving transistor DT is connected to the drain electrode of the third switching transistor ST3 receiving the pixel driving power ELVDD as the source electrode. The drain electrode of the driving transistor DT is connected to the source electrode of the fourth switching transistor ST4 .

When a voltage greater than the threshold voltage is applied to the gate electrode of the driving transistor DT, it is turned on. The turned-on driving transistor DT flows a driving current from the source electrode to the drain electrode.

The light emitting device EL includes an anode electrode and a cathode electrode. The light emitting device EL flows a driving current from the anode electrode to the cathode electrode. The anode electrode of the light emitting device EL is connected to the second node N2 to which the drain electrode of the fourth switching transistor ST4 is connected. The cathode electrode of the light emitting device EL is connected to a ground line on which the low potential power voltage ELVSS is formed. The light emitting element EL emits light with a brightness corresponding to the driving current flowing from the driving transistor DT.

The storage capacitor Cst has both electrodes. One electrode of the storage capacitor Cst is connected to the first node N1 . The other electrode of the storage capacitor Cst is connected to the pixel driving power supply ELVDD line.

The storage capacitor Cst stores the difference voltage between the pixel driving power ELVDD and the first node N1 when the fifth switching transistor ST5 connected to the first node N1 is turned on. The storage capacitor Cst maintains the differential voltage stored in the first node N1 when the fifth switching transistor ST5 is turned off. In addition, the storage capacitor Cst may control the driving of the driving transistor DT using the stored and maintained voltage.

The gate electrode of the first switching transistor ST1 receives the second scan signal Scan2 . The source electrode of the first switching transistor ST1 is connected to the drain electrode of the driving transistor DT. A drain electrode of the first switching transistor ST1 is connected to the first node N1 . The first switching transistor ST1 is turned on by the second scan signal Scan2 so that the voltage of the first node N1 is the sum of the data voltage Vdata and the threshold voltage Vtp of the driving transistor DT. Increase to Vdata+Vtp.

The gate electrode of the second switching transistor ST2 receives the second scan signal Scan2. The source electrode of the second switching transistor ST2 is connected to the data line DL to receive the data voltage Vdata. The drain electrode of the second switching transistor ST2 is connected to the source electrode of the driving transistor DT. The second switching transistor T2 is turned on by the second scan signal Scan2 to supply the data voltage Vdata to the source electrode of the driving transistor DT.

The gate electrode of the third switching transistor ST3 receives the emission control signal EM. The source electrode of the third switching transistor ST3 receives the pixel driving power ELVDD. The drain electrode of the third switching transistor ST3 is connected to the source electrode of the driving transistor DT. The third switching transistor ST3 is turned on by the emission control signal EM to supply the pixel driving power ELVDD to the driving transistor DT so that the driving transistor DT flows a driving current.

The gate electrode of the fourth switching transistor ST4 receives the emission control signal EM. The source electrode of the fourth switching transistor ST4 is connected to the drain electrode of the driving transistor DT. The drain electrode of the fourth switching transistor ST4 is connected to the second node N2 . The fourth switching transistor ST4 is turned on by the light emission control signal EM, and a driving current flows through the light emitting device EL to emit light.

The gate electrode of the fifth switching transistor ST5 receives the first scan signal Scan1 . The source electrode of the fifth switching transistor ST5 is supplied with the initialization voltage Vinit. A drain electrode of the fifth switching transistor ST5 is connected to the first node N1 . The fifth switching transistor ST5 is turned on by the first scan signal Scan1 to initialize the voltage of the first node N1 to the initialization voltage Vinit.

The gate electrode of the sixth switching transistor ST6 receives the first scan signal Scan1 . The source electrode of the sixth switching transistor ST6 is supplied with the initialization voltage Vinit. A drain electrode of the sixth switching transistor ST6 is connected to the second node N2 . The sixth switching transistor ST6 is turned on by the first scan signal Scan1 to initialize the voltage of the second node N2 to the initialization voltage Vinit.

The pixel P according to the first embodiment of the present invention consists of seven thin film transistors (TFTs) and one capacitor, and is therefore collectively referred to as a 7T1C compensation circuit. Also, the pixel P according to the first embodiment of the present invention operates with two types of scan signals and one type of emission control signal EM.

The first gate driver 11 is connected to the odd gate lines G1, G3, ..., Gn-1 to supply odd scan signals. The second gate driver 12 is connected to the even gate lines G2, G4, ..., Gn to supply even scan signals.

Specifically, the first gate driver 11 receives the first gate control signal GCS1 from the timing controller 30 . The first gate driver 11 generates odd scan signals according to the first gate control signal GCS1 and supplies the generated odd scan signals to the odd gate lines G1, G3, ..., Gn-1. The second gate driver 12 receives the second gate control signal GCS2 from the timing controller 30 . The second gate driver 12 generates even scan signals according to the second gate control signal GCS2 and supplies them to the even gate lines G2, G4, ..., Gn. That is, the first and second gate drivers 11 and 12 may be driven in an interlace manner.

However, the first and second gate drivers 11 and 12 are not limited to being driven in an interlaced manner. The first gate driver 11 may supply scan signals to some gate lines of the display panel 10 , and the second gate driver 12 may supply scan signals to the remaining gate lines of the display panel 10 . .

Alternatively, the first gate driver 11 supplies scan signals to all gate lines of the display panel 10 , and the second gate driver 12 also supplies scan signals to all gate lines of the display panel 10 . can In this case, scan signals of the same waveform are supplied to the same gate line.

An RC load is generated inside the display panel 10 due to resistance and capacitor components of wirings and layers constituting the pixel. Due to the RC load, when the scan signal is supplied from only one side of the display panel 10 , the scan signal is delayed or the waveform of the scan signal is distorted at the opposite side of the side to which the scan signal is supplied. In order to prevent delay or distortion of the scan signal, the first and second gate drivers 11 and 12 are disposed on both left and right sides of the display panel 10, and the same scan signal is applied to the same gate line in the GIP circuits on the left and right sides. supply That is, the delay or distortion of the scan signal is prevented as much as possible by applying a double feeding structure, which is a structure in which signals are supplied from both sides of the same gate line.

The display panel 10 may be divided into a display area DA and a non-display area NDA. The display area DA is an area in which pixels P are provided and an image is displayed. The non-display area NDA is an area provided around the display area DA and is an area in which no image is displayed. The first and second gate drivers 11 and 12 may be provided in the non-display area NDA using a gate driver in panel (GIP) method. In FIG. 1 , the first gate driver 11 is provided in the left non-display area NDA of the display panel 10 , and the second gate driver 12 is provided in the right non-display area NDA of the display panel 10 . has been exemplified in However, the present invention is not limited thereto, and the first and second gate drivers 11 and 12 may be disposed on sides of the non-display area NDA of the display panel 10 in different directions, if necessary, and may be disposed in the non-display area. It may be disposed on the same side if it does not deviate from (NDA) and does not overlap.

The data driver 20 is connected to the data lines D1 to Dm. The data driver 20 receives digital video data DATA and a data control signal DCS from the timing controller 30 , and converts the digital video data DATA into analog data voltages according to the data control signal DCS. do. The data driver 20 supplies analog data voltages to the data lines D1 to Dm. The data driver 20 may include one source drive integrated circuit (hereinafter, referred to as “IC”) or a plurality of source drive ICs.

The timing controller 30 receives digital video data DATA and timing signals TS from an external system board. The timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock. The timing controller 30 includes first and second gate control signals GCS1 and GCS2 for controlling operation timings of the first and second gate drivers 11 and 12 and the data driver 20 based on the timing signal. A data control signal DCS for controlling the operation timing is generated. The first and second gate control signals GCS1 may include start signals, clock signals, and a reset signal.

The timing controller 30 supplies digital video data DATA and a data control signal DCS to the data driver 20 . The timing controller 30 supplies the first gate control signal GCS1 to the first gate driver 11 and the second gate control signal GCS2 to the second gate driver 12 .

Meanwhile, when the video image of the digital video data DATA is a still image, the timing controller 30 may control the display device to be driven at a low frame frequency in order to drive the display device with low power. That is, the timing controller 30 may control the display device to be driven at a low refresh rate (LRR) or a variable refresh rate (VRR).

For example, when the video image of the digital video data DATA is a moving picture, the timing controller 30 may control the display device to be driven at a frame frequency of 60 Hz as shown in FIG. 3 . On the other hand, when the video image of the digital video data DATA is a still image, as shown in FIG. 4 , the display device may be controlled to be driven at a frame frequency of 1 Hz. In the case of a frame frequency of 60Hz, 60 frame periods FR1 to FR60 exist for 1 second (1s) as shown in FIG. 3, and in the case of a frame frequency of 1Hz, one frame period for 1 second (1s) as shown in FIG. 4 (FR1) exists. Each of the frame periods includes an active period AP and a blank period BP. The active period AP is a period in which the first and second gate drivers 11 and 12 output scan signals and the data driver 20 outputs data voltages to supply data voltages to the pixels P. The blank period BP is an idle period inserted between the active periods AP. Accordingly, during the blank period BP, the first and second gate drivers 11 and 12 do not output scan signals, and the data driver 20 does not output data voltages. As shown in FIG. 4 , when the organic light emitting diode display is driven at a frame frequency of 1 Hz, the blank period BP becomes much longer than that of the active period AP, so that power consumption of the organic light emitting display apparatus can be reduced.

In addition, the timing controller 30 may control the display device to stop and start. The stop & start driving divides the display panel 10 into N (N is a positive integer greater than or equal to 2) blocks, and the first and second gate drivers 11 to correspond to the N blocks of the display panel 10 . , 12) After each stage is also divided into N blocks, the first and second gate drivers 11 and 12 corresponding to the block of the display panel 10 on which an image is displayed are included in each block. Stages are controlled to output scan signals, and stages included in each block of the first and second gate drivers 11 and 12 corresponding to a block of the display panel 10 on which an image is not displayed output scan signals. It is a driving method to control not to do so. When the stop & start driving is performed, unnecessary scan signals are not output to an area where an image is not displayed, so power consumption of the display device can be reduced.

5 is a detailed circuit diagram illustrating a stage STA included in the first gate driver 11 according to an example of the present application. 6 is a plan view illustrating an arrangement relationship of the GIP circuits GIP in the first and second gate drivers 11 and 12 of the organic light emitting diode display according to an example of the present application. 7 illustrates a previous output signal Scan_PRE, first and second gate clock signals GCLK1 and GCLK2, a Q node voltage VQ, and a first scan signal Scan1 of the stage STA according to an example of the present application. , the P-node voltage VP, and the second scan signal Scan2 are waveform diagrams.

The first and second gate drivers 11 and 12 according to an example of the present application have a plurality of stages STA. Each of the stages STA includes one GIP circuit GIP and first and second transistors T1 and T2 connected to the GIP circuit GIP. The stage STA includes a previous scan signal Scan_PRE that is a second scan signal Scan2 of the previous stage, first and second gate clock signals GCLK1 and GCLK2, and a gate high voltage VGH that is a DC power supply voltage, and A gate low voltage VGL is supplied. The stage STA outputs the first and second scan signals Scan1 and Scan2. In the following description, it will be assumed that the first and second transistors T1 and T2 are P-type MOS transistors.

In addition, in the following description, a "front stage stage" indicates a stage located in front of any stage serving as a reference. A "rear stage" indicates a stage located behind any stage serving as a reference.

The stage STA included in the first and second gate drivers 11 and 12 according to an example of the present application outputs two different scan signals. In the conventional case, one GIP circuit (GIP) exists in one stage, and only one scan signal can be output. Accordingly, the number of stages STA equal to the number of scan lines on the display panel 10 is required. That is, the number of GIP circuits (GIPs) equal to the number of scan lines was required.

In the case of a high-resolution organic light emitting display device, the number of pixel columns also increases. A scan line must be arranged for each pixel column to supply a scan signal to the pixels. Accordingly, the number of scan lines increases in the high-resolution organic light emitting diode display. When the number of scan lines on the display panel 10 increases, the number of stages STA and the number of GIP circuits GIP also increase. The GIP circuit GIP is disposed in a non-display area of the display panel 10 . Since the GIP circuit GIP consists of a plurality of transistors, when the number of the GIP circuits GIP increases, the area of the non-display area also increases. Accordingly, it is not easy to implement a narrow bezel.

The stage STA according to an example of the present application may supply two different scan signals to two gate lines. Accordingly, the number of stages STAs used in the organic light emitting diode display can be reduced by half compared to the conventional one. Accordingly, according to an example of the present application, the arrangement area of the first and second gate drivers 11 and 12 may be reduced. In this case, the narrow bezel can be more easily implemented.

The stage STA according to an example of the present application includes a GIP circuit GIP and first and second transistors T1 and T2.

The GIP circuit GIP receives the previous scan signal Scan_PRE, the first and second gate clock signals GCLK1 and GCLK2 , and a gate high voltage VGH that is a DC power supply voltage, and a gate low voltage VGL. The first and second gate clock signals GCLK1 and GCLK2 may be supplied from the timing controller 30 , and a power voltage may be supplied from a power supply.

The GIP circuit (GIP) sets the magnitude of the voltage of the internal Q node (Q). The Q node Q is pulled up by rising to the gate high voltage VGH by the first gate clock signal GCLK1 or pulled down to the gate low voltage VGL by the second gate clock signal GCLK2. is a node.

The GIP circuit GIP outputs a first scan signal Scan1 set according to the voltage of the Q node Q. The first scan signal Scan1 changes when the voltage of the Q node Q changes to a predetermined voltage level or more.

The first transistor T1 receives the first scan signal Scan1 according to the first gate clock signal GCLK1 to set the voltage of the P node P.

The second transistor T2 receives the second gate clock signal GCLK2 according to the voltage of the P node P and outputs a second scan signal.

In this case, the stage STA according to an example of the present application transmits the second scan signal Scan2 in the same manner as adding one GIP circuit GIP using the first and second transistors T1 and T2. can create Accordingly, in the gate driver according to an example of the present application, the number of stages STA is reduced by half compared to the conventional one, and the gate area is reduced by using only two transistors by replacing one stage STA. A driving unit can be implemented. Accordingly, the area of the non-display area in which the gate driver is disposed is also reduced, so that a narrow bezel can be easily implemented.

The first transistor T1 of the present application receives the first gate clock signal GCLK1 as a gate electrode. The first gate clock signal GCLK1 may be supplied via the GIP circuit GIP or may be supplied directly from the first gate clock signal line.

The first transistor T1 receives the first scan signal Scan1 as a source electrode. In order to receive the first scan signal Scan1, the source electrode of the first transistor T1 is connected to a node outputting the first scan signal Scan1 in the QIP circuit GIP, or a line branched from the output node is connected with

The drain electrode of the first transistor T1 is connected to the P node P. When the first gate clock signal GCLK1 is applied to the gate electrode of the first transistor T1 , a change in the magnitude of the first scan signal Scan1 supplied to the source electrode is transmitted to the drain electrode. Accordingly, the first transistor T1 may set the voltage of the P node P using the first scan signal Scan1 .

When the first transistor T1 is set in this way, there is no need to generate a separate voltage to drive the first transistor T1. Accordingly, components other than the first transistor T1 can be minimized in terms of circuitry, and thus the area of the stage can be minimized.

The second transistor T2 according to the present application receives the voltage of the drain electrode of the first transistor T1 to the gate electrode. Since the gate electrode of the second transistor T2 and the drain electrode of the first transistor T1 are connected to the P node P, the gate electrode of the second transistor T2 and the drain electrode of the first transistor T1 are have the same voltage.

The second transistor T2 receives the second gate clock signal GCLK2 as a source electrode. In order to receive the second gate clock signal GCLK2 , the source electrode of the second transistor T2 is directly connected to an external line outputting the second gate clock signal GCLK2 .

The second transistor T2 outputs the second scan signal Scan2 to the drain electrode. When the second transistor T2 is turned on according to the voltage of the P node P, the voltage of the second gate clock signal GCLK2 is transferred to the drain electrode of the second transistor T2. Accordingly, the second transistor T2 generates the second scan signal Scan2 according to the second gate clock signal GCLK2 and outputs it to the gate line.

Accordingly, there is no need to additionally generate a separate signal or power other than disposing the second transistor T2 to generate the second scan signal Scan2 . Accordingly, it is not necessary to add components for generating a separate signal on the stage STA. In this case, an increase in the area of the gate driver may be minimized.

The GIP circuit GIP of the present application includes 3-1 and 3-2 transistors T3-1 and T3-2, fourth to ninth transistors T4 to T9, a bridge voltage transistor Tbv, and a Q node capacitor. (CB), and a QB node capacitor (CQB). It is assumed that all of the 3-1 and 3-2 transistors T3-1 and T3-2 and the fourth to ninth transistors T4 to T9 are P-type MOS transistors.

The gate electrodes of the 3-1 and 3-2 transistors T3-1 and T3-2 receive the second gate clock signal GCLK2. The source electrode of the 3-1 th transistor T3 - 1 receives the previous scan signal Scan_PRE. The drain electrode of the 3-1 th transistor T3-1 is connected to the source electrode of the 3-2 th transistor T3-2. The drain electrode of the 3-2 th transistor T3 - 2 is connected to the Q′ node Q′. The Q' node Q' maintains substantially the same voltage state as the Q node Q.

The gate electrode of the fourth transistor T4 receives the first gate clock signal GCLK1 . The source electrode of the fourth transistor T4 is connected to the Q' node Q'. The drain electrode of the fourth transistor T4 is connected to the fifth transistor T5 .

The gate electrode of the fifth transistor T5 is connected to the QB node QB. The QB node QB has a logic level opposite to that of the Q node Q. The source electrode of the fifth transistor T5 is connected to the gate high voltage VGH. The drain electrode of the fifth transistor T5 is connected to the Q' node Q'.

The gate electrode of the sixth transistor T6 receives the second gate clock signal GCLK2 . The source electrode of the sixth transistor T5 is connected to the gate low voltage VGL. The drain electrode of the sixth transistor T6 is connected to the QB node QB.

The gate electrode of the seventh transistor T6 is connected to the Q′ node Q′. The source electrode of the seventh transistor T7 receives the second gate clock signal GCLK2 . The drain electrode of the seventh transistor T67 is connected to the QB node QB.

The gate electrode of the eighth transistor T8 is connected to the Q node Q. The source electrode of the eighth transistor T8 receives the first gate clock signal GCLK1 . The drain electrode of the eighth transistor T8 outputs the first scan signal Scan1 .

The gate electrode of the ninth transistor T9 is connected to the QB node QB. The source electrode of the ninth transistor T9 is connected to the gate high voltage VGH. The drain electrode of the ninth transistor T9 outputs the first scan signal Scan1 .

The gate electrode of the bridge voltage transistor Tbv is supplied with the gate low voltage VGL. Accordingly, the bridge voltage transistor Tbv is always turned on. A source electrode of the bridge voltage transistor Tbv is connected to the Q' node Q', and a drain electrode of the bridge voltage transistor Tbv is connected to the Q node Q. The bridge voltage transistor Tbv maintains the voltages of the Q' node Q' and the Q node Q substantially the same. The bridge voltage transistor Tbv prevents static electricity ESD applied to the Q' node Q' from being transferred to the Q node Q.

The Q node capacitor CB is connected between the Q node Q and the output node of the first scan signal Scan1 . The Q node capacitor CB stores the voltage of the Q node Q.

The QB node capacitor CQB is connected between the QB node QB and the input node of the gate high voltage VGH. The QB node capacitor CQB stores the voltage of the QB node QB.

An arrangement structure of the GIP circuit GIP according to the stage STA of the present application will be described with reference to FIG. 6 . The same scan signal is supplied to the same gate line in the left and right GIP circuits. That is, a double-feeding structure, which is a structure in which signals are supplied from both sides of the same gate line, is applied.

In summary, the stage STA according to the present application is disposed on both sides of an arbitrary gate line, and supplies the same scan signal to the same gate line from both sides. In this case, a scan signal delay or distortion between pixels disposed on both sides of the pixels P in the display panel 10 may be minimized.

At this time, in the organic light emitting display device according to the present application, when the GIP circuits GIP1 to GIP4 are disposed on a stage disposed on one side of an arbitrary gate line, the second transistor is disposed on the stage disposed on the other side of the gate line. (T21 to T23) are arranged.

That is, the first GIP circuit GIP1 is disposed on the uppermost portion of the first gate driver 11 disposed on the left side of the non-display area NDA, and the 21st transistor T21 connected thereto is disposed, and a lower portion thereof is disposed. A third GIP circuit GIP3 is disposed on the , and a twenty-third transistor T23 connected to the third GIP circuit GIP3 is disposed again.

In this case, the second GIP circuit GIP2 is disposed on the other side of the gate line to which the twenty-first transistor T21 is connected in the non-display area NDA. In addition, the second transistor T22 connected to the second GIP circuit GIP2 is disposed on the other side of the gate line to which the third GIP circuit GIP3 is connected. Also, a fourth GIP circuit GIP4 is disposed on the other side of the gate line to which the twenty-third transistor T23 is connected.

In the organic light emitting display device according to the present application, the GIP circuit GIP and the second transistor T2 generally arranged to reduce an area instead of the GIP circuit GIP are alternately arranged on both sides. Accordingly, in the organic light emitting display device according to the present application, the area of the gate driver on both sides is the same, and the GIP circuits GIP are disposed overlappingly, or portions in which the GIP circuits GIP are disposed on both sides occur. A problem in which the area of the display area NDA increases in a specific portion may be prevented.

The operation of the stage STA will be described with reference to FIG. 7 . As described above, all transistors constituting the stage STA are P-type MOS transistors. Accordingly, when the first logic level L1, which is a high logic level, is input to the gate electrode, the transistors are turned off. Also, when the second logic level L2, which is a low logic level, is input to the gate electrode, the transistors are turned on.

The first and second gate clock signals GCLK1 and GCLK2 are alternately input. When the previous scan signal Scan_PRE changes to the second logic level L2 when the second gate clock signal GCLK2 is at the second logic level, the Q node Q by the second gate clock signal GCLK2 voltage VQ changes to the second logic level L2. In this case, the previous scan signal Scan_PRE is applied to the Q node Q while the 3-1 th transistor and the 3-2 th transistor T3-1 and T3-2 are turned on by the second gate clock signal GCLK2. because it has been forwarded to

The 3-1 and 3-2 transistors T3-1 and T3-2 of the present application receive the second gate clock signal GCLK2 and the previous scan signal Scan_PRE, and receive the second gate clock signal GCLK2. The voltage VQ of the Q node Q may be set to be the same as the previous scan signal Scan_PRE. In this case, the output of the current stage may be controlled by setting the voltage VQ of the Q node Q using the output of the previous stage, thereby enabling the sequential output of the scan signal.

The first scan signal Scan1 of the present application is output at the same time the voltage of the Q node Q is changed to the third logic level L3 lower than the second logic level L2. Accordingly, the gate electrode of the eighth transistor T8 of the present application is connected to the Q node Q to more strongly transmit the first gate clock signal GCLK1 to the drain electrode when the third logic level L3 is supplied. It is possible to more reliably output the first scan signal Scan1. As the first and second gate clock signals GCLK1 and GCLK2 alternate, the voltage of the Q node Q is further decreased as described above. As described above, the method of increasing the output to the drain electrode by lowering the gate voltage of the transistor is commonly referred to as bootstrap.

According to the same principle, the second scan signal Scan2 of the present application is output at the same time when the voltage of the P node P is changed to the third logic level L3 lower than the second logic level L2. Accordingly, the gate electrode of the second transistor T2 of the present application is connected to the P node P, and when the third logic level L3 is supplied, the second gate clock signal GCLK2 is more strongly applied to the drain electrode. It is possible to more reliably output the second scan signal Scan2.

The structure of the GIP circuit (GIP) used in the present application is not limited to the GIP circuit (GIP) described in connection with FIGS. 5 to 7 . In the present application, the first and second transistors T1 and T2 may be connected to the GIP circuit GIP implemented in various ways to output the same signal as the arrangement of the two GIP circuits GIP.

8 is a block diagram of a stage STA according to another example of the present application. The first and second gate drivers 11 according to another example of the present application have a plurality of stages STAs. Each of the stages STA includes one GIP circuit GIP and first and second transistors T1 and T2 connected to the GIP circuit GIP. The stage STA receives a start signal, a reset signal, and first to third clock signals. The stage STA outputs the first and second scan signals Scan1 and Scan2. In the following description, it will be assumed that the first and second transistors T1 and T2 are P-type MOS transistors.

In addition, in the following description, a "front stage stage" indicates a stage located in front of any stage serving as a reference. A "rear stage" indicates a stage located behind any stage serving as a reference.

The GIP circuit GIP includes a start signal line STL to which a start signal is supplied, a reset line RL to which a reset signal is supplied, and first to third clock lines CL1 to which first to third gate clock signals are supplied. ~CL3), a power supply voltage line (VSSL) to which a DC power voltage is supplied is connected. The start signal, the reset signal, and the first to third gate clock signals may be supplied from the timing controller 30 , and a power voltage may be supplied from a power supply.

The GIP circuit GIP includes a start terminal ST, a reset terminal RT, a previous carry signal input terminal PT, a rear carry signal input terminal NT, first to third clock terminals CT1 to CT3, and a power supply voltage terminal VSST and an output terminal OT.

The start terminal ST is connected to the start signal line STL or the output terminal OT of the previous stage. The start terminal ST receives the start signal of the start signal line STL or the first scan signal Scan1 output from the previous stage.

The reset terminal RT is connected to the reset signal line RL. The reset terminal RT receives a reset signal.

The previous carry signal input terminal PT may be connected to the previous carry signal line PL. The previous carry signal line is a line extending from the drain electrode of the second transistor T2 of the previous stage. The previous carry signal input terminal PT receives the second scan signal Scan2 output from the previous stage.

The rear carry signal input terminal NT may be connected to the rear carry signal line NL. The rear-end carry signal line is a line extending from the output terminal OT of the rear-stage stage. The rear carry signal input terminal NT receives the first scan signal Scan1 output from the rear stage.

Each of the first to third clock terminals CT1 to CT3 is connected to the first to third clock lines CL1 to CL3 . First to third gate clock signals are supplied to each of the first to third clock lines CL1 to CL3 . Preferably, the first to third gate clock signals are implemented as i (i is a natural number equal to or greater than 4) phase clock signals whose phases are sequentially delayed in order to secure sufficient charging time during high-speed driving. In the present application, it is assumed that the first to third gate clock signals are part of the eight-phase clock signals that overlap by a predetermined period and are sequentially delayed in phase, but it should be noted that the present application is not limited thereto. Each of the first to third gate clock signals has a predetermined period and swings between the gate high voltage VGH and the gate low voltage VGL.

The power supply voltage terminal VSST is connected to the power supply voltage line VSSL. The power voltage terminal VSST is supplied with a power voltage that is a DC voltage.

The output terminal OT is connected to the first gate line. The output terminal OT outputs the first scan signal Scan1 to the first gate line. Also, the output terminal OT is connected to the source electrode of the first transistor T1 .

The gate electrode of the first transistor T1 is connected to the first clock line CL1 . The gate electrode of the first transistor T1 receives the first gate clock signal. The source electrode of the first transistor T1 is connected to the output terminal OT of the GIP circuit GIP. The source electrode of the first transistor T1 receives the first scan signal Scan1. The drain electrode of the first transistor T1 is connected to the P node P connected to the gate electrode of the second transistor T2 . The first transistor T1 sets the voltage of the P node P by using the first scan signal Scan1 according to the first gate clock signal.

The gate electrode of the second transistor T2 is connected to the P node P. The gate electrode of the second transistor T2 receives the voltage of the P node P. The source electrode of the second transistor T2 is connected to the second clock line CL2 . The source electrode of the second transistor T2 receives the second gate clock signal. The drain electrode of the second transistor T2 outputs the second scan signal Scan2. The second transistor T2 outputs the second scan signal Scan2 using the second gate clock signal according to the voltage of the P node P.

9 is a detailed circuit diagram illustrating a GIP circuit (GIP) according to another example of the present application. FIG. 10 is a waveform diagram showing signals input to a start terminal, a previous output signal input terminal, clock signals, voltages of a pull-up node, and gate signals of the GIP circuit GIP of FIG. 9 . The structure and driving of the GIP circuit GIP will be described in more detail with reference to FIGS. 9 and 10 .

In FIG. 9 , for convenience of explanation, it has been mainly described that the pull-up node is a Q node (NQ) and the pull-down node is a QB node (NQB). Referring to FIG. 9 , the GIP circuit GIP includes a pull-up transistor TU, a pull-down transistor TD, a first noise removing unit 100 , a second noise removing unit 200 , and a Q node charging/discharging unit. 300 , a Q node reset unit 400 , an output terminal noise removing unit 500 , and a boosting capacitor CB. In addition, in the following description, it will be assumed that the pull-up transistor TU and the pull-down transistor TD are N-type MOS transistors.

The gate electrode of the pull-up transistor TU is connected to the Q node NQ, the drain electrode is connected to the first clock terminal CT1, and the source electrode is connected to the output terminal OT. The pull-up transistor TU is turned on by the gate-on voltage of the Q node NQ and supplies a clock signal input to the first clock terminal CT1 to the output terminal OT. When the pull-up transistor TU is turned on by the gate-on voltage of the Q node NQ and a clock signal of the gate-on voltage is input to the first clock terminal CT1, the gate signal of the gate-on voltage is output It may be output to the terminal OT.

A gate electrode of the pull-down transistor TD may be connected to the third clock terminal CT3 , a drain electrode may be connected to the power supply voltage terminal VSST, and a source electrode may be connected to the output terminal OT. The pull-down transistor TD is turned on by the gate-on voltage of the QB node NQB and supplies the power voltage input to the power voltage terminal VSST to the output terminal OT. When the pull-down transistor TD is turned on by the gate-on voltage of the QB node NQB, a gate signal of the gate-off voltage may be output to the output terminal OT. Hereinafter, it will be described that the power voltage input to the power voltage terminal VSST is the gate-off voltage. The gate-off voltage is a voltage that can turn off the transistors of the pixels P connected to the gate lines G1 to Gn, and the gate-on voltage is a voltage that can turn on the transistors. The gate-on voltage may be set as the gate high voltage VGH, and the gate-off voltage may be set as the gate low voltage VGL.

The first noise removing unit 100 removes the noise of the Q node NQ according to the clock signal input to the first clock terminal CT1 . The first noise removing unit 100 may include first to fourth switching elements SW1-SW4. In the following description, it is assumed that all of the switching elements provided in the GIP circuit GIP are implemented with N-type MOS transistors.

The gate electrode of the first switching element SW1 may be connected to the first node N1 , the source electrode may be connected to the Q node NQ , and the drain electrode may be connected to the power supply voltage terminal VSST. The first switching element SW1 is turned on by the gate-on voltage of the first node N1 to connect the Q node NQ to the power supply voltage terminal VSST. When the first switching element SW1 is turned on, a gate-off voltage is supplied to the Q node NQ, so that the pull-up transistor TU may be turned off.

A gate electrode and a drain electrode of the second switching element SW2 may be connected to the first clock terminal CT1 , and a source electrode may be connected to the first node N1 . That is, the second switching element SW2 may be diode-connected. The second switching element SW2 is turned on by the gate-on voltage of the clock signal input to the first clock terminal CT1 to supply the gate-on voltage to the first node N1 . When the second switching element SW2 is turned on, the gate-on voltage is supplied to the first node N1 , so that the first switching element SW1 may be turned on.

A gate electrode of the third switching element SW3 may be connected to the Q node NQ, a drain electrode may be connected to the power supply voltage terminal VSST, and a source electrode may be connected to the first node N1 . The third switching element SW3 is turned on by the gate-on voltage of the Q node NQ to connect the first node N1 to the power supply voltage terminal VSST. When the third switching element SW3 is turned on, a gate-off voltage is applied to the first node N1 , thereby turning off the first transistor SW1 .

A gate electrode of the fourth switching element SW4 may be connected to the QB node NQB, a drain electrode may be connected to the power voltage terminal VSST, and a source electrode may be connected to the first node N1 . The fourth switching element SW4 is turned on by the gate-on voltage of the QB node NQB to connect the first node N1 to the power supply voltage terminal VSST. When the fourth switching element SW4 is turned on, a gate-off voltage is applied to the first node N1 , whereby the first switching element SW1 may be turned off.

The second noise removing unit 200 removes the noise of the Q node NQ according to the clock signal input to the second clock terminal CT2 . The second noise removing unit 200 may include a fifth switching element SW5 .

A gate electrode of the fifth switching element SW5 may be connected to the second clock terminal CT2 , a drain electrode may be connected to the previous output signal input terminal PT, and a source electrode may be connected to the Q node NQ. . The fifth switching element SW5 is turned on by the gate-on voltage of the clock signal input to the second clock terminal CT2 to connect the Q node NQ to the previous stage output signal input terminal PT. When the fifth switching element SW5 is turned on, the gate-on voltage or gate-off voltage of the second scan signal Scan2 of the previous stage input from the previous stage output signal input terminal PT to the Q node NQ is can be supplied. When the fifth switching element SW5 is turned on and the gate-off voltage is supplied to the Q node NQ, noise of the Q node NQ may be removed.

The Q node charging/discharging unit 300 charges the Q node NQ to a gate-on voltage according to a start signal input to the start terminal ST, or Q according to the output signal input to the rear output signal input terminal NT. The node NQ is discharged to a gate-off voltage. The Q node charging/discharging unit 300 may include sixth and seventh switching elements SW6 and SW7.

The gate electrode and the drain electrode of the sixth switching element SW6 may be connected to the start terminal ST, and the source electrode may be connected to the Q node NQ. That is, the sixth switching element SW6 may be diode-connected. The sixth switching element SW6 is turned on by the gate-on voltage of the start signal input to the start terminal ST to supply the gate-on voltage to the Q node NQ. When the sixth switching element SW6 is turned on, the gate-on voltage is supplied to the Q node NQ, so that the pull-up transistor TU may be turned on.

A gate electrode of the seventh switching element SW7 may be connected to the rear output signal input terminal NT, a drain electrode may be connected to a power supply voltage terminal VSST, and a source electrode may be connected to the Q node NQ. The seventh switching element SW7 is turned on by the gate-on voltage of the rear-end output signal input to the rear-end output signal input terminal NT to supply the gate-off voltage to the Q node NQ. When the seventh switching element SW7 is turned on, a gate-off voltage is supplied to the Q node NQ, so that the pull-up transistor TU may be turned off.

The Q node reset unit 400 resets the Q node NQ to a gate-off voltage according to a reset signal input to the reset terminal RT. The Q node reset unit 400 may include an eighth switching element SW8.

The gate electrode of the eighth switching element SW8 may be connected to the reset terminal RT, the drain electrode may be connected to the power supply voltage terminal VSST, and the source electrode may be connected to the Q node NQ. The eighth switching element SW8 connects the Q node NQ to the power supply voltage terminal VSST according to the gate-on voltage of the reset signal input to the reset terminal RT. When the eighth switching element SW8 is turned on, the Q node NQ may be reset to a gate-off voltage.

The output terminal noise removing unit 500 removes the noise of the output terminal OT by connecting the output terminal OT to the first clock terminal CT1 according to the voltage of the output terminal OT. The output terminal noise removing unit 500 may include a ninth switching element SW9.

A gate electrode and a source electrode of the ninth switching element SW9 are connected to the output terminal OT, and a drain electrode of the ninth switching element SW9 is connected to the first clock terminal CT1 . That is, the ninth switching element SW9 may be diode-connected. When the voltage of the output terminal OT of the ninth switching element SW9 is higher than the sum of the voltage of the first gate clock signal input to the first clock terminal CT1 and the threshold voltage of the ninth switching element SW9, The output terminal OT is connected to the first clock terminal CT1. Accordingly, the gate-off voltage of the first gate clock signal input to the first clock terminal OT and the threshold voltage of the ninth switching element SW9 due to noise generated at the output terminal OT When it is higher than the sum of , the noise of the output terminal OT may be discharged to the first clock terminal OT.

The boosting capacitor CB is connected between the output terminal OT and the Q node NQ. The boosting capacitor CB maintains a voltage difference between the output terminal OT and the Q node NQ.

When the organic light emitting diode display according to the present application drives the display device at a low refresh rate or a variable refresh rate or stops and starts to reduce power consumption, the blank period BP may be increased. In this case, the semiconductor layers of the pull-up transistor TU, the pull-down transistor TD, and the first to ninth switching elements SW1 to SW9 according to the present application are preferably implemented with oxide. . However, the semiconductor layers of the pull-up transistor TU, the pull-down transistor TD, and the first to ninth switching elements SW1 to SW9 are not limited to oxide, and amorphous silicon (a-Si) ) or polysilicon (Poly-Si).

10 shows the start signal VST input to the start terminal ST of the GIP circuit GIP of FIG. 9 , the first to third gate clock signals CLK1 to CLK3 , the voltage VQ of the Q node, and the second The voltage VN1 of the first node N1 and the first to third scan signals Scan1 to Scan3 are shown. The third scan signal Scan3 is a first scan signal of a later stage.

The start signal VST swings between the gate-on voltage Von and the gate-off voltage Voff. The first to third gate clock signals CLK1 to CLK3 may be implemented as some of the clock signals having four or more phases overlapping by a predetermined period and sequentially delayed in phase.

The first to third gate clock signals CLK1 to CLK3 swing between the gate-on voltage Von and the gate-off voltage Voff. Each of the first to third gate clock signals CLK1 to CLK3 may have a gate-on voltage Von for two unit periods t and a gate-off voltage Voff for two unit periods t. In this case, each of the first to third gate clock signals CLK1 to CLK3 may overlap each other by one unit length t. One unit period t defines one horizontal line scanning period, which is a time during which data voltages are supplied to pixels connected to one gate line of the display panel 10 .

During the pull-up period put, the Q node NQ, which is the pull-up node of the GIP circuit GIP, is charged with the gate-on voltage Von. During the pull-up period put, the Q node NQ outputs the gate-on voltage Von. During the pull-down period pdt, the Q node NQ is discharged to the gate-off voltage Voff. During the pull-down period pdt, the pull-down node QB node NQB is charged with the gate-on voltage Von. During the pull-down period pdt, the GIP circuit GIP outputs the gate-off voltage Voff. The pull-up period put may include first to sixth periods t1 to t6 , and the pull-down period pdt may include seventh to tenth periods t7 to t10 .

In this case, it can be seen that the first scan signal Scan1 and the second scan signal Scan2 are generated without abnormality. In the conventional case, one GIP circuit (GIP) is required to generate one scan signal. Accordingly, in order to generate a plurality of scan signals, the same number of GIP circuits as the number of scan signals is disposed.

However, in the case of the present application, two scan signals may be generated using the GIP circuit GIP and the first and second transistors T1 and T2 connected to the GIP circuit GIP. That is, the present application can replace two GIP circuits (GIP) with one GIP circuit (GIP) and two transistors, thereby reducing the number of GIP circuits (GIP) including a plurality of transistors. Accordingly, the present application can implement a gate driver having a reduced arrangement area by reducing the number of GIP circuits (GIP) even in a high-resolution organic light emitting display device in which the number of scan signals is increased, so that the non-display area in which the gate driver is disposed can be realized. By reducing the area, it is possible to easily implement a narrow bezel.

An example of the present application may implement a gate driver in which the area is reduced by reducing the number of stages while generating the same number of scan signals and an organic light emitting display device including the same.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: first gate driver
12: second gate driver 20: data driver
30: timing control unit P: pixel
DT: driving transistor EL: light emitting element
Cst: storage capacitors ST1 to ST6: first to sixth transistors
100: first noise removing unit 200: second noise removing unit
300: pull-up node charge/discharge unit 400: pull-up node reset unit
500: output node noise removing unit 600: pull-down node charging/discharging unit

Claims (9)

A plurality of stages for outputting two different scan signals,
Each stage is
According to the plurality of gate clock signals, the previous scan signal, which is the scan signal output from the previous stage, is supplied, sets the voltage of the internal Q node, and outputs a first scan signal set according to the voltage of the Q node GIP circuit;
a first transistor configured to receive the first scan signal according to a first gate clock signal among the plurality of gate clock signals to set a voltage of the P node; and
and a second transistor configured to receive a second gate clock signal from among the plurality of gate clock signals according to the voltage of the P node and output a second scan signal. The method of claim 1,
The first transistor is
A gate driver configured to receive the first gate clock signal to a gate electrode and receive the first scan signal to a source electrode to set a voltage of the drain electrode. The method of claim 1,
The second transistor is
A gate driver configured to receive the voltage of the drain electrode of the first transistor to the gate electrode and the second gate clock signal to the source electrode to output a second scan signal to the drain electrode. The method of claim 1,
The GIP circuit is
and 3-1 and 3-2 transistors turned on by the second gate clock signal to receive the previous scan signal to set the voltage of the Q node. The method of claim 1,
The gate driver outputs the first scan signal at the same time when the voltage of the Q node is changed to a third logic level lower than a second logic level that is a low logic level. The method of claim 1,
The second scan signal is output at the same time when the voltage of the P node is changed to a third logic level lower than a second logic level that is a low logic level. a gate driver including data lines, gate lines crossing the data lines, pixels connected to the data lines and the gate lines, and stages for outputting scan signals to the gate lines display panel; and
a data driver supplying data voltages to the data lines;
The stage is
According to the plurality of gate clock signals, the previous scan signal, which is the scan signal output from the previous stage, is supplied, sets the voltage of the internal Q node, and outputs a first scan signal set according to the voltage of the Q node GIP circuit;
a first transistor configured to receive the first scan signal according to a first gate clock signal among the plurality of gate clock signals to set a voltage of the P node; and
and a second transistor receiving a second gate clock signal from among the plurality of gate clock signals according to a voltage of a P node and outputting a second scan signal. 8. The method of claim 7,
The organic light emitting diode display device in which the GIP circuit is disposed on one side of any one of the gate lines, and the second transistor is disposed on the other side of the one of the gate lines. 9. The method of claim 8,
When a GIP circuit is disposed on a stage disposed on one side of the arbitrary gate line, a second transistor is disposed on a stage disposed on the other side of the arbitrary gate line.

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