KR102257233B1 - Pulse amplitude modulation-3 transceiver based on ground referenced signaling and operation method thereof - Google Patents

Abstract

According to an embodiment of the present invention, provided is a pulse amplitude modulation-3 (PAM-3) receiver based on a ground signal transmission method, which can reduce the data recovery speed. The PAM-3 receiver based on a ground signal transmission method comprises: a signal conversion unit converting a transmission signal into a ground voltage-based differential signal; a signal processing unit outputting a digital signal and a reference signal based on the differential signal; a latch unit storing logic data for decoding operation as output data based on an output order between the digital signal and the reference signal; and a decoding unit decoding the logic data into the output data in accordance with a predetermined decoding table.

Description

3-level pulse amplitude transmission and reception device based on ground signal transmission method {PULSE AMPLITUDE MODULATION-3 TRANSCEIVER BASED ON GROUND REFERENCED SIGNALING AND OPERATION METHOD THEREOF}

The present application relates to an apparatus for transmitting and receiving a 3-level pulse amplitude based on a ground signal transmission method and a method of operating the same.

For data communication, a 2-level pulse amplitude modulation (PULSE AMPLITUDE MODULATION-2: PAM-2) signaling method having two data modulation levels is generally used. The existing PAM-2 signaling method has the advantage of simplifying the structure of the transceiver. However, only 1 bit can be transmitted during one unit interval (UI: Unit Interval), and the clock frequency must be increased to increase the bandwidth, resulting in problems such as channel attenuation and clock quality deterioration. Additional circuitry and power consumption are required to improve the clock quality. To compensate for channel attenuation, complex equalizer circuits such as Continuous Time Linear Equalizer (CTLE) and decision feedback equalizer (DFE) are required at the receiving end.

Accordingly, like PAM-2, one bit is sent to one UI, but it has three data modulation levels and uses them to use duo-binary signaling to reduce the effect of channel attenuation. The Duo binary signaling method has the advantage of ensuring clean signal quality even with channel attenuation as there is no low-to-high or high-to-low transition by storing information on the transition of data, not data, at one data modulation level. Compared to the 2 signaling method, the same clock frequency must be used and there is no gain in bandwidth.

In addition, the 3-level pulse amplitude modulation (PULSE AMPLITUDE MODULATION-3: PAM-3) signaling method is a signaling method that transmits three voltage levels at a time and can theoretically transmit 1.5 bits (log 2 3≒1.56). It has structural inefficiency. Accordingly, there is a demand for a transmitting/receiving device having a faster and more accurate data recovery speed and reducing power consumption.

An object of the present application is to provide a three-level pulse amplitude receiving apparatus capable of receiving a transmission signal of 3BIT during 2UI and reducing a data recovery speed, and a method of operating the same.

The PAM-3 receiving apparatus based on the ground signal transmission method according to the embodiment of the present application includes a signal converter that converts a transmission signal into a ground voltage-based differential signal, and outputs a digital signal and a reference signal based on the differential signal. A signal processing unit, based on an output order between the digital signal and the reference signal, decodes the logic data into the output data according to a latch unit for storing logic data for a decoding operation as output data and a preset decoding table. Includes a decoding unit.

In an embodiment, the transmission signal is a signal encoded as a 2UI 3BIT signal according to a preset encoding table.

In an embodiment, the preset encoding table includes an encoding algorithm, input data, charge pump data calculated from the input data according to the encoding algorithm, and a 2UI 3BIT signal corresponding to the charge pump data.

In an embodiment, the differential signal is a pair of analog signals converted from the transmission signal based on the ground voltage.

In an embodiment, the signal processor determines an equalized signal obtained by compensating for channel distortion of the differential signal.

In an embodiment, the voltage difference of the equalized signal corresponds to the output order.

In an embodiment, when the voltage difference between the equalization signal is a high level or a low level, the digital signal is output faster than the reference signal, and when the voltage difference between the equalization signal is a middle level, the digital signal is higher than the reference signal. Output is delayed.

In an embodiment, when the digital signal is output faster than the reference, the latch unit stores the digital signal as the logic data.

In an embodiment, when the digital signal is output to be delayed from the reference signal, the latch unit stores a reset value of the digital signal as the logic data.

In an embodiment, the preset decoding table includes a 2UI 3BIT signal corresponding to the logic data, a decoding algorithm, charge pump data calculated according to the decoding algorithm, and output data corresponding to the charge pump data.

In an embodiment, the charge pump data includes a NULL value corresponding to a signal having the highest symmetry in the EYE diagram of the transmission signal.

In an embodiment, the signal processing unit comprises: a linear equalizer that linearly equalizes the differential signal, a decision feedback equalizer that receives the digital signal and determines an equalized signal, and compares the equalized signal to compare the digital signal. And a second comparator configured to receive a preset reference voltage and output the reference signal in response to the equalization signal.

In an embodiment, the latch unit includes a first transistor having a gate connected to the second comparator and a second transistor having a gate connected to the first comparator, and a gate of the second comparator. And a second latch unit including a connected third transistor and a fourth transistor having a gate connected to the first comparison unit.

In an embodiment, the reception processing unit includes a clock providing unit providing a comparator input clock to the first and second comparators, and a short current path preventing unit changing a logic state of the comparator input clock to a high state.

In an embodiment, it further includes a dummy load unit for adjusting the size of the second reference signal according to the size of the first reference signal.

A method of operating a PAM-3 receiving apparatus according to an embodiment of the present application, comprising: converting a transmission signal into a differential signal based on a ground voltage by a signal converter, and a signal processor converting a digital signal and a reference signal based on the differential signal. Outputting, a latch unit storing logic data for a decoding operation as output data based on an output order of the digital signal and the reference signal, and a decoding unit storing the logic data stored in the latch unit in a preset decoding table And decoding the output data accordingly.

In an embodiment, the outputting comprises: linearly equalizing the differential signal, determining an equalized signal by receiving feedback from the digital signal, and in response to the equalizing signal, outputting the digital signal And receiving a reference voltage and outputting the reference signal.

In an embodiment, the storing comprises: when the digital signal is output faster than the reference signal, storing the digital signal as the logic data, and when the digital signal is output to be delayed than the reference signal, And storing the reset value of the digital signal as the logic data.

In an embodiment, the step of providing a comparator input clock to the first and second comparators by receiving an external clock by a clock providing unit, and by setting the logic state of the comparator input clock to high based on the digital signal It further includes the step of changing to the state.

The PAM-3 transmission/reception system according to the embodiment of the present application includes a transmission device that transmits a transmission signal, and receives the transmission signal and converts it into a ground voltage-based differential signal, and stores logic data according to the output order of the digital signal and the reference signal And a receiving device for decoding the output data, wherein the transmitting device includes an encoder for encoding input data identical to the output data as an up-down signal, and the up-down signal, corresponding to the 2UI 3BIT signal. And a charge pump driver for transmitting a transmission signal to the receiving device.

The three-level pulse amplitude receiving apparatus and its operating method according to the exemplary embodiment of the present application may receive a 3BIT transmission signal during a UI and may reduce a data recovery speed.

1 is a block diagram of a PAM-3 receiving apparatus based on a ground signal transmission method according to an embodiment of the present application.
2 is an example of a preset encoding table.
3 is a diagram for explaining the differential signal of FIG. 1.
4A and 4B are diagrams for explaining an output sequence between a digital signal and a reference signal.
5 is an example of a preset decoding table.
6 is a diagram illustrating the signal processing unit of FIG. 1 in detail.
7 is a diagram showing in detail the latch portion of FIG. 1.
8 is a diagram illustrating another embodiment of the signal processing unit of FIG. 6.
9 is a circuit diagram of the clock providing unit of FIG. 8.
10 is a circuit diagram of a short current path prevention unit of FIG. 9.
FIG. 11 is a diagram specifically illustrating a PAM-3 receiving apparatus based on the ground signal transmission method of FIG. 1.
12 is a conceptual diagram of a transmission/reception system based on a PAM-3 signal according to an embodiment of the present application.
13 is a diagram for describing an operating state of the charge pump driver of FIG. 12.
14 is an operation process of the PAM-3 receiving apparatus of FIG. 1.
15 is an operation process of the signal processing unit of FIG. 6.
16 is an operation process of the latch portion of FIG. 7.
17 is an operation process of the comparator clock providing unit of FIG. 8.

Hereinafter, embodiments of the present application will be described with reference to specific embodiments and the accompanying drawings. However, the embodiments of the present application may be modified into various other forms, and the scope of the present application is not limited to the embodiments described below. In addition, the embodiments of the present application are provided in order to more completely explain the present invention to a person skilled in the art. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

In the drawings, parts not related to the description are omitted in order to clearly describe the present application, and the thickness is enlarged to clearly express several layers and regions, and components having the same function within the scope of the same idea are the same reference. Describe using symbols. Furthermore, throughout the specification, when a part "includes" a certain component, it means that other components may be further included rather than excluding other components unless otherwise stated.

1 is a block diagram of a PAM-3 receiving apparatus 10 based on a ground signal transmission method according to an embodiment of the present application, FIG. 2 is an example of a preset encoding table, and FIG. 3 is a differential signal of FIG. (V _D1 , V _D2 ) is a diagram for explaining, FIGS. 4A and 4B are diagrams for explaining an output order between a digital signal and a reference signal, and FIG. 5 is a preset decoding table. This is an example.

1 to 5, the PAM-3 receiving apparatus 10 may include a signal conversion unit 100, a signal processing unit 200, a latch unit 300, and a decoding unit 400.

First, the signal converter 100 may receive the transmission signal TX and convert it into _{a ground voltage-based differential signal V D1} and V _D2. Here, the transmission signal TX may be a 2UI 3BIT signal encoded according to a preset encoding table from input data through the transmitter.

For example, a 2UI 2BIT signal may mean a signal in which input data is encoded to transmit 2 bits during 2UI, and 2UI 3BIT may mean a signal in which input data is encoded to transmit 3 bits of data during 2UI. In this case, the unit interval (UI) may be a minimum bit pulse width of data in the transmission signal TX.

In addition, the preset encoding table may include an encoding algorithm, input data, charge pump data calculated from the input data according to the encoding algorithm, and a 2UI 3BIT signal corresponding to the charge pump data.

For example, as shown in Figure 2, 2UI 3BIT signal during 2UI, (1, 1), (1, 0), (1, -1), (0, -1), (0, 0) , (0, 1), (-1, 1), (-1, 0), and (0, 0) 3BIT data. In addition, the encoding algorithm may include four algorithms for encoding 3BIT of input data for each bit of 4BIT of charge pump data. In addition, the charge pump data may include a NULL value to which input data is not allocated. At this time, the NULL value may be assigned to the 2UI 3BIT signal of (0,0) corresponding to the highest symmetry on the EYE diagram to facilitate reading of the eye-diagram.

Specifically, the signal conversion unit 100 receives the transmission signal TX and converts the transmission signal TX into a differential signal V _D1 and V _D2 using a reference voltage as a ground voltage, and the signal processing unit 200 Can be transferred to.

As shown in FIG. 3, the differential signals V _D1 and V _{D2 may be a pair of analog signals V D1} and V _D2 converted from the transmission signal TX based on the ground voltage V _G. That is, the signal conversion unit 100 may apply Ground Referenced Signaling to the PAM-3 signaling method to transmit the ground voltage-based differential signals V _D1 and V _D2 to the signal processing unit 200.

Next, the signal processing unit 200 is based on the differential signal (V _D1 , V _D2 ) converted through the signal conversion unit 100, the digital signal (COM _OUTP , COM _OUTN ) and the reference signal (COM _VREP , COM _VREN). ) Can be printed. Since the signal processing unit 200 operates _{by receiving the differential signals V D1} and V _D2 converted from the transmission signal TX based on the _{ground voltage V G} , it is more stable than the differential signals converted to any reference voltage. Can be operated, and power consumption can be reduced.

The signal processing unit 200 according to the embodiment compensates for channel distortion with respect to the differential signals V _D1 and V _{D2 in order to output digital signals COM OUTP} and COM _OUTN and reference signals COM _VREP and COM _VREN. Equalization signals D _INP and D _INN can be determined.

Here, the voltage difference between the equalization signals D _INP and D _INN may correspond to an output order between the _{digital signals COM OUTP} and COM _OUTN and the reference signals COM _VREP and COM _VREN.

As shown in FIG. 4A, when _{the voltage difference between the equalization signals D INP} and D _INN is a high level (H) or a low level (L), the output order is the digital signals COM _OUTP and COM _OUTN as the reference signal ( It may be a first decision time (Fast decision) that is output faster than _{COM VREP} and COM _{VREN ).}

As shown in FIG. 4B, when _{the voltage difference between the equalization signals D INP} and D _INN is the middle level M, the output order is the digital signals COM _OUTP and COM _OUTN as the reference signals COM _VREP and COM _VREN It may be a second decision time (Slow decision) that is output to be more delayed.

Next, the latch unit 300 stores logic data for decoding into output data based on the output order between the _{digital signals COM OUTP} and COM _OUTN and the reference signals COM _VREP and COM _VREN I can. Here, the logic data may be a 2UI 3BIT signal, and the output data RX may be a signal restored from the transmission signal TX.

Specifically, when the digital signals COM _OUTP and COM _OUTN are output faster than the reference signals COM _VREP and COM _VREN , the latch unit 300 may _{store the digital signals COM OUTP} and COM _OUTN as logic data. .

In addition, when the digital signals (COM _OUTP , COM _OUTN ) are output to be delayed than the reference signals (COM _VREP , COM _VREN ), the latch unit 300 sets the reset values for the _{digital signals (COM OUTP} , COM _{OUTN) to logic data.} Can be saved as. Here, the reset value for the digital signals COM _OUTP and COM _OUTN may be a value of (0,0).

Next, the decoding unit 400 may decode the logic data stored in the latch unit 300 according to a preset decoding table. Specifically, during 2UI, the decoding unit 400 may decode the logic data stored in the latch unit 300 in units of 3BIT according to a preset decoding table.

Here, the preset decoding table may include a 2UI 3BIT signal corresponding to logic data, a decoding algorithm, charge pump data calculated according to the decoding algorithm, and output data corresponding to the charge pump data.

For example, as shown in Figure 5, 2UI 3BIT signal during 2UI, (1, 1), (1, 0), (1, -1), (0, -1), (0, 0) , (0, 1), (-1, 1), (-1, 0), and (0, 0) 3BIT data. In addition, the decoding algorithm may include three algorithms for decoding 4BIT of charge pump data for each bit of 3BIT of output data. In addition, the charge pump data may include a NULL value to which output data is not allocated. In this case, the NULL value may be assigned to the 2UI 3BIT signal of (0,0) corresponding to the highest symmetry on the EYE diagram so as to facilitate reading of the eye-diagram.

The PAM-3 receiving device 10 according to the embodiment of the present application includes logic data for decoding into output data based on the output order of _{digital signals COM OUTP} and COM _OUTN and reference signals COM _VREP and COM _VREN Since it can store, it is possible to reduce the time for restoring the output data compared to a conventional receiving device that compares all level levels between a digital signal and a reference signal.

Hereinafter, the signal processing unit 200 and the latch unit 300 will be described in more detail with reference to FIGS. 6 to 10.

6 is a diagram illustrating the signal processing unit 200 of FIG. 1 in detail.

1 and 6, the signal processing unit 200 may include a linear equalization unit 210, a decision feedback equalization unit 220, a first comparison unit 230 and a second comparison unit 240. .

First, the linear equalizer 210 may linearly equalize the differential signals V _D1 and V _D2 according to a preset equalization coefficient.

Next, the decision feedback equalization unit 220 is _{a digital signal COM OUTP} output through the first and second comparators 230 and 240 in order to compensate for channel distortion for the _{differential signals V D1} and V _D2. , COM _OUTN ) and reference signals (COM _VREP , COM _VREN ) can be fed back.

At this time, the decision feedback equalizer 220 may determine equalization signals D _INP and D _{INN based on the digital signals COM OUTP} and COM _OUTN and the reference signals COM _VREP and COM _VREN . Here, the equalization signals D _INP and D _INN may be analog signals.

Next, the first comparison unit 230 may output digital signals COM _OUTP and COM _{OUTN by comparing the equalization signals D INP} and D _{INN determined through the decision feedback equalization unit 220.} Here, the first comparison unit 230 may be an analog-to-digital converter that converts _{equalization signals D INP} and D _INN into digital signals COM _OUTP and COM _OUTN.

Next, the second comparison unit 240 receives preset reference voltages V _REFP and V _{REFN according to the equalization signals D INP} and D _INN determined through the decision feedback equalization unit 220 and receives the reference signal ( COM _VREP , COM _VREN ) can be output.

7 is a diagram specifically showing the latch unit 300 of FIG. 1.

1 and 7, the latch unit 300 may include first and second latch units 310 and 320.

First, the first latch unit 310 may include a first transistor 311 having a gate connected to the second comparison unit 240 and a second transistor 312 having a gate connected to the first comparison unit 230. .

_{Specifically, the first transistor 311 is applied} to the first reference signal COM _{VREP among the reference signals COM VREP} and COM VREN output from the second comparison unit 240 to the gate through the second input node N2. Based on this, it is possible to switch connection between the first input node N1 and the ground.

In addition, the second transistor 312 is based on the first digital signal (COM _OUTP) of the first comparison unit first digital via the input node (N1) receiving the output a gate signal (COM _OUTP, COM _OUTN) from 230 Thus, it is possible to switch and connect the second input node N2 and the ground.

Next, the second latch unit 320 may include a third transistor 321 having a gate connected to the second comparison unit 240 and a fourth transistor 322 having a gate connected to the first comparison unit 230. have.

_{Specifically, the third transistor 321 is applied} to the first reference signal COM _{VREP among the reference signals COM VREP} and COM VREN output from the second comparison unit 240 to the gate through the fourth input node N4. Based on this, the third input node N3 and the ground may be switched and connected.

In addition, the fourth transistor 322 is based on the second digital signal COM _{OUTN among digital signals COM OUTP} and COM _{OUTN that} are output from the first comparator 230 to the gate through the third input node N3. Thus, the connection between the fourth input node N4 and the ground may be switched.

FIG. 8 is a diagram showing another embodiment of the signal processing unit 200 of FIG. 6, FIG. 9 is a circuit diagram of the clock providing unit 250 of FIG. 8, and FIG. 10 is a short current path prevention unit ( 260).

8 to 10, the signal processing unit 200 includes a linear equalization unit 210, a decision feedback equalization unit 220, a first comparison unit 230, a second comparison unit 240, and a clock providing unit ( 250) and a short current path prevention unit 260 may be included. Hereinafter, a redundant description of the linear equalization unit 210, the decision feedback equalization unit 220, the first comparison unit 230 and the second comparison unit 240 of the same reference number described in FIG. 6 will be omitted. .

First, the clock providing unit 250 may receive an external clock from the outside and may receive an enable signal. Here, the enable signal may be a signal provided when the digital signal output through the first comparator 230 has a preset value in order to reduce power consumption of the first comparator 230.

Specifically, as shown in FIG. 9, the clock providing unit 250 frequency adjusters 251_1, 251_2, 251_3 for frequency adjustment _{of the input clock CK IN} to the output clock CK _{OUT according to the enable signal.} The comparator input clock can be provided via. Here, the comparator input clock may be an edge signal for sampling the PAM-3 signal.

In addition, the clock providing unit 250 may receive a first reference signal COM _{VREN among reference signals COM VREP} and COM _{VREN through one of a pair of transistors.}

Here, the gate of one transistor may be connected to the second comparator 240, and the gate of the other transistor may be connected to the output terminals of the frequency adjusters 251_1, 251_2, and 251_3. In this case, the clock providing unit 250 may receive an enable signal through a node in which a pair of transistors are connected to each other.

Next, the short current path prevention unit 260 sets the comparator input clock provided to the first comparator 230 through the clock providing unit 250 to a high state based on the _{digital signals COM OUTP} and COM _OUTN. You can change it.

For example, when the digital signals COM _OUTP and COM _OUTN output through the first comparison unit 230 have a value of (0,0), the short current path prevention unit 260 A comparator input clock provided to the first comparator 230 through the clock providing unit 250 may be changed to a HIGH state so that a current path) is not formed. As illustrated in FIG. 10, the short current path prevention unit 260 may include a plurality of transistors.

11 is a diagram showing in detail the PAM-3 receiving apparatus 11 based on the ground signal transmission method of FIG. 1.

1 to 11, the PAM-3 receiving apparatus 11 includes a signal conversion unit 100, a signal processing unit 200, a latch unit 300, a decoding unit 400, and a dummy load unit 500. Can include. Hereinafter, redundant descriptions of the signal conversion unit 100, the signal processing unit 200, the latch unit 300, and the decoding unit 400 having the same reference numerals described in FIGS. 1 to 10 will be omitted.

11, the latch unit 300 includes a pair of Cross Couple Latch corresponding to the first and second latch units 310 and 320, and the decoding unit 400 is a 3bit/2UI PAM-3 It can be a Decoder.

The dummy load unit 500 according to the embodiment _{adjusts the size of the second reference signal COM VREN} equally according to the size of the first reference signal COM VREN, thereby performing a comparison operation of the second comparison unit 240 Can be performed ideally.

12 is a conceptual diagram of a PAM-3 transmission/reception system 1000 according to an exemplary embodiment of the present application, and FIG. 13 is a diagram illustrating an operation state of the charge pump driver 23 of FIG. 12.

1 to 12, the PAM-3 transmission/reception system 1000 may include a reception device 10 and a transmission device 20. Hereinafter, a redundant description of the receiving device 10 having the same reference number described in FIGS. 1 to 11 will be omitted.

First, the transmission device 20 may include an encoder 21 and a charge pump driver 23.

As shown in FIG. 12, the encoder 21 may be a 3bit 2UI half-rate encoder that encodes input data into an up-down signal. Here, the input data may be 3BIT, and the up-down signal may be 2BIT.

Next, the charge pump driver 23 may transmit a transmission signal TX corresponding to the 2UI 3BIT signal based on the up-down signal encoded through the encoder 21.

As shown in FIG. 13, the charge pump driver 23 may operate in any one of a precharge state, a drive middle state, a drive high state, and a drive low state according to an up-down signal using a capacitor. have.

The reception device 10 according to the embodiment of the present application may convert the transmission signal TX transmitted through the transmission device 20 into voltage-based differential signals V _D1 and V _D2. In this case, the reception device 10 may decode the stored logic data into output data according to the output order of the _{digital signals COM OUTP} and COM _OUTN and the reference signals COM _VREP and COM _VREN.

14 is an operation process of the PAM-3 receiving apparatus 10 of FIG. 1.

Referring to FIGS. 1 and 14, in step S110, the signal conversion unit 100 may convert a transmission signal TX into a ground voltage-based differential signal V _D1 and V _D2 .

Then, in step S120, the signal processing unit 200 may output digital signals COM _OUTP and COM _OUTN and reference signals COM _VREP and COM _{VREN based on the differential signals V D1} and V _D2 . .

Then, in step S130, the latch unit 300 may store logic data for a decoding operation based on an output order between the _{digital signals COM OUTP} and COM _OUTN and the reference signals COM _VREP and COM _VREN. .

Thereafter, in step S140, the decoding unit 400 may decode the logic data stored in the latch unit 300 into output data according to a preset decoding table.

15 is an operation process of the signal processing unit 200 of FIG. 6.

6 and 15, in step S121, the signal processing unit 200 may linearly equalize _{the difference signals V D1} and V _{D2 according to a preset equalization coefficient.}

Then, in step S123, the signal processing unit 200 may determine equalization signals D _INP and D _{INN by receiving feedback of the digital signals COM OUTP} and COM _OUTN .

Then, in step S125, the signal processing unit 200 _{outputs digital signals COM OUTP} and COM _OUTN in response to the _{equalization signals D INP} and D _INN and receives a preset reference voltage to receive the reference signal COM _VREP. , COM _VREN ) can be output.

Here, the digital signals COM _OUTP and COM _OUTN include a first digital signal COM _OUTP and a second digital signal COM _OUTN , and the reference signals COM _VREP and COM _VREN are the first reference signals COM _VREP ) And a second reference signal COM _VREN .

16 is an operation process of the latch unit 300 of FIG. 7.

7 and 16, in step S131, when the digital signals COM _OUTP and COM _OUTN are output faster than the reference signals COM _VREP and COM _VREN , the latch unit 300 is a digital signal COM _OUTP , COM _OUTN ) can be saved as logic data.

On the other hand, in step S133, when the digital signals (COM _OUTP , COM _OUTN ) are output to be delayed than the reference signals (COM _VREP , COM _VREN ), the latch unit 300 resets the _{digital signals (COM OUTP} , COM _OUTN). Values can be stored as logic data.

17 is an operation process of the clock providing unit 250 and the short current path prevention unit 260 of FIG. 8.

8 and 17, in step S210, the clock providing unit 250 may receive an external clock and provide a comparator input clock to the first and second comparators 230 and 240.

Thereafter, in step S220, the short current path prevention unit 260 may change the logic state of the comparator input clock to a high state based on the _{digital signals COM OUTP} and COM _OUTN.

Although the present application has been described with reference to the exemplary embodiment illustrated in the drawings, this is only exemplary, and those of ordinary skill in the art will understand that various modifications and equivalent other exemplary embodiments are possible therefrom. Therefore, the true technical protection scope of the present application should be determined by the technical idea of the attached registration claims.

10: receiving device
20: transmitting device
100: signal conversion unit
200: signal processing unit
300: latch part
400: decoding unit
1000: sending/receiving system

Claims (20)

A signal converter for converting a transmission signal into a ground voltage-based differential signal;
A signal processing unit that outputs a digital signal and a reference signal based on the differential signal;
A latch unit for storing logic data for decoding into output data based on an output order between the digital signal and the reference signal; And
In accordance with a preset decoding table, comprising a decoding unit for decoding the logic data to the output data,
The transmission signal is a signal encoded as a 2UI 3BIT signal according to a preset encoding table. delete The method of claim 1,
The preset encoding table includes an encoding algorithm, input data, charge pump data calculated from the input data according to the encoding algorithm, and a 2UI 3BIT signal corresponding to the charge pump data. Receiving device. The method of claim 1,
The differential signal is a pair of analog signals converted from the transmission signal based on the ground voltage. The method of claim 1,
The signal processing unit determines an equalized signal obtained by compensating for channel distortion of the differential signal. The method of claim 5,
The PAM-3 receiving apparatus, wherein the voltage difference of the equalized signal corresponds to the output order. The method of claim 6,
When the voltage difference between the equalized signal is a high level or a low level, the digital signal is output faster than the reference signal,
When the voltage difference of the equalized signal is at a middle level, the digital signal is output to be delayed from the reference signal. The method of claim 7,
The latch unit stores the digital signal as the logic data when the digital signal is output faster than the reference signal. The method of claim 7,
The latch unit, when the digital signal is output to be delayed from the reference signal, stores a reset value of the digital signal as the logic data. The method of claim 1,
The preset decoding table includes a 2UI 3BIT signal corresponding to the logic data, a decoding algorithm, charge pump data calculated according to the decoding algorithm, and output data corresponding to the charge pump data. The method of claim 10,
The charge pump data includes a NULL value,
The NULL value is assigned to a 2UI 3BIT signal of (0,0) corresponding to the highest symmetry on the EYE diagram. The method of claim 1,
The signal processing unit may include a linear equalization unit that linearly equalizes the differential signal;
A decision feedback equalizer that receives the digital signal and determines an equalized signal;
A first comparison unit comparing the equalized signals and outputting the digital signals; And
In response to the equalization signal, PAM-3 receiving apparatus comprising a second comparison unit for receiving a preset reference voltage and outputting the reference signal. The method of claim 12,
The latch unit may include a first latch unit including a first transistor having a gate connected to the second comparison unit and a second transistor having a gate connected to the first comparison unit; And
And a second latch unit including a third transistor having a gate connected to the second comparison unit and a fourth transistor having a gate connected to the first comparison unit. The method of claim 12,
The signal processing unit may include a clock providing unit providing a comparator input clock to the first and second comparators; And
And a short current path prevention unit for changing the logic state of the comparator input clock to a high state. The method of claim 12,
The PAM-3 receiving apparatus further comprising a dummy load unit for adjusting the size of the second reference signal according to the size of the first reference signal. A method of operating a PAM-3 receiving device, comprising:
Converting the transmission signal into a ground voltage-based differential signal by a signal converter;
Outputting, by a signal processor, a digital signal and a reference signal based on the differential signal;
Storing logic data for decoding into output data based on an output order of the digital signal and the reference signal by a latch unit; And
A decoding unit decoding the logic data stored in the latch unit into the output data according to a preset decoding table,
The transmission signal is a signal encoded as a 2UI 3BIT signal according to a preset encoding table. The method of claim 16,
The outputting may include linearly equalizing the differential signal;
Receiving the digital signal and determining an equalized signal; And
And outputting the reference signal by receiving the digital signal in response to the equalization signal and receiving a preset reference voltage. The method of claim 16,
The storing may include storing the digital signal as the logic data when the digital signal is output faster than the reference signal; And
And storing a reset value of the digital signal as the logic data when the digital signal is output to be delayed than the reference signal. The method of claim 16,
Receiving an external clock from a clock providing unit and providing a comparator input clock to the first and second comparators; And
The method of operating a PAM-3 receiving apparatus further comprising the step of changing a logic state of the comparator input clock to a high state based on the digital signal by a short current path prevention unit. A transmission device that transmits a transmission signal TX; And
A receiving device for receiving the transmission signal, converting it into a ground voltage-based differential signal, and decoding the stored logic data into output data according to an output order of a digital signal and a reference signal,
The transmission device,
An encoder encoding input data identical to the output data into an up-down signal; And
And a charge pump driver for transmitting the transmission signal corresponding to the 2UI 3BIT signal to the receiving device based on the up-down signal.

Images