KR102204355B1 - Inter-symbol interference minimized Pulse Amplitude Modulation 4 receiver - Google Patents

Abstract

The present invention discloses a PAM-4 receiver in which inter-symbol interference is minimized. The PAM-4 receiver of the present invention includes a continuous-time linear equalizer that filters high-frequency peaking and inter-code interference of the PAM-4 signal, and automatically adjusts the output of the filtered PAM-4 signal from the continuous-time linear equalizer to remain constant. After summing the judgment value and weight of the PAM-4 data included in the PAM-4 signal adjusted from the gain control unit and the automatic gain control unit, the feedback equalization is performed to compensate to reduce the error between symbols caused by signal distortion. The decision feedback equalizer unit including a plurality of decision feedback equalizer taps, the PAM-4 data received from the decision feedback equalizer unit and the error stream are converted from the serial-to-parallel converter unit and the serial-to-parallel converter unit to convert the serial state to the parallel state. It includes a pseudo-random bit sequence checker that checks the bit stream of the PAM-4 data and the error stream with a pseudo-random number.

Description

PAM-4 receiver with minimized inter-symbol interference {Inter-symbol interference minimized Pulse Amplitude Modulation 4 receiver}

The present invention relates to a pulse-amplitude modulation (PAM) technology, and more particularly, to a PAM-4 receiver in which interference between symbols is minimized, which solves an impedance mismatch problem and sufficiently secures a bandwidth.

As the bandwidth demands of data centers and telecommunication companies increase, discussions on the standard specifications of optical interfaces capable of operating up to 56Gb/s per channel are active. In order to implement such a high-speed optical interface, a high-efficiency multi-level signaling modulation technique such as pulse amplitude modulation is required instead of simple modulation of the conventional non-return-to-zero (NRZ) method.

That is, in order to improve the performance of the overall transmission system, it is necessary to increase the communication speed between the internal chip and the chip (Chip-to-Chip). In this way, a modulation technique such as PAM having a multilevel amplitude is used to satisfy high transmission capacity and increase channel efficiency in the interconnection.

However, in a conventional PAM receiver, a serious reflection characteristic was exhibited due to an impedance mismatch occurring at a PCB (Printed Circuit Board) substrate and a connection part. These reflections are fatal in PAM signals that require high linearity, and are difficult to solve effectively by a continuous-time linear equalizer (CTLE) at the receiving end or a feed-forward equalizer (FFE) at the transmitting end. There is this.

Korean Registered Patent Publication No. 10-1455095 (2014.10.21.)

The technical problem to be achieved by the present invention is to solve the problem that showed sensitivity to impedance mismatch, and to secure enough bandwidth to overcome the penalty of signal to noise ratio (SNR), intersymbol interference. , ISI) to reduce inter-symbol interference is minimized to provide a PAM-4 receiver.

In order to achieve the above object, the PAM-4 receiver with minimized inter-symbol interference according to an embodiment of the present invention prevents high frequency peaking and intersymbol interference of a Pulse Amplitude Modulation 4 (PAM-4) signal. Continuous-Time Linear Equalizer (CTLE) unit for filtering, Auto Gain Controller (AGC) that adjusts the output of the filtered PAM-4 signal from the continuous-time linear equalizer unit to be kept constant Part, a plurality of compensating to reduce the error between symbols caused by signal distortion by summing the decision value and weight of the PAM-4 data included in the PAM-4 signal adjusted by the automatic gain control unit, and then performing feedback equalization. Decision Feedback Equalizer (DFE) tab of the Decision Feedback Equalizer (DFE), a serial-to-parallel converter that converts PAM-4 data and error streams received from the Decision Feedback Equalizer from serial to parallel, and And a Pseudo-Random Bit Sequence (PRBS) tester that checks the bit stream of the PAM-4 data and the error stream converted by the serial-to-parallel converter using a pseudo-random number.

In addition, the decision feedback equalizer unit includes 10 DFE taps, and two current conversion circuits (Current Mode Logic, CML) supporting PAM-4 data paths for even and odd numbers including the 10 DFE taps. It characterized in that it comprises a current summing circuit connected in a cascade (cascade).

In addition, the current summing circuit corresponds to one of the two current conversion circuits, a first summing circuit including a third DFE tap to a tenth DFE tap among the 10 DFE taps, and the other of the two current conversion circuits. And a second summing circuit including a first DFE tap and a second DFE tap among the 10 DFE taps.

In addition, the second summing circuit is designed in a structure in which the first DFE tap is directly fed back and drives three data slicers and four error slicers corresponding to even and odd numbers, respectively. It is characterized by letting.

In addition, the current summing circuit further comprises a decoder for converting 3bit PAM-4 data generated from data slicers corresponding to even and odd numbers and a 4bit error stream generated from the error slicer into a 3bit binary code. .

In addition, the decoder is characterized in that it selects one valid stream from among the 4-bit error streams by using a stream value before deserialization.

In addition, the current summing circuit converts PAM-4 data for the first DFE tap, the second DFE tap, the third DFE tap, and the fourth DFE tap into thermometer encoding, and the fifth DFE tap and the sixth DFE tap It is characterized in that the PAM-4 data for the DFE tap, the 7th DFE tap, the 8th DFE tap, the 9th DFE tap, and the 10th DFE tap are converted into binary weights.

A PAM-4 receiver with minimized intersymbol interference according to another embodiment of the present invention includes a continuous-time linear equalizer that filters high-frequency peaking and inter-symbol interference of a PAM-4 signal, and a PAM-filtered from the continuous-time linear equalizer. 4 An automatic gain control unit that adjusts the output of the signal to be kept constant, and after adding the judgment value and weight of the PAM-4 data included in the PAM-4 signal adjusted from the automatic gain control unit, A decision feedback equalizer unit including a plurality of taps for compensating to reduce an error between symbols caused by signal distortion;

A serial-to-parallel converter unit for converting the PAM-4 data and error streams compensated from the decision feedback equalizer unit from a serial state to a parallel state, and the PAM-4 data and error streams converted from the serial-to-parallel converter unit as a pseudo-random number. Including a pseudo-random bit sequence inspection unit for checking the; LC phase-locked loop (Phase-Locked Loop, PLL) unit for fixing the frequency phase of the clock signal to be transmitted to the decision feedback equalizer unit and the LC phase-locked loop unit It further comprises a phase interpolator (Phase Interpolator) for interpolating the frequency phase of the clock signal transmitted from the signal to the decision feedback equalizer.

The PAM-4 receiver with minimized inter-symbol interference according to the present invention is designed to include a plurality of Decision Feedback Equalizer (DFE) taps, thereby solving the problem of being sensitive to impedance mismatch and ensuring sufficient bandwidth. Thus, interference between codes can be reduced.

Through this, it is possible to improve performance in terms of speed, quality, power consumption, area, etc. compared to a conventional receiver.

1 is a diagram illustrating a PAM-4 receiver according to an embodiment of the present invention.
2 is a view for explaining a DFE unit according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating a sense amplifier circuit applied to the DFE tab of FIG. 2.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, in adding reference numerals to elements of each drawing, note that the same elements are to have the same numerals as possible even if they are indicated on different drawings. In addition, in describing the present invention, when it is determined that a detailed description of a related known configuration or function is apparent to those skilled in the art or may obscure the subject matter of the present invention, the detailed description thereof will be omitted.

1 is a diagram illustrating a PAM-4 receiver according to an embodiment of the present invention.

Referring to FIG. 1, the PAM-4 receiver 100 solves the problem of exhibiting a characteristic sensitive to impedance mismatch, and reduces inter-code interference to overcome the SNR penalty by securing sufficient bandwidth. Here, the PAM-4 receiver 100 is an analog-based receiver and has an on-chip type. The PAM-4 receiver 100 includes a continuous-time linear equalizer (CTLE) unit (hereinafter referred to as'CTLE unit') (10) and an automatic gain controller (AGC) unit (hereinafter referred to as ,'AGC unit') (20), Decision Feedback Equalizer (DFE) unit (hereinafter referred to as'DFE unit') 30, deserializer unit 40 and doctor Including a Pseudo-Random Bit Sequence (PRBS) inspection unit (hereinafter referred to as'PRBS inspection unit'), and an LC phase-locked loop (PLL) unit (hereinafter referred to as'PLL unit') (60) and a phase interpolator (Phase Interpolator) unit 70 is further included.

The CTLE unit 10 filters high-frequency peaking and inter-code interference for the PAM-4 signal received from the receiving end of the PAM-4 receiver 100. That is, the CTLE unit 10 removes high frequency peaking and inter-code interference included in the PAM-4 signal. The CTLE unit 10 may include a plurality of CTLE elements and filter high-frequency peaking and inter-symbol interference through a plurality of steps. Through this, the CTLE unit 10 may reduce the number of DFE taps to be included in the DFE unit 30.

Here, it further includes an on-die termination (ODT) including a termination resistor for impedance matching between the receiving end and the CTLE unit 10 and an electrostatic discharge (ESD) discharged when the charged charge is grounded.

The AGC unit 20 adjusts the output of the filtered PAM-4 signal from the CTLE unit 10 to be kept constant. The AGC unit 20 automatically adjusts the gain by sensing the strength of the PAM-4 signal. Through this, the AGC unit 20 may increase the reception rate of the PAM-4 signal.

The DFE unit 30 sums the determination values and weights of the PAM-4 data included in the PAM-4 signal adjusted from the AGC unit 20, and then performs feedback equalization so that errors between symbols caused by signal distortion are attenuated. Includes multiple DFE taps to compensate. At this time, the DFE unit 30 is driven by receiving a half-rate clock signal. The DFE unit 30 outputs the sampled 4bit PAM-4 data and 2bit error stream by performing data slicing and error slicing. The DFE unit 30 may transmit the 4bit PAM-4 data and the 2bit error stream to the serial/parallel converter unit 40 at a rate of 14Gb/s. Here, the DFE unit 30 includes two or more DFE taps, and preferably may include 10 DFE taps.

The serial-to-parallel converter unit 40 deserializes the PAM-4 data and the error stream received from the DFE unit 30. That is, the serial-to-parallel converter unit 40 converts the PAM-4 data and the error stream from the serial state to the parallel state. Through this, the serial-to-parallel converter unit 40 converts the PAM-4 data from 4 bits to 128 bits, and converts the error stream from 2 bits to 64 bits. The serial-to-parallel converter unit 40 may transmit 128-bit PAM-4 data and a 64-bit error stream to the PRBS inspection unit 50 at a rate of 437.5 Mb/s.

The PRBS inspection unit 50 inspects the bit string of the PAM-4 data and the error stream converted from the serial-to-parallel converter unit 40 with a pseudo-random number. The PRBS inspection unit 50 secures the reliability of the PAM-4 data and the error stream by inspecting the bit string. The PRBS inspection unit 50 includes a data storage buffer. Through this, the PRBS inspection unit 50 stores the PAM-4 data and the error stream inspected for the bit string in the data storage buffer.

The LC-PLL unit 60 fixes the frequency phase of the clock signal to be transmitted to the DFE unit 30. The LC-PLL unit 60 serves to transmit a clock signal having a frequency of four phases to the phase interpolation 70. At this time, the transmitted clock signal may have a frequency of 14 GHz.

The phase interpolation unit 70 interpolates the frequency phase of the clock signal transmitted from the LC-PLL unit 60 and transmits it to the DFE unit 30. The phase interpolation unit 70 converts a clock signal having four phase frequencies into a clock signal having two phase frequencies during interpolation.

Meanwhile, the off-chip controller 200 controls the driving of the PAM-4 receiver 100 from the outside. The off-chip controller 200 performs a buad-rate clock and data recovery (CDR) and PAM level adaptation. The off-chip controller 200 controls the output phase of the phase interpolation unit 70 so that data is sampled at an appropriate sampling point through a transmission rate ratio clock/data recovery technique. The off-chip controller 200 adjusts an error slicer and a data threshold based on a voltage level of a slicer input through a PAM level adaptation technique. In addition, the off-chip controller 200 periodically loads the sampled PAM-4 data and error stream from the storage data buffer in order to perform a transmission rate ratio clock/data recovery technique and a PAM level adaptation technique.

2 is a view for explaining a DFE unit according to an embodiment of the present invention.

1 and 2, the DFE unit 30 includes a plurality of DFE taps. Here, the DFE unit 30 may include 10 DFE taps. The DFE unit 30 includes a first DFE tab (h1), a second DFE tab (h2), a third DFE tab (h3), a fourth DFE tab (h4), a fifth DFE tab (h5), and a sixth DFE tab. (h6), a seventh DFE tab (h7), an eighth DFE tab (h8), a ninth DFE tab (h9), and a tenth DFE tab (h10).

The DFE unit 30 supports two current conversion circuits supporting PAM-4 data paths for even and odd numbers including the first DFE tap to the tenth DFE tap in order to meet the accurate DFE feedback timing. Mode Logic, CML) includes a current summing circuit connected in a cascade. That is, the current conversion circuit is designed to include a first summing circuit 31 and a second summing circuit 32, and the output terminal of the first summing circuit 31 is connected to the input terminal of the second summing circuit 32 do.

The first summing circuit 31 includes an input terminal of the current conversion circuit, and includes a third DFE tap to a tenth DFE tap among 10 DFE taps. The first summing circuit 31 is designed so that PAM-4 data for even and odd numbers are classified in each tap corresponding to the third DFE tap to the tenth DFE tap.

The second summing circuit 32 is connected to the output terminal of the first summing circuit 31, includes an output terminal of the current conversion circuit, and includes a first DFE tap and a second DFE tap among 10 DFE taps. The second summing circuit 32 is designed so that PAM-4 data for even and odd numbers are classified in each tap corresponding to the first DFE tap and the second DFE tap.

Here, in the second summing circuit 32, in order to reduce the load of the summing node, minimize power consumption, and reduce design complexity, the first DEF tap is not a widely used inference method, but directly feedback. It is designed in a structure that can be used. Through this, the second summing circuit 32 includes three data slicers (DL, DZ, DH) 33 and four error slicers (ELN, EHN, respectively) corresponding to even and odd numbers. ELP, EHP) 34 is driven.

The current summing circuit converts PAM-4 data for the first DFE tap, the second DFE tap, the third DFE tap, and the fourth DFE tap into thermometer encoding to reduce the load of high-speed DFE feedback signals. The current summing circuit converts PAM-4 data for the 5th DFE tap, the 6th DFE tap, the 7th DFE tap, the 8th DFE tap, the 9th DFE tap and the 10th DFE tap into binary weights.

The total summation circuit further includes a decoder 35 for converting the 3bit PAM-4 data generated from the data slicer 33 corresponding to even and odd numbers and the 4bit error stream generated from the error slicer 34 into a 3bit binary code. Include. Here, the 3-bit binary code is a 2-bit PAM-4 data and 1-bit error stream. At this time, the decoder 35 selects one valid stream from among the 4-bit error streams by using the stream value before deserialization. The decoder 35 transmits the converted 3-bit binary code to the serial-to-parallel converter unit 40.

FIG. 3 is a diagram illustrating a sense amplifier circuit applied to the DFE tab of FIG. 2.

2 and 3, in general, matching the feedback timing of the first DFE tap directly to the output node of the second summing circuit 32 causes a serious problem in circuit implementation. Accordingly, the sense amplifier applied to the DFE tap of the DFE unit 30 is designed so that the optimized speed is matched to the first DFE tap path. That is, the data slicer 33 directly delays the QP and QN outputs of the master latch, and uses a pre-charged complementary metal-oxide semiconductor (CMOS) inverter amplifier. 1 Pass it to the DFE tab.

Here, when the clock signal is a falling edge, the output polarity of the first DFE tap is precharged with a power supply voltage to apply a common mode tap current to the second summing circuit 32. When the clock signal is at the rising edge, the pseudo differential output of the first DFE tap starts to be output, and finally, the first DFE tap current flows to the output of the second summing circuit 32. It is fixed as a complimentary rail-to-to signal.

Meanwhile, in order to prevent the tail node of the current conversion circuit of the first DFE tap of the second summing circuit 32 from dipping in the regeneration stage of the sense amplifier, the timing at which pre-charging is performed is applied to the two inverters. Delayed by the sampling edge. Through this, the second summing circuit 32 can be stabilized.

The output of the second DFE tap is called from a keeper latch that determines sampled data. At this time, since the four error slicers 34 do not need to meet the timing, they are designed as a master-slave StrongArm sense amplifier previously used as a smaller device to reduce power consumption.

Therefore, the sampling aperture timing of the data slicer 33 and the error slicer 34 is a systematic offset from the phase of the sampling clock signal out of the optimal clock/data recovery lock position. Match what is characterized to prevent.

As described above, the conventional receiver with the DFE function is disadvantageous in terms of area and power consumption by using NRZ modulation or PAM-4 including an analog-digital converter (ADC)-based DFE, and is disadvantageous in terms of impedance mismatch. It showed sensitive characteristics. However, the PAM-4 receiver 100 of the present invention has improved performance in terms of data rate, quality, power consumption, and area compared to a conventional receiver.

Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific preferred embodiments described above, and without departing from the gist of the present invention claimed in the claims, in the technical field to which the present invention pertains. Anyone of ordinary skill in the art can implement various modifications, as well as such modifications will be within the scope of the claims.

10: CTLE part
20: AGC unit
30: DFE part
31: first summing circuit
32: second summing circuit
33: data slicer
34: error slicer
35: decoder
40: serial-to-parallel converter unit
50: PRBS inspection unit
60: LC-PLL part
70: phase interpolation unit
100: PAM-4 receiver
200: off-chip controller

Claims (8)

A Continuous-Time Linear Equalizer (CTLE) unit for filtering high frequency peaking and intersymbol interference of a Pulse Amplitude Modulation 4 (PAM-4) signal;
An automatic gain controller (AGC) unit for adjusting the output of the filtered PAM-4 signal from the continuous-time linear equalizer unit to be kept constant;
After summing the judgment value and weight of the PAM-4 data included in the PAM-4 signal adjusted by the automatic gain control unit, feedback equalization is performed to compensate for reducing the error between symbols caused by signal distortion. A decision feedback equalizer unit including a Decision Feedback Equalizer (DFE) tab;
A serial-to-parallel converter for converting the PAM-4 data and error streams received from the decision feedback equalizer from a serial state to a parallel state; And
Including; a Pseudo-Random Bit Sequence (PRBS) test unit for checking a bit sequence of the PAM-4 data and the error stream converted from the serial-to-parallel converter unit with a pseudo-random number,
The decision feedback equalizer unit,
Includes 10 DFE taps and includes two current mode logic (CML) cascaded currents that support the PAM-4 data path for even and odd numbers including the 10 DFE taps. Circuit; includes,
The current summing circuit,
A first summing circuit corresponding to one of the two current conversion circuits and including a third DFE tap to a tenth DFE tap among the ten DFE taps; And
A second summing circuit corresponding to the remaining one of the two current conversion circuits and including a first DFE tap and a second DFE tap among the 10 DFE taps;
PAM-4 receiver with minimized inter-symbol interference, comprising a. delete delete The method of claim 1,
The second summing circuit,
Intersymbol interference, characterized in that the first DFE tap is designed in a structure in which direct feedback is provided to drive three data slicers and four error slicers corresponding to even and odd numbers, respectively. This minimized PAM-4 receiver. The method of claim 4,
The current summing circuit,
A decoder for converting 3bit PAM-4 data generated from data slicers corresponding to even and odd numbers and 4bit error streams generated from error slicers into 3bit binary code;
PAM-4 receiver with minimized inter-symbol interference, characterized in that it further comprises. The method of claim 5,
The decoder,
A PAM-4 receiver with minimized inter-symbol interference, characterized in that selecting one valid stream from among the 4-bit error streams by using a stream value before deserialization. The method of claim 1,
The current summing circuit,
PAM-4 data for the first DFE tab, the second DFE tab, the third DFE tab, and the fourth DFE tab are converted into thermometer encoding, and the 5th DFE tab, the 6th DFE tab, and the 7th DFE tab And converting PAM-4 data for the 8th DFE tap, the 9th DFE tap, and the 10th DFE tap into binary weights. A continuous-time linear equalizer for filtering high-frequency peaking and inter-code interference of the PAM-4 signal;
An automatic gain control unit for adjusting the output of the filtered PAM-4 signal from the continuous-time linear equalizer unit to be kept constant;
A plurality of taps for compensating so that errors between symbols caused by signal distortion are reduced by summing the determination values and weights of PAM-4 data included in the PAM-4 signal adjusted by the automatic gain control unit, and equalizing feedback Decision feedback equalizer unit comprising a;
A serial-to-parallel converter for converting the PAM-4 data and error streams compensated by the decision feedback equalizer from a serial state to a parallel state;
A pseudo-random bit sequence test unit for checking a bit stream with a pseudo random number on the PAM-4 data and the error stream converted by the serial-to-parallel converter unit;
An LC phase-locked loop (PLL) unit for fixing a frequency phase of a clock signal to be transmitted to the decision feedback equalizer unit; And
Including; a phase interpolator (Phase Interpolator) for interpolating the frequency phase of the clock signal transmitted from the LC phase-locked loop unit and transmits it to the decision feedback equalizer unit,
The decision feedback equalizer unit,
Includes 10 DFE taps, and a current summing circuit in which two current conversion circuits are cascaded to support PAM-4 data paths for even and odd numbers including the 10 DFE taps,
The current summing circuit,
A first summing circuit corresponding to one of the two current conversion circuits and including a third DFE tap to a tenth DFE tap among the ten DFE taps; And
A second summing circuit corresponding to the remaining one of the two current conversion circuits and including a first DFE tap and a second DFE tap among the 10 DFE taps;
PAM-4 receiver with minimized inter-symbol interference, comprising a.

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