KR20190052472A - Inter-symbol interference minimized Pulse Amplitude Modulation 4 receiver - Google Patents

Abstract

Disclosed in the present invention is a pulse amplitude modulation 4 (PAM-4) receiver with minimized intersymbol interference. The PAM-4 receiver, according to the present invention, comprises: a continuous-time linear equalizer (CTLE) unit for filtering high frequency peaking and intersymbol interference of a PAM-4 signal; an auto gain control (AGC) unit for performing adjustment so an output of the PAM-4 signal filtered from the CTLE unit is constantly maintained; a decision feedback equalizer (DFE) unit including a plurality of DFE taps for summing the weight and determination value of PAM-4 data included in the PAM-4 signal adjusted from the AGC unit, performs feedback equalization of the summed value, and performs compensation to reduce errors between symbols caused by signal distortion; a serial-to-parallel converter unit for converting error streams and the PAM-4 data received from the DFE unit from a serial state to a parallel state; and a pseudo-random bit sequence (PRBS) check unit for checking a bit string with a pseudo-random number with respect to the PAM-4 data and the error streams converted from the serial-to-parallel converter unit.

Description

A PAM-4 receiver with minimized inter-symbol interference {Inter-symbol interference minimized Pulse Amplitude Modulation 4 receiver}

The present invention relates to a pulse amplitude modulation (PAM) technique, and more particularly, to a PAM-4 receiver in which impedance mismatching problems are solved and inter-symbol interference is minimized to ensure sufficient bandwidth.

As demand for bandwidth of data center and telecommunication companies increases, there is a lot of discussion about optical interface standard specification which can operate up to 56 Gb / s per channel. In order to realize such a high-speed optical interface, a high-efficiency multi-level signaling modulation technique such as pulse amplitude modulation is required instead of conventional non-return-to-zero (NRZ) simple modulation.

That is, in order to improve the performance of the overall transmission system, the communication speed between the internal chip and the chip (chip-to-chip) must be increased. In this way, a modulation scheme such as PAM with multi-level amplitude is used to meet the high transmission capacity in the interconnection and to increase the channel efficiency.

However, the conventional PAM receiver showed severe reflection characteristics due to the impedance mismatch occurring at the connection portion with the printed circuit board (PCB). These reflections are fatal in PAM signals requiring high linearity and are difficult to effectively solve due to the continuous-time linear equalizer (CTLE) of the receiving end or the feed-forward equalizer (FFE) of the transmitting end. .

Korean Registered Patent No. 10-1455095 (Oct. 21, 2014)

SUMMARY OF THE INVENTION The present invention has been made in order to solve the problem of being susceptible to impedance mismatching and to provide a sufficient bandwidth to prevent intersymbol interference (SNR) penalties to overcome the SNR penalty. , ISI) that minimizes inter-symbol interference.

In order to achieve the above object, a PAM-4 receiver in which inter-symbol interference is minimized according to an embodiment of the present invention performs high frequency peaking and intersymbol interference of a PAM-4 (Pulse Amplitude Modulation 4) An automatic gain controller (AGC) that adjusts the output of the PAM-4 signal filtered from the continuous time linear equalizer unit to be constant, a constant time linear equalizer 4 compensates the error between the symbols generated by the signal distortion by summing up the estimated values and weights of the PAM-4 data included in the PAM-4 signal adjusted by the automatic gain control unit, A decision feedback equalizer including a decision feedback equalizer (DFE) tap of the decision feedback equalizer, a PAM-4 data and error stream received from the decision feedback equalizer, And a Pseudo-Random Bit Sequence (PRBS) checking unit for checking the PAM-4 data and the error stream, which have been converted from the serial-to-parallel converter unit, into a pseudo-random number bit string. .

The decision feedback equalizer also includes two current switching circuits (CMLs), including ten DFE taps and supporting the PAM-4 data path for even and odd numbers, including the ten DFE taps And a current summation circuit connected in cascade.

The current summing circuit may further include a first summing circuit corresponding to one of the two current switching circuits and including a third DFE tap to a tenth DFE tap among the ten DFE taps, And a second summing circuit corresponding to one of the 10 DFE taps and including a first DFE tap and a second DFE tap.

The second summing circuit is designed to have a structure in which the first DFE tap is directly feedbacked to drive three data slicers and four error slicers corresponding to even and odd numbers, .

The current summation circuit may further include a decoder for converting the 3-bit PAM-4 data generated from the data slicer corresponding to the even and odd numbers and the 4-bit error stream generated from the error slicer into the 3-bit binary code .

Also, the decoder selects one of the 4-bit error streams using a stream value before deserialization.

The current summation circuit also converts the PAM-4 data for the first DFE tap, the second DFE tap, the third DFE tap, and the fourth DFE tap into a thermometer encoding and the fifth DFE tap, 4 data for the DFE tap, the seventh DFE tap, the eighth DFE tap, the ninth DFE tap, and the tenth DFE tap are converted into binary weights.

The PAM-4 receiver with minimized inter-symbol interference according to another embodiment of the present invention includes a continuous time linear equalizer unit for filtering high frequency peaking and intersymbol interference of a PAM-4 signal, a PAM-4 filtered from the continuous time linear equalizer unit, 4 signal from the PAM-4 signal adjusted by the PAM-4 signal from the PAM-4 signal adjusted by the automatic gain control unit, and then feedback-equalizes the PAM- A decision feedback equalizer including a plurality of taps that compensate for errors between symbols caused by signal distortion to be reduced;

A PAM-4 data and an error stream from the decision feedback equalizer to convert the PAM-4 data and the error stream from a serial state to a parallel state, and a PAM-4 data and error stream converted from the deserialization equalizer, A phase locked loop (PLL) unit for fixing a frequency phase of a clock signal to be transmitted to the decision feedback equalizer unit and a phase locked loop And a phase interpolator for interpolating a frequency phase of the clock signal transmitted from the phase comparator and transmitting the interpolated frequency phase to the decision feedback equalizer.

The PAM-4 receiver in which the inter-symbol interference of the present invention is minimized is designed to include a plurality of decision feedback equalizers (DFE) taps, thereby solving the problem of being sensitive to impedance mismatch, Thereby reducing inter-symbol interference.

This can improve performance in terms of speed, quality, power consumption and area compared to conventional receivers.

1 is a view for explaining a PAM-4 receiver according to an embodiment of the present invention.
2 is a view for explaining a DFE unit according to an embodiment of the present invention.
3 is a diagram for explaining a sense amplifier circuit applied to the DFE tap of FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals as used in the appended drawings denote like elements, unless indicated otherwise. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather obvious or understandable to those skilled in the art.

1 is a view for explaining a PAM-4 receiver according to an embodiment of the present invention.

Referring to FIG. 1, the PAM-4 receiver 100 solves the problem of being sensitive to impedance mismatch, and reduces intersymbol interference so that sufficient bandwidth can be secured to overcome the SNR penalty. Here, the PAM-4 receiver 100 is an analog-based receiver and is on-chip. The PAM-4 receiver 100 includes a Continuous-Time Linear Equalizer (CTLE) unit 10, an Auto Gain Controller (AGC) unit A DFE unit 30, a deserializer 40 and a DFE unit 30. The DFE unit 30 includes a DFE unit 30, an AGC unit 20, a Decision Feedback Equalizer (DFE) unit 30, (PLL) unit (hereinafter, referred to as " PLL unit ") including a pseudo-random bit sequence (PRBS) (60) and a phase interpolator (70).

The CTLE unit 10 filters high-frequency peaking and intersymbol interference for the PAM-4 signal received from the receiving end of the PAM-4 receiver 100. [ That is, the CTLE unit 10 eliminates the high-frequency peaking and intersymbol interference included in the PAM-4 signal. The CTLE unit 10 may include a plurality of CTLE elements to filter high-frequency peaking and intersymbol interference while passing through a plurality of stages. Thus, the CTLE unit 10 can reduce the number of DFE taps to be included in the DFE unit 30. [

Here, an on-die termination (ODT) including a termination resistance for impedance matching is provided between the receiving end and the CTLE unit 10, and an electrostatic discharge (ESD) discharging when the charged electric charges are grounded.

The AGC unit 20 adjusts the output of the filtered PAM-4 signal from the CTLE unit 10 to be constant. The AGC unit 20 detects the intensity of the PAM-4 signal and automatically adjusts the gain. Accordingly, the AGC unit 20 can increase the reception rate of the PAM-4 signal.

The DFE unit 30 sums the sum and the weight of the PAM-4 data included in the PAM-4 signal adjusted by the AGC unit 20 and then performs feedback equalization so that the error between the symbols generated by the signal distortion is attenuated And a plurality of DFE taps to compensate. At this time, the DFE unit 30 is driven by receiving a half-rate clock signal. The DFE unit 30 performs data slicing and error slicing to output sampled 4-bit PAM-4 data and a 2-bit error stream. The DFE unit 30 can transmit the 4-bit PAM-4 data and the 2-bit error stream to the deserializer 40 at a rate of 14 Gb / s. Here, the DFE unit 30 includes two or more DFE taps, and preferably, may include ten DFE taps.

The deserializer unit 40 deserializes the PAM-4 data and the error stream received from the DFE unit 30. That is, the deserializer unit 40 converts the PAM-4 data and the error stream from the serial state to the parallel state. The serial-to-parallel converter unit 40 converts the PAM-4 data from 4 bits to 128 bits, and converts the error stream from 2 bits to 64 bits. The deserializer unit 40 can transmit the 128-bit PAM-4 data and the 64-bit error stream to the PRBS checking unit 50 at a rate of 437.5 Mb / s.

The PRBS inspecting unit 50 inspects the bit stream of the converted PAM-4 data and the error stream from the deserializer 40 using a pseudo-random number. The PRBS checking unit 50 inspects the bit stream to secure the reliability of the PAM-4 data and the error stream. The PRBS checking unit 50 includes a data storing buffer. Accordingly, the PRBS inspecting unit 50 stores the PAM-4 data and the error stream, which have been checked for the bit stream, in the data storage buffer.

The LC-PLL unit 60 fixes the frequency phase of the clock signal to be transmitted to the DFE unit 30. [ The LC-PLL unit 60 serves to transmit a clock signal having a frequency of four phases to the phase interpolation 70. At this time, the transmitted clock signal may have a frequency of 14 GHz.

The phase interpolation unit 70 interpolates the frequency phase of the clock signal transmitted from the LC-PLL unit 60 and transmits it to the DFE unit 30. [ The phase interpolation unit 70 converts a clock signal having four phase frequencies into a clock signal having two phase frequencies in the course of interpolation.

On the other hand, the off-chip controller 200 externally controls the operation of the PAM-4 receiver 100. Off-chip controller 200 performs buad-rate clock and data recovery (CDR) and PAM level adaptation. The off-chip controller 200 controls the output phase of the phase interpolator 70 so that data is sampled at an appropriate sampling point through a transmission rate ratio clock / data recovery technique. Off-chip controller 200 adjusts the error slicer and data threshold based on the voltage level of the slicer input through the PAM level adaptation technique. The off-chip controller 200 also periodically fetches the sampled PAM-4 data and error stream from the storage data buffer to perform the transmission rate ratio clock / data recovery technique and the PAM level adaptation technique.

2 is a view for explaining a DFE unit according to an embodiment of the present invention.

Referring to Figs. 1 and 2, the DFE unit 30 includes a plurality of DFE taps. Here, the DFE unit 30 may include ten DFE tabs. The DFE unit 30 includes a first DFE tap h1, a second DFE tap h2, a third DFE tap h3, a fourth DFE tap h4, a fifth DFE tap h5, a seventh DFE tap h6, a seventh DFE tap h7, an eighth DFE tap h8, a ninth DFE tap h9, and a tenth DFE tap h10.

The DFE unit 30 includes two current-switching circuits (Current) for supporting the PAM-4 data path for even and odd numbers, including first DFE taps to tenth DFE taps, to meet accurate DFE feedback timing. Mode Logic, CML) connected in cascade. That is, the current switching circuit includes a first summing circuit 31 and a second summing circuit 32, and the output of the first summing circuit 31 is connected to the input of the second summing circuit 32 do.

The first summing circuit 31 includes the input terminal of the current switching circuit and includes the third DFE taps to the tenth DFE taps among the ten DFE taps. The first summing circuit 31 is designed such that the taps corresponding to the third DFE tap to the tenth DFE tap divide the PAM-4 data for even and odd numbers.

The second summation circuit 32 is connected to the output of the first summation circuit 31 and includes the output stage of the current switching circuit and includes a first DFE tap and a second DFE tap of the ten DFE taps. The second summation circuit 32 is designed such that the PAM-4 data for even and odd numbers of each tap corresponding to the first DFE tap and the second DFE tap are distinguished.

Here, the second summing circuit 32 is a direct feedback circuit in which the first DEF tap, which is not a conventionally widely used inference method, is used to reduce the load on the summing node, minimize the power consumption, . Thus, the second summing circuit 32 includes three data slicers (DL, DZ, DH) 33 and four error slicers (ELN, EHN, ELP, and EHP) 34, respectively.

The current summation circuit converts the PAM-4 data for the first DFE tap, the second DFE tap, the third DFE tap and the fourth DFE tap into a thermometer encoding to reduce the load on the fast DFE feedback signals. The current summation circuit converts the PAM-4 data for the fifth DFE tap, the sixth DFE tap, the seventh DFE tap, the eighth DFE tap, the ninth DFE tap, and the tenth DFE tap into binary weights.

The joint summing circuit further includes a decoder 35 for converting the 3-bit PAM-4 data generated from the data slicer 33 corresponding to even and odd numbers and the 4-bit error stream generated from the error slicer 34 into a 3-bit binary code . Here, the 3-bit binary code is 2-bit PAM-4 data and 1-bit error stream. At this time, the decoder 35 selects one of the 4-bit error streams using the stream value before deserialization. The decoder 35 transmits the converted 3-bit binary code to the deserializer 40. [

3 is a diagram for explaining a sense amplifier circuit applied to the DFE tap of FIG.

2 and 3, adjusting the feedback timing of the first DFE tap directly to the output node of the second summing circuit 32 generally causes a serious problem in circuit implementation. Therefore, the sense amplifier applied to the DFE tap of the DFE section 30 is designed to be optimized in speed in the first DFE tap path. That is, the data slicer 33 directly delays the master latch outputs QP and QN and outputs the master latch outputs QP and QN through the pre-charged complementary metal-oxide semiconductor (CMOS) 1 Transmit to the DFE tab.

Here, when the clock signal is a falling edge, the output bipolarity of the first DFE tap is precharged to the supply voltage to apply a common mode tap current to the second summing circuit 32. When the clock signal is at the rising edge, the pseudo-differential output of the first DFE tap begins to be output, and finally the complementary rail to the first DFE tap current flows to the output of the second summation circuit 32 (Complimentary rail-to-toe) signal.

On the other hand, in order to prevent the tail node of the current switching circuit of the first DFE tap of the second summation circuit 32 from being dipped during the regeneration step of the sense amplifier, Lt; / RTI > Thereby, the second summing circuit 32 can achieve stabilization.

The output of the second DFE tap is fetched from a keeper latch that sets the sampled data. At this time, the four error slicers 34 do not have to meet timing, so they are designed with a master-slave StrongArm sense amplifier that was previously used as a smaller device to reduce power consumption.

Thus, the sampling aperture timing of the data slicer 33 and the error slicer 34 is determined by the systematic offset in the phase of the sampling clock signal out of the optimal clock / data recovery lock position In order to prevent the occurrence of the disease.

As described above, the receiver with the conventional DFE function is disadvantageous in terms of area and power consumption by using the NRZ modulation or using the PAM-4 including the analog-digital converter (ADC) based DFE, Sensitive properties. However, the PAM-4 receiver 100 of the present invention improves performance in terms of data rate, quality, power consumption and area as compared with the conventional receiver.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation in the embodiment in which said invention is directed. It will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the appended claims.

10: CTLE section
20: AGC section
30: DFE section
31: First summing circuit
32: second summation circuit
33: data slicer
34: Error Slicer
35: decoder
40: deserializer
50: PRBS inspection section
60: LC-PLL section
70: Phase interpolation section
100: PAM-4 receiver
200: Off-chip controller

Claims (8)

A Continuous-Time Linear Equalizer (CTLE) unit for filtering high-frequency peaking and intersymbol interference of a PAM-4 (Pulse Amplitude Modulation 4) signal;
An automatic gain controller (AGC) unit for adjusting the output of the PAM-4 signal filtered from the continuous time linear equalizer unit to be constant;
A plurality of judges for summing up the judgment values and weights of the PAM-4 data included in the PAM-4 signal adjusted by the automatic gain control unit and performing feedback equalization so as to reduce the error between the symbols caused by the signal distortion; A decision feedback equalizer including a Decision Feedback Equalizer (DFE) tap;
A serial-to-parallel converter unit for converting the PAM-4 data and the error stream received from the decision feedback equalizer unit from a serial state to a parallel state; And
A Pseudo-Random Bit Sequence (PRBS) checking unit for checking the PAM-4 data and the error stream converted from the deserializer;
PAM-4 receiver with minimized intersymbol interference. The method according to claim 1,
Wherein the decision feedback equalizer comprises:
Two current-switching circuits (CMLs) that include 10 DFE taps and support the PAM-4 data path for even and odd numbers, including the 10 DFE taps, are cascade- Wherein the inter-symbol interference is minimized. 3. The method of claim 2,
Wherein the current summation circuit comprises:
A first summing circuit corresponding to one of the two current switching circuits and including a third DFE tap to a tenth DFE tap among the ten DFE taps; And
A second summing circuit corresponding to the remaining one of the two current switching circuits, the first summing circuit including a first DFE tap and a second DFE tap of the ten DFE taps;
Wherein the PAM-4 receiver minimizes inter-symbol interference. The method of claim 3,
Wherein the second summing circuit comprises:
The first DFE tap is designed to be a direct feedback structure to drive three data slicers and four error slicers corresponding to even and odd numbers, This minimized PAM-4 receiver. 5. The method of claim 4,
Wherein the current summation circuit comprises:
A decoder for converting the 3-bit PAM-4 data generated from the data slicer corresponding to the even and odd numbers and the 4-bit error stream generated from the error slicer into the 3-bit binary code;
Wherein the PAM-4 receiver minimizes inter-symbol interference. 6. The method of claim 5,
The decoder includes:
Wherein one of the 4-bit error streams is selected using a stream value prior to deserialization. The method of claim 3,
Wherein the current summation circuit comprises:
Converts the PAM-4 data for the first DFE tap, the second DFE tap, the third DFE tap and the fourth DFE tap into a thermometer encoding and the fifth DFE tap, the sixth DFE tap, the seventh DFE tap, , The eighth DFE tap, the ninth DFE tap, and the tenth DFE tap are converted into binary weights, wherein the inter-symbol interference is minimized. A continuous time linear equalizer for filtering high frequency peaks and intersymbol interference of a PAM-4 signal;
An automatic gain control unit for adjusting the output of the PAM-4 signal filtered from the continuous time linear equalizer unit to be constant;
A plurality of tapes for compensating for errors between symbols caused by signal distortion by summing up the estimated values and weights of the PAM-4 data included in the PAM-4 signal adjusted by the automatic gain control unit, A decision feedback equalizer comprising:
A deserializer unit for converting the compensated PAM-4 data and error stream from the decision feedback equalizer unit from a serial state to a parallel state; And
And a pseudo-random number bit string check unit for checking a bit string by pseudo-random number in the PAM-4 data and the error stream converted from the serializer unit,
An LC phase-locked loop (PLL) unit for fixing a frequency phase of a clock signal to be transmitted to the decision feedback equalizer; And
A phase interpolator for interpolating the frequency phase of the clock signal transmitted from the LC phase locked loop and transmitting the interpolated frequency phase to the decision feedback equalizer;
Wherein the inter-symbol interference is minimized.

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