KR102491784B1 - Duo-binary receiver and transceiver with ground-referenced signaling - Google Patents

Abstract

The purpose of the present invention is to provide a duo binary receiver and transceiver using a ground signal technique that can reduce power consumption, signal noise, and hardware costs. According to one aspect of the present disclosure, in a receiver including a decoder that receives and decodes a first signal corresponding to a first time unit and a second signal corresponding to a second time unit after the first time unit, if the second signal has a high level or a low level among three signal levels, wherein the three signal levels include the high level, a middle level, and the low level, the decoder decodes the second signal as 1 or 0. When the second signal has the middle level, the decoder decodes the second signal based on the decoding result of the first signal.

Description

Duo binary receiver and transceiver using ground signal technique {DUO-BINARY RECEIVER AND TRANSCEIVER WITH GROUND-REFERENCED SIGNALING}

The present disclosure relates to a duo binary receiver and transceiver using a ground signal technique.

In conventional high-speed single-channel I/O (input/output) circuits, current is supplied or cut off from a supply voltage according to data during signal transmission. However, as shown in FIG. 1, the conventional high-speed single-channel I/O circuit generates noise due to inductors, resistors, capacitors, etc. in the supply voltage, and such noise is reflected in data, greatly degrading signal accuracy. In addition, existing high-speed single-channel I/O circuits require a separate reference voltage.

Among technologies to improve this, the ground signal-based transmission technology stores charge in a capacitor as shown in FIG. 2, transmits data after removing the connection with the supply voltage, and transmits current from the supply voltage constantly through two parallel transmitter driver structures. let it flow At this time, since only the current path through the ground is used, the noise of the supply voltage is greatly reduced, and since the ground voltage can be used as a reference voltage of a single channel structure, there is no need to supply a separate reference voltage. However, existing ground signal-based transmission technology has only a structure designed for a single channel.

Meanwhile, duo-binary signaling is a signaling technique in which two signal levels used for data transmission are changed to three signal levels. As shown in FIG. 3, the existing duo-binary signaling technology has a method in which a 2:1 multiplexer is replaced through encoding. However, this has a problem in that hardware cost is high because four comparators and two reference voltages are required for decoding. In addition, when middle level data is input to the comparator, there is a problem in that the decision of data is delayed and is determined randomly.

Korean Registered Patent No. 10-2257233 Korean Registered Patent No. 10-1978470

Various examples of the present disclosure are to provide a duo-binary receiver and transceiver using a ground signal technique capable of reducing power consumption, signal noise, and hardware cost.

The technical problems to be achieved in various examples of the present disclosure are not limited to those mentioned above, and other technical problems not mentioned above can be solved by those skilled in the art from various examples of the present disclosure to be described below. can be considered by

In one aspect of the present disclosure, in a receiver including a decoder receiving and decoding a first signal corresponding to a first time unit and a second signal corresponding to a second time unit after the first time unit , the second signal has three signal levels, wherein the three signal levels include a high level, a middle level, and a low level; of the high level or the low level, the decoder decodes the second signal as 1 or 0, and when the second signal has the middle level, the decoder determines the decoding result of the first signal It is a receiver that decodes the second signal based on.

For example, when the second signal has the middle level, the decoder decodes the second signal as 0 when the decoding result of the first signal is 1, and the decoding result of the first signal is 0. In this case, the second signal may be decoded as 1.

For example, the middle level may correspond to the ground level.

In another aspect of the present disclosure, a receiver including a decoder receiving and decoding a first signal corresponding to a first time unit and a second signal corresponding to a second time unit after the first time unit wherein the decoder comprises: a first comparator outputting a comparison result according to the signal level of the first signal and a second comparator outputting a comparison result according to the signal level of the second signal; an R_1_1 th transistor connected to an output terminal of the first comparator and an R_1_2 th transistor connected to an output terminal of the second comparator; and a first EN buffer connected between an output terminal of the first comparator and a gate of the R_1_2 th transistor, and a second EN buffer connected between an output terminal of the second comparator and a gate of the R_1_1 th transistor. 2 signal has three signal levels, wherein the three signal levels include a high level, a middle level and a low level; of the high level or the low level, the second comparator outputs the second signal as 1 or 0, and when the second signal has the middle level, the first EN buffer and the second Based on the EN buffer being turned on, the second comparator is a receiver that outputs a comparison result of the second signal based on a comparison result of the first comparator.

For example, when the second signal has the middle level, the second comparator outputs the second signal as 0 when the comparison result of the first comparator is 1, and the comparison result of the first comparator is 1. In case of 0, the second signal may be output as 1.

For example, the middle level may correspond to the ground level.

For example, each of the first comparator and the second comparator may include: a first symmetric stage receiving the first signal and the second signal and outputting a comparison result for the first signal and the second signal; 2 symmetrical ends; and an R_2_1 transistor having one end connected to the output terminal of the first symmetric terminal and controlled by the comparison result of the first signal, and one end connected to the output terminal of the second symmetric terminal, and comparing the first signal. A R_2_2 th transistor controlled by the complementary result of the result may be included.

In another aspect of the present disclosure, an encoder for encoding input data into a first signal corresponding to a first time unit and a second signal corresponding to a second time unit after the first time unit; and a decoder receiving and decoding the first signal and the second signal, wherein the second signal has three signal levels, wherein the three signal levels are a high level and a middle level. ) level and low level -; of the high level or the low level, the decoder decodes the second signal as 1 or 0, and when the second signal has the middle level, the decoder determines the decoding result of the first signal It is a transceiver that decodes the second signal based on.

For example, the input data includes first to third serial data consecutive on a time resource, the encoder compares the first serial data and the second serial data to encode the first signal, , The second signal may be encoded by comparing the second serial data and the third serial data.

For example, the encoder encodes the first signal to have the high level or the low level when the first serial data and the second serial data are the same, and the first serial data and the second serial data is different, the first signal is encoded to have the intermediate level, and when the second serial data and the third serial data are the same, the first signal is encoded to have the high level or the low level, and the second When the serial data and the third serial data are different, the first signal may be encoded to have the intermediate level.

The various examples of the present disclosure described above are only some of the preferred examples of the present disclosure, and various examples in which the technical features of the various examples of the present disclosure are reflected are detailed descriptions to be detailed below by those of ordinary skill in the art. It can be derived and understood based on.

According to various examples of the present disclosure, the following effects are obtained.

According to various examples of the present disclosure, a duo binary receiver and transceiver using a ground signal technique capable of reducing power consumption, signal noise, and hardware cost may be provided.

Also, compatibility with existing two-level signals can be increased.

In addition, in the conventional duo-binary signaling technology based on the reference voltage, a decoder included to convert a unary code into a binary signal is not required.

Effects obtainable from various examples of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned are clearly derived to those skilled in the art based on the detailed description below and can be understood.

The accompanying drawings are provided to aid understanding of various examples of the present disclosure, and provide various examples of the present disclosure together with detailed descriptions. However, technical features of various examples of the present disclosure are not limited to specific drawings, and features disclosed in each drawing may be combined with each other to form a new embodiment. Reference numerals in each figure mean structural elements.
1 is a circuit diagram of an exemplary high-speed single-channel I/O circuit.
2 is a circuit diagram of an exemplary ground signal based circuit.
3 is intended to illustrate an exemplary duo-binary signaling circuit.
4 is a circuit diagram of a transmitter according to an example of the present disclosure.
5 is serial data according to an example of the present disclosure.
6A and 6B are circuit diagrams of an encoder according to an example of the present disclosure.
7 is a circuit diagram of a driver according to an example of the present disclosure.
8 is a circuit diagram of a receiver according to an example of the present disclosure.
9 is a circuit diagram of a decoder according to an example of the present disclosure.
10 is a circuit diagram of a first comparator and a second comparator according to an example of the present disclosure.
11 is a circuit diagram of a first EN buffer and a second EN buffer according to an example of the present disclosure.
12 is for explaining an operation of a decoder according to an example of the present disclosure.
13 is a circuit diagram of a transceiver according to an example of the present disclosure.

Hereinafter, implementations according to the present invention will be described in detail with reference to the accompanying drawings. The detailed description set forth below in conjunction with the accompanying drawings is intended to describe exemplary implementations of the invention, and is not intended to represent the only implementations in which the invention may be practiced. The following detailed description includes specific details for the purpose of providing a thorough understanding of the present invention. However, one skilled in the art recognizes that the present disclosure may be practiced without these specific details.

In some cases, in order to avoid obscuring the concept of the present disclosure, well-known structures and devices may be omitted or may be shown in block diagram form centering on core functions of each structure and device. In addition, the same reference numerals are used to describe like elements throughout the present disclosure.

Since various examples according to the concept of the present invention can be made with various changes and have various forms, various examples will be illustrated in the drawings and described in detail in the present disclosure. However, this is not intended to limit the various examples according to the concept of the present invention to specific disclosed forms, and includes modifications, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first or second may be used to describe various components, but the components should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another component, for example, without departing from the scope of rights according to the concept of the present invention, a first component may be named a second component, Similarly, the second component may also be referred to as the first component.

It is understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, but other elements may exist in the middle. It should be. On the other hand, when an element is referred to as “directly connected” or “directly connected” to another element, it should be understood that no other element exists in the middle. Expressions describing the relationship between components, such as "between" and "directly between" or "directly adjacent to" should be interpreted similarly.

In various examples of this disclosure, “/” and “,” should be interpreted as indicating “and/or”. For example, “A/B” may mean “A and/or B”. Furthermore, “A, B” may mean “A and/or B”. Furthermore, “A/B/C” may mean “at least one of A, B and/or C”. Furthermore, “A, B, C” may mean “at least one of A, B and/or C”.

In various examples of this disclosure, “or” should be interpreted as indicating “and/or”. For example, "A or B" can include "only A", "only B", and/or "both A and B". In other words, "or" should be interpreted as indicating "in addition or alternatively."

The terms used in this disclosure are only used to describe specific various examples, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this disclosure, the terms "comprise" or "having" are intended to designate that the described feature, number, step, operation, component, part, or combination thereof exists, but one or more other features or numbers, It should be understood that the presence or addition of steps, operations, components, parts, or combinations thereof is not precluded.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in the present disclosure, it should not be interpreted in an ideal or excessively formal meaning. don't Hereinafter, various examples of the present disclosure will be described in detail with reference to the accompanying drawings.

Various examples of the present disclosure relate to a transceiver combining the above-described ground signal transmission-based transmission technology and duo-binary signaling. A transceiver includes a transmitter and a receiver.

transmitter

4 is a block diagram of a transmitter according to an example of the present disclosure.

Referring to FIG. 4 , a transmitter 100 according to an example of the present disclosure includes a signal generator 110, a serializer 120, an encoder 130, and a driver 140.

The signal generator 110 generates input data of the transceiver 10 according to various examples of the present disclosure. The signal generator 110 may generate input data based on, for example, a pseudo-random pattern. The input data may be, for example, n pieces of parallel data (where n is a natural number).

Alternatively, the signal generator 110 may generate test data for performance testing of the transceiver 10 . Like the input data, the test data may be generated based on a pseudo-random pattern, and may be n pieces of parallel data.

The serializer 120 serializes the input data generated from the signal generator 110 into serial data. As converted to serial data, input data can be transmitted over a single channel. For example, serializer 120 can serialize n pieces of parallel data into two pieces of serial data. The two serial data may include EVEN data and ODD data.

In the present disclosure, EVEN data and ODD data may each correspond to 1 unit interval (UI). UI is the minimum pulse width of meaningful data in a signal. Accordingly, EVEN data and ODD data are data transmitted during a total of 2 UIs. In this disclosure, 1 UI may be referred to as a unit of time.

Encoder 130 duo binary encodes the serial data. The encoding signal in which the serial data is encoded includes a first up-down signal and a second up-down signal.

The driver 140 transmits the encoded signal to the receiver 200 through a single channel. A signal transmitted through the driver 140 may be referred to as a transmission signal.

Hereinafter, the encoder 130 and the driver 140 will be described in detail with reference to FIGS. 5 to 7 .

5 is serial data according to an example of the present disclosure, and FIGS. 6A and 6B are circuit diagrams of an encoder according to an example of the present disclosure.

Referring to FIG. 5 , serial data input to the encoder 130 includes EVEN data and ODD data as described above. In this case, if ODD data transmitted within one cycle (or current cycle) is ODD ₀ and EVEN data is EVEN ₀ , EVEN data transmitted within a previous cycle may be referred to as EVEN _-1 . Here, one period may include 2 UIs. In other words, EVEN _-1 is the data of the previous time unit of ODD ₀ .

Referring to FIGS. 6A and 6B , an encoder 130 to which serial data as shown in FIG. 2 is applied may include a first encoder 131 and a second encoder 132 . The first encoder 131 and the second encoder 132 perform duo-binary encoding on three serial data (EVEN _-1 , ODD ₀ , EVEN ₀ ) based on the following operation.

As shown in FIG. 6A, the first encoder 131 compares EVEN _-1 of the previous period with ODD ₀ of the current period, that is, data of different time units to generate first up-down signals, UP _ODD and DN _ODD . For example, the first encoder 131 compares EVEN _-1 , which is a NOT signal of EVEN- ₁ , with ODD ₀ to generate UP _ODD , and compares EVEN- ₁ with ODDB ₀ , which is a NOT signal of ODD ₀ , to generate DN _ODD generate At this time, EVEN _-1 and EVENB _-1 may be applied to the EN buffer 133 and output as high, low, or high impedance.

As shown in FIG. 6B, the second encoder 132 compares ODD ₀ and EVEN ₀ of the current period, that is, data of different time units to generate second up-down signals, UP _EVEN and DN _EVEN . For example, the second encoder 132 compares ODDB ₀ , which is a NOT signal of ODD ₀ , with EVEN ₀ to generate UP _EVEN , and compares ODD ₀ with EVENB ₀ , which is a NOT signal of EVEN ₀ , to generate DN _EVEN . . At this time, ODDB ₀ and ODD ₀ may be applied to the EN buffer 133 and output as high, low, or high impedance.

7 is a circuit diagram of a driver according to an example of the present disclosure.

Referring to FIG. 7 , the driver 140 includes a T_1_1 th transistor 141 to a T_1_6 th transistor 146 and a capacitor 147 . When the T_1_1 th transistor 141 and the T_1_6 th transistor 146 are turned on, the driver 140 pre-charges the capacitor 147 . Precharging may be performed when the clock signal is 1.

When the T_1_2 th transistor 142 and the T_1_5 th transistor 145 are turned on, the driver 140 transmits a high level signal. That is, when UP _ODD or UP _EVEN applied to the T_1_2 th transistor 142 and the T_1_5 th transistor 145 is 1, the driver 140 transmits a high level signal.

When all transistors are turned off, the driver 140 transmits a middle level signal corresponding to the ground level. That is, when both the first up-down signal and the second up-down signal are 0, the driver 140 transmits the middle level signal.

When the T_1_3 th transistor 143 and the T_1_4 th transistor 144 are turned on, the driver 140 transmits a low level signal. Signal transmission may be performed when the clock signal is zero. That is, when DN _ODD or DN _EVEN applied to the T_1_3 th transistor 143 and the T_1_4 th transistor 144 is 1, the driver 140 transmits a low level signal.

Although not shown, the above-described driver 140 may include two drivers 140, and a first up-down signal and a second up-down signal are applied to each driver 140, and transmission accordingly. signals can be transmitted separately. Here, the first up-down signal and the transmission signal corresponding to the first time unit may be referred to as a first signal, and the second up-down signal and the transmission signal corresponding to the second time unit may be referred to as a second signal. it could be done

The transmitter 100 according to various examples of the present disclosure described above may perform duo-binary encoding on input data without a separate reference voltage.

receiving set

8 is a circuit diagram of a receiver according to an example of the present disclosure.

Referring to FIG. 8 , a receiver 200 according to an example of the present disclosure includes an S2D amplifier 210, an equalizer 220, a decoder 230, and a converter 240.

The S2D amplifier 210 converts a transmission signal (ie, a first signal and a second signal) passing through a single channel into a differential signal. In the memory interface, a single channel is used to increase pin efficiency. When restoring a signal that has passed through a single channel, the transmission signal is converted into a differential signal to be resistant to supply voltage noise. For example, the S2D amplifier 210 converts a single alternating current (AC) signal into a differential signal based on a direct current (DC) signal having an intermediate level.

The equalizer 220 compensates for signal attenuation due to transmission and reception channels. A transmit/receive channel generally has a low pass filter (LPF) characteristic consisting of a resistor, an inductor, and a capacitor, so Inter symbol Interference (ISI) becomes severe in a high frequency domain. Therefore, the equalizer 220 reduces signal attenuation due to ISI compensate For example, the equalizer 220 may be a continuous time linear equalizer (CTLE) that compensates for signal attenuation due to a channel by lowering a signal in a low frequency domain and amplifying a signal in a high frequency domain.

The transmission signal is converted into differential signals INP ₀ and INN ₀ through the above-described S2D amplifier 210 and equalizer 220 . The differential signal may include a first differential signal corresponding to the aforementioned first signal and a second differential signal corresponding to the second signal. The differential signal is applied to decoder 230.

Decoder 230 decodes the differential signal. Decoder 230 decodes the differential signal to obtain duo binary data.

The converter 240 converts the decoded data from a return to zero (RZ) method to a non-return to zero (NRZ) method to obtain final original data, that is, input data.

Hereinafter, the decoder 230 according to an example of the present disclosure will be described in detail with reference to FIGS. 9 to 12 .

9 is a circuit diagram of a decoder according to an example of the present disclosure.

Referring to FIG. 9 , the decoder 230 according to an example of the present disclosure includes a first comparator 231 and a second comparator 232, an R_1_1th transistor 233 and an R_1_2th transistor 234, and a first EN buffer. (235a) and a second EN buffer (235b).

The first comparator 231 may be referred to as an ODD comparator, and the second comparator 232 may be referred to as an EVEN comparator.

The first comparator 231 receives the first differential signal, compares the first differential signal with each other, and outputs output data COMP _ODD as a result of the comparison. The second comparator 232 receives the second differential signal, compares the second differential signal with each other, and outputs output data COMP _EVEN as a result of the comparison.

Output terminals of the first EN buffer 235a and the second EN buffer 235b are connected to gates of the R_1_1th transistor 233 and the R_1_2th transistor 234, respectively. That is, the R_1_1th transistor 233 and the R_1_2th transistor 234 are turned on or off by the output data of the first EN buffer 235a and the second EN buffer 235b.

For example, when the EN signal is 0, that is, when the first EN buffer 235a and the second EN buffer 235b are turned off, both the R_1_1th transistor 233 and the R_1_2th transistor 234 are turned off. It is turned off, and thus data of two levels (high level and low level) is decoded.

For example, when the EN signal is 1, that is, when the first EN buffer 235a and the second EN buffer 235b are turned on, both the R_1_1th transistor 233 and the R_1_2th transistor 234 are turned on. It is turned on, and thus data of three levels (high level, middle level and low level) is decoded. That is, middle level data can be decoded when the first EN buffer 235a and the second EN buffer 235b are turned on.

The first EN buffer 235a is connected between the output terminal of the first comparator 231 and the gate of the R_1_2 th transistor 234, and the second EN buffer 235b is connected between the output terminal of the second comparator 232 and the R_1_1 th transistor. It is connected between the gates of (233).

10 is a circuit diagram of a first comparator and a second comparator according to an example of the present disclosure.

Referring to FIG. 10, the first comparator 231 and the second comparator 232 have a first symmetrical stage 236, a second symmetrical stage 237, and R_2_1 corresponding to differential signals INP ₀ and INN ₀ , respectively. transistor 238 and the R_2_2th transistor 239.

Each of the first symmetrical stage 236 and the second symmetrical stage 237 includes a plurality of transistors controlled according to a differential signal or a clock signal, and the first symmetrical stage 236 generates an output signal OUTP ₀ for INP ₀ , and the second symmetry stage 237 outputs OUTN ₀ , which is an output signal for INN ₀ .

Each of the R_2_1th transistor 238 and the R_2_2th transistor 239 is turned on or off by D _PREV , which is a signal of the previous time unit, and a NOT signal of the previous time unit signal, that is, DB _PREV , which is a complementary signal. According to D _PREV and DB _PREV , one of the R_2_1 th transistor 238 and the R_2_2 th transistor 239 is turned on, so that whether the output signal is output as 1 or 0 when the differential signal is at the middle level may be determined complementaryly.

The output data of the first comparator 231 and the second comparator 232 have a result value according to the signal level of the differential signal. For example, when the signal level of the differential signal is a high level or a low level, the output signal is 1 or 0 as a result value corresponding to each level. In other words, when the signal level of the differential signal is high or low, data of the current time unit is output as it is.

For example, when the signal level of the differential signal is a middle level, the output signal has a result value opposite to data of a previous time unit based on the current time unit. For example, when the data of the previous time unit is 0, the output signal is 1, and when the data of the previous time unit is 1, the output signal is 0.

11 is a circuit diagram of a first EN buffer and a second EN buffer according to an example of the present disclosure.

Referring to FIG. 11 , the first EN buffer 235a and the second EN buffer 235b according to an example of the present disclosure include a plurality of transistors driven by an EN signal, and when the EN signal is 1, an input signal A value equal to (1 or 0) is output, and when the EN signal is 0, high impedance is output.

12 is for explaining an operation of a decoder according to an example of the present disclosure.

Referring to FIG. 12 , the decoder 230 samples a signal corresponding to EVEN data based on a clock signal in a differential signal (CTLE output). The decoder 230 outputs output data of the D0 section for the signal sampled through the second comparator 232 . The output data of the D0 section, that is, the output data of the current time unit, is reflected after a predetermined time delay through the second EN buffer 235b when the first comparator 231 outputs the output data of the D1 section. That is, in the decoder 230 according to the present disclosure, data from one time unit ago is reflected in determining current data.

The receiver 200 according to various examples of the present disclosure described above determines middle-level data opposite to data one time unit ago, since data from one time unit ago may be reflected in determining current data. Therefore, when middle level data is input to the comparator, the problem of slow data determination and random determination can be solved.

In addition, the receiver 200 according to various examples of the present disclosure described above may be provided with only two comparators and separate reference voltages, unlike the conventional duo binary signaling that requires four comparators and two reference voltages as shown in FIG. Decoding is possible without the need for this, reducing power consumption and hardware cost.

transceiver

13 is a circuit diagram of a transceiver according to an example of the present disclosure.

Referring to FIG. 13 , a transceiver 10 according to an example of the present disclosure includes the above-described transmitter 100 and receiver 200 of the present disclosure. For example, the transmitter 100 included in the transceiver 10 encodes input data into a first signal corresponding to a first time unit and a second signal corresponding to a second time unit after the first time unit. (130). For example, the receiver 200 included in the transceiver 10 may include a decoder 230 that receives and decodes the first signal and the second signal.

In this case, the decoder 230 may decode the second signal as 1 or 0 when the second signal has a high level or a low level among the three signal levels. Alternatively, when the second signal has a middle level, the decoder 230 may decode the second signal based on a decoding result of the first signal.

According to the transmitter 100, receiver 200, and transceiver 10 according to various examples of the present disclosure described above, duo-binary encoding and decoding of input data is possible without a separate reference voltage, so power consumption and hardware cost can be reduced. .

In particular, since data from one time unit ago can be reflected in determining current data during decoding, middle-level data is determined opposite to data from one time unit ago. Therefore, when middle level data is input to the comparator, the problem of slow data determination and random determination can be solved.

Since the examples of the proposed schemes in the above description may also be included as one of the implementation methods of the present disclosure, it is obvious that they can be regarded as a kind of proposed schemes. In addition, the above-described proposed schemes may be implemented independently, but may also be implemented in a combination (or merged) form of some proposed schemes.

Examples of the present disclosure disclosed as described above are provided to enable those skilled in the art to implement and practice the present disclosure. Although the above has been described with reference to examples of the present disclosure, a person skilled in the art may variously modify and change the examples of the present disclosure. Thus, the present disclosure is not intended to be limited to the examples set forth herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

10: transceiver
100: transmitter 200: receiver
110: signal generator 120: serializer
130: encoder 140: driver
210: S2D amplifier 220: equalizer
230: decoder 240: converter

Claims (10)

Applying the first signal and the second signal from an encoder that encodes input data into a first signal corresponding to a first time unit and a second signal corresponding to a second time unit after the first time unit In a receiver including a decoder for receiving and decoding,
the second signal has three signal levels, wherein the three signal levels include a high level, a middle level and a low level; of the high level or the low level, the decoder decodes the second signal into 1 or 0;
When the second signal has the middle level, the decoder decodes the second signal based on a decoding result of the first signal;
The input data includes first to third serial data consecutive on time resources,
The first signal is a signal encoded from comparing the first serial data and the second serial data, and the second signal is a signal encoded from comparing the second serial data and the third serial data. ,
receiving set.
According to claim 1,
When the second signal has the middle level, the decoder decodes the second signal as 0 when the decoding result of the first signal is 1, and the second signal is decoded as 0 when the decoding result of the first signal is 0. decoding the signal to 1,
receiving set.
According to claim 1,
The middle level corresponds to the ground level,
receiving set.
Applying the first signal and the second signal from an encoder that encodes input data into a first signal corresponding to a first time unit and a second signal corresponding to a second time unit after the first time unit In a receiver including a decoder for receiving and decoding,
The decoder is:
a first comparator outputting a comparison result according to the signal level of the first signal and a second comparator outputting a comparison result according to the signal level of the second signal;
an R_1_1 th transistor connected to an output terminal of the first comparator and an R_1_2 th transistor connected to an output terminal of the second comparator; and
A first EN buffer connected between an output terminal of the first comparator and a gate of the R_1_2 th transistor and a second EN buffer connected between an output terminal of the second comparator and a gate of the R_1_1 th transistor,
the second signal has three signal levels, wherein the three signal levels include a high level, a middle level and a low level; of the high level or the low level, the second comparator outputs the second signal as 1 or 0,
When the second signal has the middle level, the second comparator determines the second signal based on a comparison result of the first comparator based on the fact that the first EN buffer and the second EN buffer are turned on. outputs the comparison result of
The input data includes first to third serial data consecutive on time resources,
The first signal is a signal encoded from comparing the first serial data and the second serial data, and the second signal is a signal encoded from comparing the second serial data and the third serial data. ,
receiving set.
According to claim 4,
When the second signal has the middle level, the second comparator outputs the second signal as 0 when the comparison result of the first comparator is 1, and when the comparison result of the first comparator is 0, the second comparator outputs the second signal as 0. Outputting the second signal as 1,
receiving set.
According to claim 4,
The middle level corresponds to the ground level,
receiving set.
According to claim 4,
Each of the first comparator and the second comparator:
a first symmetric end and a second symmetric end receiving the first signal and the second signal and outputting a comparison result of the first signal and the second signal; and
The R_2_1 transistor having one end connected to the output terminal of the first symmetrical terminal and controlled by the comparison result of the first signal, and one end connected to the output terminal of the second symmetrical terminal, and the comparison result of the first signal Including the R_2_2th transistor controlled by the complementary result of
receiving set.
an encoder for encoding input data into a first signal corresponding to a first time unit and a second signal corresponding to a second time unit after the first time unit; and
A decoder for receiving and decoding the first signal and the second signal;
the second signal has three signal levels, wherein the three signal levels include a high level, a middle level and a low level; of the high level or the low level, the decoder decodes the second signal into 1 or 0;
When the second signal has the middle level, the decoder decodes the second signal based on a decoding result of the first signal;
The input data includes first to third serial data consecutive on time resources,
The encoder compares the first serial data and the second serial data to encode the first signal, and compares the second serial data and the third serial data to encode the second signal.
transceiver.
delete According to claim 8,
The encoder,
When the first serial data and the second serial data are the same, the first signal is encoded to have the high level or the low level, and when the first serial data and the second serial data are different, the first signal encoding to have the middle level;
When the second serial data and the third serial data are the same, the first signal is encoded to have the high level or the low level, and when the second serial data and the third serial data are different, the first signal Encoding to have the middle level,
transceiver.

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