KR20230061686A - Receiver, operation method thereof, and transmitting and receiving system including thereof - Google Patents

Abstract

A receiver, an operation method thereof, and a transmission/reception system including the same are disclosed. A receiver according to an embodiment of the present invention includes a signal processing unit for generating a compensation signal by signal processing a transmission signal encoded by a first encoding method; and a decoding unit generating a received signal by applying a sampling scheme corresponding to a second encoding scheme different from the first encoding scheme to the compensation signal in synchronization with a clock signal.

Description

Receiver, method of operation thereof, and transmission/reception system including the same

The present application relates to a receiver, an operation method thereof, and a transmission/reception system including the same.

In an input/output circuit such as a memory interface, an NRZ signal method using a 0 state without charge and a 1 state charged with charge is used for signal transmission.

At this time, a noise margin in the receiver may be reduced due to noise, attenuation or distortion of the signal. Power consumption may increase due to the structure and operation of a transmitter or receiver of a transmission/reception system for compensating for noise, attenuation, or distortion of a signal. An increase in power consumption may reduce battery life and cause heat generation.

This phenomenon can be more problematic in high-bandwidth memory interfaces.

The present invention is to provide a receiver capable of low-power operation, an operating method thereof, and a transmission/reception system including the same.

A receiver according to an embodiment of the present invention includes a signal processing unit for generating a compensation signal by signal processing a transmission signal encoded by a first encoding method; and a decoding unit generating a received signal by applying a sampling scheme corresponding to a second encoding scheme different from the first encoding scheme to the compensation signal in synchronization with a clock signal.

The first encoding method may be a non-return to zero (NRZ) encoding method, and the second encoding method may be a duo-binary encoding method.

The signal processing unit may include an equalizer equalizing the transmission signal; and an amplifier configured to amplify the signal equalized by the equalizer and output the amplified signal as the compensation signal.

The decoding unit may generate the received signal by sampling the transmission signal at a zero crossing point on an eye diagram of the compensation signal.

The clock signal may have a clock period equal to or less than 1/2 of the transmission rate of the transmission signal.

The decoding unit may include: a first comparison unit outputting a first result value or a second result value when the compensation signal is greater than a first reference value or less than a second reference value at a first edge of the clock signal; When the compensation signal is smaller than the first reference value and greater than the second reference value at the first edge of the clock signal, based on an integral value obtained by integrating the compensation signal for the first period until the first edge of the clock signal , a second comparison unit outputting a third result value or a fourth result value; and a decoder (146decoder) for determining the received signal corresponding to the first to fourth result values.

The second comparator may include: a differential integrator integrating a compensation signal for a first period up to a first edge of the clock signal and outputting the integral value; and a second differential comparator outputting one of the third result value and the fourth result value based on the integral value.

The differential integrator includes a first circuit and a second circuit, and the first circuit is a first type in which gates are connected to each other, gated by the clock signal, and a voltage is applied to one end connected to each other ( 11th and 21st transistors of type); a 31st transistor of the first type having a gate connected to the 11th and 21st transistors and having both ends connected to the other ends of the 11th and 21st transistors; 11th and 21st capacitors having one ends connected to both ends of the 31st transistor, respectively; 41st and 51st transistors of the first type having gates connected to each other, gated by an inverted signal of the clock signal, and having one end connected to both ends of the 31st transistor; and a 61st transistor of a second type gated by the compensation signal and having one end connected to the 41st transistor, wherein the second circuit has gates connected to each other and is gated by an inverted signal of the clock signal. , twelfth and twelfth transistors of the first type to which a voltage is applied to one end connected to each other; a 32nd transistor of the first type having a gate connected to the twelfth and 22nd transistors and having both ends connected to the other ends of the twelfth and 22nd transistors; twelfth and twelfth capacitors having one ends connected to both ends of the 32nd transistor, respectively; Gates are connected to each other to be gated by the clock signal, one end is connected to both ends of the 32nd transistor, and the other end is connected to the other end of the corresponding transistor among the 41st and 51st transistors. 42nd and 52nd transistors of one type; and a 62nd transistor of the second type gated by an inversion signal of the compensation signal and having one end connected to the other end of the 52nd transistor.

The integrator may further include 71st and 72nd transistors of the second type connected in parallel with the 61st and 62nd transistors to adjust voltages across the 31st and 32nd transistors, respectively. there is.

The differential integrator may be provided with at least two different weights applied according to a compensation signal before the first edge of the clock signal, respectively.

The second differential comparator may apply a different weight to the integral value according to a compensation signal before the first edge of the clock signal.

The integral value may be a value to which a different weight is applied according to a compensation signal before the first edge of the clock signal.

The decoding unit may perform sampling corresponding to the first encoding method on a transmission signal encoded by the first encoding method in response to a mode signal.

The receiver may perform a high-speed memory interface.

A transmission/reception system according to an embodiment of the present invention includes a signal processor generating a compensation signal by signal processing a transmission signal encoded by a first encoding scheme, and a second encoding scheme for the compensation signal synchronized with a clock signal. A receiver including a decoding unit for generating a received signal by applying a sampling method corresponding to; and a transmitter outputting the transmission signal encoded in the first method.

A receiver according to an embodiment of the present invention includes a signal processing unit for signal processing a transmission signal to generate a compensation signal; and a decoding unit that is synchronized with a clock signal having a clock period equal to or less than 1/2 of the transmission rate of the transmission signal and generates a received signal by sampling the compensation signal. , a first comparator outputting a first result value or a second result value when the compensation signal is greater than a first reference value or less than a second reference value at a first edge of the clock signal; When the compensation signal is smaller than the first reference value and greater than the second reference value at the first edge of the clock signal, based on an integral value obtained by integrating the compensation signal for the first period until the first edge of the clock signal , a second comparison unit outputting a third result value or a fourth result value; and a decoder (146decoder) for determining the received signal corresponding to the first to fourth result values.

A method of operating a receiver according to an embodiment of the present invention includes generating a compensation signal by signal processing a transmission signal encoded by a first encoding method; and generating a received signal by applying a sampling method corresponding to a second encoding method to the compensation signal in synchronization with a clock signal.

The generating of the received signal includes performing sampling on the transmitted signal at a zero crossing point on an eye diagram for the compensation signal in synchronization with the clock signal, and , the clock signal may have a clock period equal to or less than 1/2 of the transmission rate of the transmission signal.

The generating of the received signal may include decoding the received signal of “11” when the compensation signal is greater than or equal to a first reference value; decoding a received signal of “00” when the compensation signal is equal to or less than a second reference value; When the compensation signal is smaller than the first reference value and greater than the second reference value, "10" or "10" based on the integral value obtained by integrating the compensation signal for the first period up to the first edge of the clock signal. Decoding into a received signal of; may include.

According to a receiver according to an embodiment of the present invention, a method for operating the same, and a transmission/reception system including the same, the receiver can accurately output a received signal even if the transmitter does not perform an additional encoding operation, thereby reducing power consumption.

According to a receiver according to an embodiment of the present invention, an operating method thereof, and a transmission/reception system including the same, the receiver can accurately output a received signal while operating in synchronization with a clock signal of 1/2 or less of the transmission rate of the transmission signal, Power consumption can be reduced.

1 is a diagram showing a receiver according to an embodiment of the present invention.
2 is a diagram illustrating a method of operating a receiver according to an embodiment of the present invention.
3 is a diagram showing a signal processing unit according to an embodiment of the present invention.
4 is a diagram for explaining NRZ and duo binary encoding schemes.
5 to 7 are diagrams for explaining a decoding unit and its operation according to an embodiment of the present invention, respectively.
8 is a diagram showing a decoding unit in more detail according to an embodiment of the present invention.
9 is a diagram illustrating a differential integrator according to an embodiment of the present invention.
10 to 11 and 12 are views for explaining the operation of a differential integrator according to an embodiment of the present invention.
12 is a diagram illustrating a decoding unit according to an embodiment of the present invention.
13 is a diagram showing a transmission/reception system according to an embodiment of the present invention.

Hereinafter, embodiments of the present application will be described with reference to specific embodiments and accompanying drawings. However, the embodiments of the present application may be modified in many different forms, and the scope of the present application is not limited to the embodiments described below. In addition, the embodiments of the present application are provided to more completely explain the present invention to those skilled in the art. Therefore, the shape and size of elements in the drawings may be exaggerated for clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

In addition, in order to clearly describe the present application in the drawings, parts irrelevant to the description are omitted, and the thickness is enlarged to clearly express various layers and regions, and components having the same function within the scope of the same concept are referred to as the same reference. Explain using symbols. Furthermore, throughout the specification, when a certain component is said to "include", it means that it may further include other components without excluding other components unless otherwise stated.

1 is a diagram showing a receiver according to an embodiment of the present invention, and FIG. 2 is a diagram showing a method of operating a receiver according to an embodiment of the present invention.

1 and 2, the receiver 100 according to an embodiment of the present invention includes a signal processing unit 120) and a decoding unit 180 to transmit a transmission signal TX even with low power. A corresponding accurate received signal RX may be output. The method 200 of operating a receiver according to an embodiment of the present invention includes generating a compensation signal CX (S220) and generating a received signal RX (S240), and transmits a signal (S240) even with low power. TX) can output an accurate received signal (RX).

The receiver 100 and the method of operating the receiver 200 according to an embodiment of the present invention can perform a high-speed memory interface required to realize a System on Chip (SoC) memory bandwidth of 500 GB/s or more, respectively. can

The receiver 100 according to an embodiment of the present invention may operate in the method 200 for operating a receiver according to an embodiment of the present invention. Also, the method 200 for operating a receiver according to an embodiment of the present invention may be executed in the receiver 100 according to an embodiment of the present invention. However, it is not limited thereto. The receiver 100 according to the embodiment of the present invention may operate in a method different from the method 200 of operating the receiver according to the embodiment of the present invention. In addition, the method 200 of operating a receiver according to an embodiment of the present invention may be executed in a device or system different from the receiver 100 according to an embodiment of the present invention.

However, in the following, for convenience of description, the receiver 100 according to the embodiment of the present invention operates in the operation method 200 of the receiver according to the embodiment of the present invention, and the receiver 100 according to the embodiment of the present invention Only an example in which the operation method 200 is executed in the receiver 100 according to an embodiment of the present invention will be described.

Hereinafter, each module of the non-destructive diagnostic system 100 according to an embodiment of the present invention and each step of the operating method 200 of a receiver according to an embodiment of the present invention will be described in more detail.

Continuing to refer to FIGS. 1 and 2 , the signal processing unit 120 according to the embodiment of the present invention generates a compensation signal CX by signal processing the transmission signal TX encoded by the first encoding method. Do (S220).

3 is a diagram showing a signal processing unit according to an embodiment of the present invention.

Referring to FIG. 3 , the signal processing unit 120 according to an embodiment of the present invention may include an equalizer CTLE and an amplifier AMP. The equalizer CTLE equalizes the input transmission signal TX to reduce the effect of attenuation or distortion caused during transmission through the channel CH. The amplifier AMP amplifies the signals equalized by the equalizer CTLE and outputs them as compensation signals VP and VN, thereby making subsequent decoding operations accurate and easy.

At this time, the compensation signal (voltage level of) for the transmission signal (TX)_P) applied to the non-inverting terminal (not shown) of the receiver 100 of FIG. 1 is VP, and applied to the inverting terminal (not shown) The compensation signal (voltage level of) for the transmission signal (TX)_N) is referred to as VN. Below, the same.

The signal processor 120 may further include an analog front end (AFE) and the like in addition to the equalizer CTLE and the amplifier AMP.

Referring back to FIGS. 1 and 2 , the decoding unit 140 applies a sampling method corresponding to the second encoding method to the compensation signal CX in synchronization with the clock signal CLK, and thereby receives the received signal RX. ) to create

If the first encoding method is a non-return to zero (NRZ) encoding method, the second encoding method may be a duo-binary encoding method. The first encoding method and/or the second encoding method may be another encoding method. However, in the following description, for convenience of description, unless otherwise specified, the first encoding method is NRZ and the second encoding method is duo binary.

4 is a diagram for explaining NRZ and duo binary encoding schemes.

First, referring to (a) of FIG. 4, the NRZ encoding method refers to a method of converting binary values of 1 and 0 into a positive voltage (+1) and a negative voltage (-1), respectively. The transmitter outputs the NRZ-encoded transmission signal (TX), and the receiver receives it, performs a decoding operation corresponding to NRZ encoding, and outputs the received signal (RX). At this time, as described above, as attenuation or distortion is caused in the process of transmitting the transmission signal TX through the channel, the receiver performs compensation using an equalizer (not shown) or the like.

Next, referring to (b) of FIG. 4, the duo-binary encoding method precodes the NRZ-encoded signal In by reflecting the channel loss, so that three binary values of 1 and 0 (or above) refers to the method of converting to a level. To this end, the transmitter further includes a precoder for precoding the NRZ-encoded signal In. The precoded signal (Out) output from the transmitter is input to the receiver as a transmission signal (TX) converted to three (or more) levels in the process of being transmitted through a channel.

According to a receiver according to an embodiment of the present invention, an operating method thereof, and a system including the same, it is possible to implement both the advantages of the NRZ conversion scheme and the duo-binary conversion scheme.

Hereinafter, a decoding unit and an operating method thereof according to an embodiment of the present invention capable of implementing the advantages of both the NRZ conversion method and the duo-binary conversion method will be described in detail.

5 to 7 are diagrams for explaining a decoding unit and its operation according to an embodiment of the present invention, respectively.

5 to 7 , the decoding unit 140 according to an embodiment of the present invention may include a first comparison unit 142, a second comparison unit 144, and decoders 146 decoder and 146.

The first comparator 142 generates a first result value CVAL1 when the compensation signal CX is greater than the first reference value VH or less than the second reference value VL at the first edge of the clock signal CLK. Alternatively, the second result value CVAL2 may be output. When the non-inverted compensation signal VP is greater than the first reference value VH, the first result value CVAL1 corresponding to 'H', that is, 11, and the non-inverted compensation signal VP correspond to the second reference value VL ), the second result value CVAL2 corresponding to 'L', that is, 00, may be generated.

When the compensation signal CX is smaller than the first reference value VH and greater than the second reference value VL at the first edge of the clock signal CLK, the second comparator 144 outputs the first edge of the clock signal CLK. Based on an integral value obtained by integrating the compensation signal CX for the first period up to the edge, a third result value CVAL3 or a fourth result value CVAL4 may be output. When the non-inverted compensation signal (VP) is smaller than the first reference value (VH) and greater than the second reference value (VL), 'M', that is, the third result value (CVAL3) or the fourth result value (corresponding to 01 or 10) CVAL4) can be created.

The decoder 146 may determine received signals RX corresponding to the first to fourth result values CVAL4CVAL1 to CVAL4. For example, the reception signal RX is applied to the non-inverted compensation signal VP, as shown in the eye diagram of FIG. 6 for the first cycle INTEG of the clock signal CLK. It can be determined as one of 11, 00, 01 and 10.

When the first method is NRZ and the second method is duo binary, the decoding unit 140 according to an embodiment of the present invention generates a zero crossing point (not in an eye region of an eye diagram corresponding to the NRZ encoding method) The sampling operation may be performed at a zero crossing point, that is, a crossing point between the non-inverted compensation signal VP and the inverted compensation signal VN.

As shown in (a) of FIG. 6 and FIG. 7 , the decoding unit 140 according to an embodiment of the present invention has a clock period equal to or less than 1/2 of the transmission rate of the transmission signal TX (CLK). ) can be synchronized. In this case, compared to the case where the clock signal CLK has the same clock period as the transmission speed of the transmission signal TX, as shown in (b) of FIG. 7, power can be reduced by about half.

As such, according to the receiver, the method of operation thereof, and the system including the same according to an embodiment of the present invention, two values of the first reference value (VH) and the second reference value (VL) for the NRZ-encoded received transmission signal (TX) By performing a comparison operation with a reference value and a sampling operation at a zero crossing point, 3-level processing of a transmission signal in an NRZ receiver may be possible. Accordingly, only 2/3 of the bandwidth can be used in the AFE (not shown) of the receiver.

In addition, according to a receiver according to an embodiment of the present invention, an operating method thereof, and a system including the same, the clock signal (CLK) has a clock cycle of 1/2 or less of the transmission rate of the transmission signal (TX), thereby providing high-speed Low-power implementation may be possible by reducing power by clocking, which consumes the most power in a receiver circuit.

Therefore, according to the receiver according to the embodiment of the present invention, its operating method and system including the same, it is possible to implement low power in an NRZ receiver.

8 is a diagram showing a decoding unit in more detail according to an embodiment of the present invention.

6 and 8, the first comparison unit 142 of the decoding unit 140 according to the embodiment of the present invention includes a pair of first differential comparators CMP1 for the compensation signal CX, which is a differential signal. can include One of the pair of first differential comparators CMP1 operates on a non-inverted clock signal (CLK_odd in FIG. 7) of the clock signal CLK, and the other operates on an inverted clock signal (FIG. 7) of the clock signal CLK. 7 CLK_even). However, the first comparator 142 may be provided with one of various types of circuits capable of performing the above-described operation.

The first differential comparator (CMP1) outputs a first result value (CVAL1) or a second result value (CVAL2) of 'L' or 'H', and outputs the first result value (CVAL1) or the second result value (CVAL2). may be transmitted to the second comparator 144 and the decoder 146.

The second comparison unit 144 may include a differential integrator (ITG) and a second differential comparator (CMP2) to output the third result value (CVAL3) or the fourth result value (CVAL4) of 'M'.

The pair of differential integrators ITG may integrate the compensation signal CX for the first period up to the first edge of the clock signal CLK and output an integral value. The pair of second differential comparators CMP2 may output one of a third result value CVAL3 and a fourth result value CVAL4 based on the integral value output from the corresponding differential integrator ITG. 8 illustrates an example in which a pair of a differential integrator (ITG) and a second differential comparator (CMP2) are provided, but is not limited thereto, and may be provided as one of various types of circuits capable of performing the above-described operation. there is.

Hereinafter, an example of the structure and operation of a differential integrator (ITG) will be described.

9 is a diagram illustrating a differential integrator according to an embodiment of the present invention.

Referring to FIG. 9 , a differential integrator (ITG) according to an embodiment of the present invention may include a first circuit CIR1 and a second circuit CIR2.

The first circuit CIR1 includes eleventh and twenty-first transistors (of a first type) having gates connected to each other, gated by the clock signal CLK, and having voltage VDD applied to one end connected to the other. transistors T11 and T21), a gate connected to the 11th and 21st transistors T11 and T21 and both ends connected to the other end of the 11th and 21st transistors T11 and T21, the 31st transistor T31 of the first type ), the 11th and 21st capacitors (capacitors C11 and C12), one ends of which are connected to both ends of the 31st transistor T31, gates are connected to each other and gated by the inverted signal CLKB of the clock signal, and the 31st transistor The 41st and 51st transistors T41 and T51 of the first type having one end connected to both ends of T31, gated by the non-inverted compensation signal VP, and one end connected to the 41st transistor T41 A 61st transistor T61 of the second type may be included.

The second circuit CIR2 includes twelfth and twelfth transistors T12 and T22 of the first type having gates connected to each other, gated by the inverted signal CLKB of the clock signal, and having voltage VDD applied to one end connected thereto. ), a 32nd transistor T32 of the first type having a gate connected to the twelfth and 22nd transistors T12 and T22 and having both ends connected to the other ends of the twelfth and 22nd transistors T12 and T22, one end of the 32nd transistor T32 12 and 22 capacitors C12 and C22 connected to both ends of the 32 transistor T32, gates connected to each other and gated by the clock signal CLK, and one end of each of both ends of the 32 transistor T32 is connected, and the 42nd and 52nd transistors T42 and T52 of the first type to which the other ends of the corresponding transistors of the 41st and 51st transistors T41 and T51 are connected, respectively, the inverted signal of the compensation signal ( CLKBVN) and a 62nd transistor T62 of the second type having one end connected to the other end of the 52nd transistor T52.

In addition, the differential integrator (ITG) is connected in parallel with the 61st and 62nd transistors T61 and T62, respectively, to adjust the voltage across the 31st and 32nd transistors T31 and T32, of the second type. Seventy-first and seventy-second transistors T71 and T72 may be further included.

In addition, the differential integrator (ITG) may further include a bias transistor (Tbias) so that its output can be maintained at a constant voltage or current.

In this case, the first type may be a P type, and the second type may be an N type.

A more detailed description of the circuit operation of the differential integrator (ITG) of FIG. 9 will be described later.

10 to 11 are diagrams for explaining the operation of a decoding unit according to an embodiment of the present invention.

First, referring to FIGS. 6, 8, and 10, the differential integrator (ITG) generates a first reference value (VH) and a second reference value ( VL), the compensation signals VP and VN in the first period INTEG up to the first edge t1 of the clock signal CLK may be differentially integrated.

Hereinafter, the first cycle INTEG of the clock signal CLK is shown as a section from the pre-edge t0 to the first edge t1, and the resulting value 01 at the pre-edge t0 , 10, 00, and 11) is described as the previous data (PDTA), and the result value (one of 01, 10, 00, and 11) at the first edge t1 as the current data (CDTA).

The differential integrator (ITG) according to an embodiment of the present invention may operate differently according to each of the four cases of previous data (PDTA) 01, 10, 00, and 11. The previous data PDTA may be determined based on the output of the first differential comparator CMP1 or the decoder 146 .

First, the operation of the differential integrator (ITG) according to an embodiment of the present invention will be described for the case where the previous data PDTA is 01. At this time, the first circuit (CIR1) will be described as a standard. The operation of the second circuit CIR2 can be understood as an operation reversed from that of the first circuit CIR1.

Until the clock signal CLK rises at the pre-edge t0, that is, when the clock signal CLK is logic low, the eleventh to 31st transistors T11 to T31 that are PMOS transistors are all turned on. Since it is turned on and the voltage corresponding to the voltage VDD is precharged in the 11th and 21st capacitors C11 and C12 located between both ends of the 31st transistor T31 and the ground voltage, , the voltage of the integral voltages (INTN, INTP) across the 31st transistor T31 increases. The integral voltages (INTN, INTP) mean the aforementioned integral values.

After that, when the clock signal CLK rises at the free edge t0, the 11th to 31st transistors T11 to T31 are all turned off, and the 41st and 51st transistors T41 that are PMOS transistors , T51) are all turned on by the inversion signal CLKB of the clock signal, so current flows from both ends of the 31st transistor T31 to the 61st and 62nd transistors T61 and T62, which are NMOS transistors. At this time, the sixty-first and sixty-second transistors T61 and T62 are gated by the non-inverted compensation signal VP and the inverted compensation signal VN. Accordingly, the integral voltages INTN and INTP of both ends of the 31st transistor T31 decrease in response to the compensation signals VP and VN.

At this time, the voltage difference between the integral voltages INTN and INTP of both ends of the 31st transistor T31 varies according to the magnitudes of the compensation signals VP and VN after the previous data PDTA. As shown in the left graph of FIG. 10(a), when the level of the compensation signal VP after 01, which is the previous data PDTA, decreases, as shown in the left graph of FIG. 10(b), the two integrated voltages (INTN) , INTP) voltage difference also becomes small. Similarly, as shown in the right graph of FIG. 10 (a), when the magnitude of the compensation signal VP after 01, which is the previous data (PDTA), increases, as shown in the right graph of FIG. 11 (b), the two integrated voltages ( The voltage difference between INTN and INTP) also increases.

At this time, as shown in the left graph of FIG. 10(b), when the two integrated voltages (INTN and INTP) at the first edge t1 are both V1 and there is no voltage difference, the second differential comparator CMP2 accurately It may be difficult to generate the result values (CVAL3, CVAL4). This is because the second differential comparator CMP2 outputs a third result value CVAL3 or a fourth result value CVAL4 corresponding to the larger integral voltage among the two integral voltages INTN and INTP, which are integral values.

The differential integrator (ITG) according to an embodiment of the present invention may apply different weights to the integral voltages (INTN, INTP) according to the previous data (PDTA). That is, as described above, the differential integrator (ITG) according to an embodiment of the present invention further includes the 71st and 72nd transistors T71 and T72 that are NMOS connected in parallel with the 61st and 62nd transistors T61 and T62. The 71st transistor T71 is gated by the second reference value VL and the 72nd transistor T72 is gated by the second reference value VL. Therefore, as shown in the left graph of FIG. 10 (c), the integral voltage (INTN) of the two integral voltages (INTN, INTP) at the first edge (t1) decreases relatively slowly, and the other integral voltage (INTP) is relatively It decreases rapidly and has voltages of V1' and V1” at the first edge t1, respectively. At this time, the 71st and 72nd transistors T71 and T72 are provided so that the weighted voltage value (V1±V1′ or V1±V1”) becomes 1/2 of the area of the integral value in the first period (INTEG) It can be.

In this case, the second differential comparator CMP2 may output a third result value CVAL3 corresponding to the larger integral voltage INTN. The decoder 146 may output the current data CDTA of 01 corresponding to the third result value CVAL3 as the received signal RX at the first edge t1.

Since it is the operation of the same differential integrator (ITG), the right graph of FIG. 10(b) is also adjusted with the same weight. That is, as shown in the left graph of FIG. 10(c), the integral voltage (INTN) of the two integral voltages (INTN, INTP) at the first edge (t1) is another integral of V2n' increased by the weighted voltage value in V2n. The voltage INTP has a voltage of V2p' that is lowered by the weighted voltage value from V2p. In this case, the second differential comparator CMP2 may output a fourth result value CVAL4 corresponding to the larger integral voltage INTP. The decoder 146 may output the current data CDTA of 10 corresponding to the fourth result value CVAL4 as the received signal RX at the first edge t1.

Referring back to FIG. 8 , one of the pair of differential integrators (ITGs) may have the same structure as the circuit of FIG. 9 and perform the same operation as that of FIG. 10 . The differential integrator (ITG) having the same structure as the circuit of FIG. 9 and performing the same operation as that of FIG. 10 may output a meaningful result value when the previous data PDTA is 01 or 00.

On the other hand, the other of the pair of differential integrators (ITG) may have the opposite gating signals of the seventy-first and seventy-second transistors T71 and T72 of FIG. 9 as described above in relation to weighting. That is, the 71st transistor T71 may be gated by the first reference value VH, and the 72nd transistor T72 may be gated by the second reference value VL. The differential integrator (ITG) of this structure can output a meaningful result value when the previous data (PDTA) is 10 or 11.

For example, as shown in FIG. 11 , when the previous data PDTA is 11, the 71st transistor T71 is gated by the first reference value VH, and the 72nd transistor T72 is gated by the second reference value. As gated by (VL), a weight may be added in a direction in which the difference between the two integral voltages (INTN, INTP) is further reduced. However, referring to FIG. 11 (C) showing the output of the differential integrator (ITG) with weights, the integral voltage (INTP) of the two integral voltages (INTN, INTP) is larger regardless of the current data (CDTA). , the second differential comparator CMP2 may not be able to identify the current data CDTA. The second differential comparator CMP2 according to an embodiment of the present invention may apply a different weight to the integral value according to the previous data PDTA of the clock signal CLK.

For example, the second differential comparator CMP2 may include an offset circuit (not shown) connected to an input terminal, and may adjust a voltage level of one of the two integral voltages INTN and INTP. For example, the offset circuit includes an NMOS transistor connected in parallel to an input terminal to which one integral voltage (INTP) is input and turned on when the previous data PDTA is 11, and an input terminal to another integral voltage (INTN). It may include a transistor connected in parallel to and gated with a ground voltage.

Accordingly, the voltage level of one integral voltage INTP may be lowered. At this time, the other integral voltage (INTN) maintains the voltage level. Therefore, when the difference between the two integral voltages INTN and INTP, which are outputs of the differential integrator ITG (FIG. 11(c)) is small, for example, when the current data CDTA is 01, the two integral voltages ( INTN, INTP) can be reversed. That is, when the current data CDTA is 01, the output of the differential integrator ITG is integrated through the offset circuit of the second differential comparator CMP2 when the voltage level of the integral voltage INTP is greater than the other integral voltage INTN. The voltage level of the voltage INTP becomes smaller. Even when the current data CDTA is 10 due to the offset circuit, the voltage level of the integral voltage INTP will be lowered, but it does not reach the extent of inverting the relative magnitude with the other integral voltages INTP.

The second differential comparator (CMP2) generates different outputs according to the relative voltage magnitudes of the two integral voltages (INTN and INTP) voltage-adjusted through the offset circuit, and thus the decoder 146 converts the current data (CDTA) to 10 or 01. can be decoded with

As such, according to the receiver, method of operation thereof, and transmission/reception system including the same according to an embodiment of the present invention, even if the clock period of the clock signal (CLK) is only 1/2 of the transmission rate of the transmission signal (TX), the received signal is accurate. (RX) can be output, so low-power implementation may be possible.

In the description of the decoding unit 140 such as FIG. 8 above, for convenience of explanation, the result values (CVAL1 to CVAL4) between the first comparison unit 142, the second comparison unit 144, and the decoder 146 are described. ), it has been described that only some result values are transmitted, but it is not limited thereto. All result values may be transmitted to each other, and furthermore, the decoding result (received signal RX) of the decoder 146 may be transmitted to the first comparator 142 and the second comparator 144.

12 is a diagram illustrating a decoding unit according to an embodiment of the present invention.

1 and 12 , the decoding unit 140 according to the embodiment of the present invention responds to the mode signal XMOD and uses an encoding method (first encoding method) different from the encoding method (first encoding method) of the transmission signal TX. Sampling corresponding to the same encoding method, not the second encoding method), may be performed. For example, the decoding unit 140 of FIG. 12 may perform sampling in the eye region of the eye diagram on the transmission signal TX converted by the NRZ scheme. Alternatively, the decoding unit 140 of FIG. 12 may perform sampling at the zero crossing point of the eye diagram for the transmission signal TX converted in the duo-binary method.

13 is a diagram showing a transmission/reception system according to an embodiment of the present invention.

13, a transmission/reception system 1000 according to an embodiment of the present invention includes a receiver 100 and a transmitter 300. The transmitter 300 converts input data IDTA into a first encoding method to transmit a transmission signal. The receiver 100 receives the transmission signal TX, performs a sampling operation corresponding to a second encoding method different from the first encoding method, and outputs the received signal RX. The receiver 100 may be implemented with the same or similar structure as the above-mentioned receiver and perform the same or similar operation as the above-mentioned receiver.

Although representative embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications are possible to the above-described embodiments without departing from the scope of the present invention. . Therefore, the scope of the present invention should not be limited to the described embodiments and should not be defined, and should be defined by not only the claims to be described later, but also those equivalent to these claims.

Claims (20)

a signal processor generating a compensation signal by signal processing the transmission signal encoded by the first encoding method; and
A receiver comprising: a decoding unit configured to generate a received signal by applying a sampling scheme corresponding to a second encoding scheme different from the first encoding scheme to the compensation signal in synchronization with a clock signal. According to claim 1,
The first encoding method is a non-return to zero (NRZ) encoding method,
The second encoding method is a duo-binary encoding method. According to claim 1,
The decoding unit,
A receiver configured to generate the received signal by sampling the transmitted signal at a zero crossing point on an eye diagram of the compensation signal. According to claim 1,
The clock signal is
A receiver having a clock period of 1/2 or less of the transmission rate of the transmission signal. According to claim 1,
The decoding unit,
a first comparator configured to output a first result value or a second result value when the compensation signal is greater than a first reference value or less than a second reference value at a first edge of the clock signal;
When the compensation signal is smaller than the first reference value and greater than the second reference value at the first edge of the clock signal, based on an integral value obtained by integrating the compensation signal for the first period until the first edge of the clock signal , a second comparison unit outputting a third result value or a fourth result value; and
A receiver comprising a; decoder (146decoder) for determining the received signal corresponding to the first to fourth result values. According to claim 5,
The second comparison unit,
a differential integrator integrating the compensation signal for a first period up to a first edge of the clock signal and outputting the integral value; and
A receiver comprising: a second differential comparator outputting one of the third result value and the fourth result value based on the integral value. According to claim 6,
The differential integrator,
Including a first circuit and a second circuit,
The first circuit,
11th and 21st transistors of a first type having gates connected to each other, gated by the clock signal, and having voltage applied to one end connected to each other;
a 31st transistor of the first type having a gate connected to the 11th and 21st transistors and having both ends connected to the other ends of the 11th and 21st transistors;
11th and 21st capacitors having one end connected to both ends of the 31st transistor, respectively;
41st and 51st transistors of the first type having gates connected to each other, gated by an inverted signal of the clock signal, and having one end connected to both ends of the 31st transistor;
A 61st transistor of a second type gated by the compensation signal and having one end connected to the 41st transistor;
The second circuit,
twelfth and twelfth transistors of the first type having gates connected to each other, gated by an inversion signal of the clock signal, and having voltage applied to one end connected to each other;
a 32nd transistor of the first type having a gate connected to the twelfth and 22nd transistors and having both ends connected to the other ends of the twelfth and 22nd transistors;
twelfth and twelfth capacitors having one ends connected to both ends of the 32nd transistor, respectively;
Gates are connected to each other to be gated by the clock signal, one end is connected to both ends of the 32nd transistor, and the other end is connected to the other end of the corresponding transistor among the 41st and 51st transistors. 42nd and 52nd transistors of one type;
A receiver comprising: a 62nd transistor of the second type gated by an inversion signal of the compensation signal and having one end connected to the other end of the 52nd transistor. According to claim 7,
The differential integrator,
71st and 72nd transistors of the second type connected in parallel with the 61st and 62nd transistors, respectively, to adjust voltages across the 31st and 32nd transistors. According to claim 6,
The differential integrator,
Each receiver is provided with at least two or more to which different weights are applied according to the compensation signal before the first edge of the clock signal. According to claim 6,
The second differential comparator,
A receiver that differently applies a weight to the integral value according to a compensation signal before a first edge of the clock signal. According to claim 5,
The integral value is,
The receiver is a value to which different weights are applied according to the compensation signal before the first edge of the clock signal. According to claim 1,
The decoding unit,
A receiver configured to perform sampling corresponding to the first encoding method on a transmission signal encoded by the first encoding method in response to a mode signal. According to claim 1,
A receiver that implements a high-speed memory interface. The receiver of claim 1; and
and a transmitter outputting the transmission signal converted by the first encoding method. a signal processing unit that processes the transmission signal to generate a compensation signal; and
A decoding unit that generates a received signal by sampling the compensation signal in synchronization with a clock signal having a clock period equal to or less than 1/2 of the transmission rate of the transmitted signal;
The decoding unit,
a first comparator configured to output a first result value or a second result value when the compensation signal is greater than a first reference value or less than a second reference value at a first edge of the clock signal;
When the compensation signal is smaller than the first reference value and greater than the second reference value at the first edge of the clock signal, based on an integral value obtained by integrating the compensation signal for the first period until the first edge of the clock signal , a second comparison unit outputting a third result value or a fourth result value; and
A receiver including a decoder (146decoder) for determining the received signal corresponding to the first to fourth result values. According to claim 15,
The transmission signal is a signal encoded by a first encoding method,
The decoding unit,
A receiver performing sampling corresponding to the second encoding method on the compensation signal. According to claim 16,
The first encoding method is a non-return to zero (NRZ) encoding method,
The second encoding method is a duo-binary encoding method. generating a compensation signal by signal processing a transmission signal encoded by a first encoding method; and
A method of operating a receiver comprising: generating a received signal by applying a sampling method corresponding to a second encoding method to the compensation signal in synchronization with a clock signal. According to claim 18,
Generating the received signal,
In synchronization with the clock signal, performing sampling on the transmission signal at a zero crossing point on an eye diagram for the compensation signal;
The clock signal is
A method of operating a receiver having a clock period of 1/2 or less of the transmission rate of the transmission signal. According to claim 19,
Generating the received signal,
decoding a received signal of “11” when the compensation signal is greater than or equal to a first reference value;
decoding a received signal of “00” when the compensation signal is equal to or less than a second reference value;
When the compensation signal is smaller than the first reference value and greater than the second reference value, "10" or "10" based on the integral value obtained by integrating the compensation signal for the first period up to the first edge of the clock signal. A method of operating a receiver including; decoding a received signal of.

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