JPH11345054A - Driver circuit for signal transmission - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the distortion of a waveform caused in a transmission line and the occurrence of interference between codes and to accurately transmit a signal by providing the driver circuit with a level adjusting means, etc., for adjusting the output level of a prestage driver so that an output stage driver outputs a signal of a variable level corresponding to the output level of the prestage driver. SOLUTION: The driver circuit is provided with a level adjusting circuit 5 for compensating the attenuation of a high frequency component and the prestage driver 4 so as to compensate the attenuation of a high frequency component in a signal transmission line 3. Namely at the time of sending a signal from the driver side, the high frequency component of a signal SS is emphasized by the circuit 5 and the driver 4, the emphasized signal S1 is amplified by the output stage driver 1, an output signal S2 from the driver 1 is transmitted to the transmission line 3. Consequently a signal S3 supplied to a receiver 2 through the transmission line 3 is compensated as to the attenuation of the high frequency component and has a waveform free from distortion and interference between codes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission driver circuit, and more particularly to an LSI (Large Scale Integration).
The present invention relates to a signal transmission driver circuit used for signal transmission between chips or between a plurality of elements or circuit blocks in a chip. In recent years, with the high-speed operation of LSI, signal transmission between LSI chips or between a plurality of elements or circuit blocks in a chip, for example, DRAM (Dynamic Radar)
It is also necessary to increase the speed of signal transmission between an ndom access memory) and a processor (logic circuit). Furthermore, high-speed signal transmission is also required in connection between housings for configuring a multiprocessor server and connection between a server and peripheral circuits. Therefore, there is a demand for providing a signal transmission driver circuit capable of high-speed signal transmission.

[0002]

2. Description of the Related Art In recent years, the performance of components constituting computers and other information processing apparatuses has been greatly improved. Specifically, for example, there has been a remarkable improvement in the performance of DRAMs and processors in recent years, and if the signal transmission speed between these components and elements is not improved accordingly, the performance of the entire system will be improved. I can't do that.

That is, for example, the speed gap between a DRAM and a processor tends to be large, and in recent years, this speed gap has been hindering the improvement of computer performance. Further, in addition to the signal transmission between these chips, the signal transmission speed between elements and circuit blocks in the chip has also become a major factor limiting the performance of the chip as the chip becomes larger. Further, there is a need for a signal transmission driver circuit capable of high-speed signal transmission even in connection between housings for configuring a multiprocessor server and in connection between a server and peripheral circuits.

FIG. 1 is a block diagram schematically showing an example of a conventional signal transmission driver circuit. In FIG. 1, reference numeral 301 denotes an output stage driver, 302 denotes a receiver,
03 denotes a signal transmission path, and 304 denotes a preceding driver. As shown in FIG. 1, the conventional signal transmission driver circuit includes an output stage driver 301 and a pre-stage driver 304, and for example, a high-speed signal S of about several Gbps.
S is amplified by the pre-stage driver 304 and the output stage driver 301, and is amplified via the signal transmission path 303 by the receiver 302.
To tell. Here, the signal transmission path 303
Is, for example, a cable having a length of several meters to several tens of meters for making a connection between housings for configuring a multiprocessor server and a connection between the server and peripheral circuits,
Specifically, it is configured as a thin copper wire of about 30 AWG (American Wire Gauge).

[0005]

As shown in FIG. 1 described above, for example, a high-speed signal SS of several Gbps is amplified by a pre-stage driver 304 and an output-stage driver 301, and an output signal S2 of the output-stage driver 301 is amplified. For example,
When transmitted by a signal transmission line (cable) 303 composed of a thin copper wire having a length of several meters and having a thickness of about AWG30, attenuation of a high-frequency component occurs due to a skin effect of the cable, and the received waveform S3 at the receiver 302 becomes distorted. turn into. In addition, the reception waveform S3 in the receiver 302 has a large interference between codes, and may not be able to be received by a normal reception circuit.

The present invention has been made in consideration of the above-mentioned problems of the conventional signal transmission driver circuit, and prevents a waveform distortion and an interference between codes which occur in a process in which a signal is transmitted through a transmission line, thereby providing an accurate signal. It is an object of the present invention to provide a signal transmission driver circuit capable of transmission.

[0007]

According to the present invention, there is provided a signal transmission driver circuit for transmitting a signal, comprising: an output stage driver; a pre-stage driver for driving the output stage driver; There is provided a signal transmission driver circuit, comprising: level adjustment means for adjusting an output level, wherein the output stage driver outputs a signal of a variable level according to the output level of the preceding stage driver.

According to the driver circuit for signal transmission of the present invention, the output stage driver outputs a variable level in accordance with the output of the preceding stage driver whose output level is adjusted by the level adjusting means. This makes it possible to perform accurate signal transmission while preventing waveform distortion and interference between codes that occur in the process of transmitting a signal through a transmission path.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing an embodiment of a signal transmission driver circuit according to the present invention in detail, a principle configuration of the present invention will be described with reference to FIG. FIG. 2 is a block diagram schematically showing the principle configuration of the signal transmission driver circuit according to the present invention. In FIG. 2, reference numeral 1 denotes an output stage driver,
Reference numeral 2 denotes a receiver, 3 denotes a signal transmission path, 4 denotes a preceding driver, and 5 denotes a level adjustment circuit. Here, the signal transmission path 3 is configured by a thin copper wire such as AWG 30 or the like and having a length of about several meters.

As shown in FIG. 2, the signal transmission driver circuit of the present invention is provided with a circuit (level adjustment circuit 5 and pre-stage driver 4) for compensating for attenuation of high frequency components. It is designed to compensate for attenuation. That is, when a signal is transmitted on the driver side, the level adjustment circuit 5 and the preceding driver 4
The high frequency component of the signal SS is emphasized, the signal S1 is amplified by the output stage driver 1, and the output signal S2 of the output stage driver 1 is
To the signal transmission path 3. As a result, the signal S3 supplied to the receiver 2 through the signal transmission path 3 has a waveform in which the attenuation of the high-frequency component due to the signal transmission path 3 is compensated and free from distortion and intersymbol interference. The same effect can be obtained by providing a circuit for compensating the frequency characteristics of the signal transmission line 3 on the receiving side (the receiver 2 side).

In general, if the length or the structure of the signal transmission line 3 changes, the amount of attenuation on the high frequency side of the transmitted signal also changes. Therefore, it is necessary to make the signal transmission level variable on the driver side, regardless of whether the characteristics are compensated on the driver side or performed on the receiver side. Specifically, by configuring a discrete-time filter on the driver side, the driver can be provided with a desired frequency characteristic.
The driver needs to output an analog level.

For this reason, in the signal transmission driver circuit of the present invention, as shown in FIG.
Drives the output stage driver 1 to obtain an analog level. FIG. 3 is a waveform diagram showing the operation of the signal transmission driver circuit according to the present invention in comparison with a conventional driver circuit. FIG. 3A shows the output of the conventional output stage driver, and FIG. Indicates the output of the output stage driver 1 in the signal transmission driver circuit of the present invention. FIGS. 3A and 3B show the potential difference ΔV in the complementary signal.
And specifically shows a waveform when the data changes to "0, 1, 1, 0, 0, 0, 1".

The potential difference of the output waveform of the conventional output stage driver (301) is + V0 and -V0 according to data "1" and "0" as shown in FIG. On the other hand, the potential difference of the output waveform of the output stage driver 1 in the signal transmission driver circuit of the present invention is shown in FIG.
As shown in (b), when the data changes from “0” to “1”, it is set to + V2 (large potential difference), and when the data changes from “1” to “0”, −V2 ( Large potential difference), the data remains “1” and “0”
+ V1 and -V1 (small potential difference)
It is said.

In the above description, two levels of each data "1" and "0" are set. However, the number of levels is not limited to two, and a plurality of levels can be set. Further, the voltage level + V0 in FIG. 3A corresponds to, for example, the voltage level + V1 in FIG. 3B. As described above, in the signal transmission driver circuit of the present invention, the driver (output stage driver 1) outputs an analog level (a total of four levels in FIG. 3B) instead of a binary digital value. The driver circuit can perform an equalization process (equalization) for compensating for the frequency characteristics of the signal transmission path 3 to easily increase the speed of signal transmission.

Hereinafter, embodiments of a signal transmission driver circuit according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 4 is a circuit diagram schematically showing a first embodiment of the signal transmission driver circuit of the present invention. FIG. 5 is a circuit diagram showing an example of a configuration of a gain variable section in the signal transmission driver circuit of FIG. 4. FIG. 6 is a circuit diagram showing an example of a configuration of an amplifier circuit in the signal transmission driver circuit of FIG. It is.

As shown in FIG. 4, in the signal transmission driver circuit according to the first embodiment, the pre-stage driver 4 includes an amplifying unit 41, a variable gain unit 42, and a feedback resistor 43. The output stage driver 1 is n
Channel MOS transistor (nMOS transistor) 11 and p-channel MOS transistor (pM
(OS transistor) 12.

The output stage driver 1 is configured as, for example, a source follower circuit having a gain of about 1 using a large-sized nMOS transistor 11 and pMOS transistor 12 to drive a load resistance of several tens of ohms. As shown in FIG. 5, the gain variable section 42
It is composed of a plurality of transfer gates 421 to 42n that are switching-controlled by control signals (control codes) φ1 to φn from a control signal generation circuit (level adjustment circuit) 5, and each control signal (for example, φ1) is at a high level “H”. And the corresponding transfer gate (421)
Is turned on to make the input voltage gain of the input signal (SS) variable. Here, the control signals φ1 to φn are directly supplied to the gates of the nMOS transistors of the transfer gates 421 to 42n.
Inverted control signals φ1 to φn are supplied to the gate of the S transistor via an inverter.
The number of control signals φ1 to φn and corresponding transfer gates 421 to 42n is, for example, 16 or 3
It can be set to about two, but as a minimum case, it may be set to two (φ1, φ2 and 421, 422).

As shown in FIG. 6, the amplifying unit 41
The differential amplifier circuit is constituted by MOS transistors 411 to 413 and nMOS transistors 414 to 417, and the active state is controlled by a signal φE supplied to the gates of the transistors 416 and 417. According to the first embodiment, the output signal S2
Since the levels of the outputs “0” and “1” in (S1) can be made variable, the output signal S2 of the driver can be changed according to the amount of attenuation of the cable 3,
High speed and low power consumption can be satisfied.

FIG. 7 is a circuit diagram schematically showing a second embodiment of the signal transmission driver circuit of the present invention. As is clear from the comparison between FIG. 7 and FIG. 4, in the second embodiment, the pre-stage driver 4 (control signal generation circuit 5) has the same configuration as the first embodiment, and the output stage driver 1 is the first embodiment. Is configured differently.

That is, in the second embodiment, the output stage driver 1 is constituted by an amplifier circuit 11 to which feedback is applied. Here, the resistance value of the feedback resistor 13 is set to be about 2 to 4 times the resistance value of the resistor 12 provided on the input (inverting input) side,
A gain of about 2 to 4 times is given. Specifically, for example, the resistance value of the resistor 12 is set to 1 KΩ, and the resistance value of the feedback resistor 13 is set to 3 KΩ.
Can be set to about 3.

In the second embodiment, the variable-level output S1 of the pre-stage driver 4 is further amplified and output by the output-stage driver 1 (S2). There is an advantage that instability such as oscillation does not easily occur when driving a load. Further, by making the gains of both the pre-stage driver 4 and the output stage driver 1 variable, it is possible to widen the change range of the gain in the output signal S2 of the output stage driver 1.

FIGS. 8 and 9 show a third embodiment of the signal transmission driver circuit of the present invention. FIG. 8 shows an example of the configuration of a preceding stage driver, and FIG. 9 shows one example of an output stage driver. FIG. 3 is a circuit diagram illustrating a configuration example. As shown in FIG. 8, in the third embodiment, the pre-stage driver 4 is configured as a current limiting inverter. That is, the current limiting inverter (pre-stage driver) 4
MOS transistors 44 and 45 and nMOS transistors 46 and 47 are provided.
The gate of the transistor 44 and the gate of the nMOS transistor 47 are supplied in common. Also, pM
The control voltage Vcp is applied to the gate of the OS transistor 45, and the control voltage Vcn is applied to the gate of the nMOS transistor 46.

As shown in FIG. 9, in the third embodiment, the output stage driver 1 can be configured as a constant current circuit using a current mirror circuit, and the output terminal (S2 ), A current-voltage conversion circuit for converting an input current (output of the preceding driver 4) S1 into an output voltage S2 is provided.

The constant current circuit (output stage driver) 1 has a pM
It comprises OS transistors 14, 15, 16 and nMOS transistors 17, 18, 19, and a resistance load 10 is provided at the output terminal. Where pM
The OS transistors 15 and 16 are current mirror connected, and the nMOS transistors 18 and 19 are current mirror connected.

As described above, the pre-stage driver 4 for driving the current-voltage conversion circuit (constant current circuit 1 and load resistor 10)
8 is used, the output current of the preceding driver 4 is controlled by changing the control voltage (Vcp, Vcn) of the current limiting inverter (previous driver) 4. Output stage driver 1
Is amplified by the current mirror and appears. According to the third embodiment, at the input terminal (S1) of the output stage driver 1, the output level can be controlled by current addition, so that there is an advantage that the level control can be easily performed. As will be described later, the current limit of the pre-stage driver 4 can be easily controlled using a current output D / A converter or the like.

FIG. 10 is a circuit diagram showing a modification of the third embodiment of the signal transmission driver circuit of the present invention. As shown in FIG. 10, in a modification of the third embodiment, a resistance load 40 is provided at the output terminal of a current limiting inverter (pre-stage driver) 4 to generate a voltage output (S1). The output signal is linearly amplified by the output stage driver 1 similar to that of the second embodiment to obtain an output signal S2 having a variable voltage level.

FIG. 11 is a circuit diagram schematically showing an output stage driver as a fourth embodiment of the signal transmission driver circuit of the present invention. As shown in FIG. 11, in the fourth embodiment, the output stage driver 1 includes a pMOS transistor 1
01 and an nMOS transistor 102, and an output-to-input feedback resistor (circuit) 103.

In the output stage driver 1 according to the fourth embodiment, the output impedance of the inverter (101, 102) is reduced by the feedback resistor 103 (for example, about several tens of Ω). That is, by using the feedback resistor 103, the output impedance is reduced to one of the loop gain when the feedback circuit is not provided.

As described above, according to the fourth embodiment, an output impedance of, for example, about several tens of ohms can be obtained by the small-sized output transistors (101, 102). FIG. 12 is a circuit diagram schematically showing a fifth embodiment of the signal transmission driver circuit of the present invention.

As shown in FIG. 12, in the fifth embodiment, the former-stage driver 4 has the same configuration as that shown in FIG. 8, and the output-stage driver 1 has an amplifier circuit 104 and a feedback resistor 105. Have been. The control signal generation circuit (level adjustment circuit) 5 includes three delay stages 531, 532, and 53 that provide a delay for each bit.
3, a decoder 54, a weighting circuit 51 for weighting the output of the decoder 54, and a weighting circuit 51
And a control voltage generation unit 55 that generates control voltages Vcp and Vcn from the current obtained by the above.

The decoder 54 outputs a signal (a signal delayed by 1 bit, 2 bits, and 3 bits) delayed by each of the delay stages 531, 532 and 533 connected in series and a signal SS directly input. It receives a temporal 4-bit data series and outputs weighting signals CS1 to CSn corresponding to the 4-bit data series.
The weighting circuit 51 includes a plurality of pairs (for example, 16) of pM
OS transistors 511, 521; 512, 522;
51n, 52n and one transistor 511 of each pair.
To 51n, a bias voltage Vc is applied to the gates,
Weighting signals CS1 to CSn from the decoder 54 are supplied to the gates of the other transistors 521 to 52n. Here, the decoder 54 is constituted by, for example, a static RAM (SRAM).
When the power is turned on, for example, a test bit sequence is transmitted to the receiving side via the signal transmission path 3, and the correspondence between the input 4-bit data sequence and the output weighting signals CS 1 to CSn according to the result is obtained. Is written.

Transistors 511, 521; 512, 5
22;... 51n and 52n have different sizes for each pair, and the weighting signal CS1 output from the decoder 54.
To CSn attains a low level “L”, the corresponding one of the transistors (521 to 52n) is turned on, and a current corresponding to the size of the turned on transistor is generated by the control voltage generation unit. 55 (transistor 55
It flows through 1). Here, the weighting signals CS1 to CSn correspond to the immediately preceding bit (one bit before).
, The level of the output signal S1 (S2) is controlled so that the influence of the data two bits before and the data three bits before is small. The transistor 5 of the weighting circuit 51
., 522;... 51n and 52n are transistors of the same size, and the weighting signals CS1 to CSn output from the decoder 54 are low-level by an arbitrary number according to the input 4-bit data series. L ”, a predetermined number of transistors (521 to 52
n) may be turned on, and a current corresponding to the number of turned on transistors may flow through the transistor 551.

The control voltage generator 55 includes nMOS transistors 551 and 553 and a pMOS transistor 552
And a current weighted by the weighting circuit 51 is supplied to the transistor 551, and the transistor 55 is connected to the transistor 551 in a current mirror manner.
3 and the transistor 552 connected in series to the transistor 553 generate control voltages Vcn and Vcp. These control voltages Vcn and Vcp are applied to the gates of the transistors 46 and 45 in the pre-stage driver 4, respectively, to control the level of the signal S2 output via the output stage driver 1.

As described above, according to the fifth embodiment, accurate signal transmission can be performed by compensating the frequency characteristic of the signal transmission line 3 on the driver side. FIG. 13 is a circuit diagram schematically showing a sixth embodiment of the signal transmission driver circuit of the present invention. As shown in FIG. 13, in the sixth embodiment, the pre-stage driver 4 includes four delay stages 401, 402, 403, and 404 each of which gives a delay of one bit.
Five current limiting inverters 405, 406, 407, 4
08, 409. Here, the current limiting inverter 405 receives the signal SS directly, the current limiting inverter 406 receives the signal SS one bit earlier by the delay stage 401, and the current limiting inverter 407 receives the signal SS. And 402, the signal SS two bits earlier is input, the current limiting inverter 408 receives the signal SS three bits earlier by the delay stages 401 to 403, and the current limiting inverter 409 has a delay. The stages 401 to 404 receive the signal SS four bits earlier.

Each of the current limiting inverters 405 to 409
The control signal (Vc) supplied to each of the current limiting inverters 405 to 409 is configured as shown in FIG.
By selecting (p, Vcn) and the polarity, the driver has a frequency characteristic opposite to the transmission characteristic of the signal transmission line 3. Note that the current limiting inverters 405 to 4
For example, the size of the transistor constituting the transistor 09 is set such that the transistor used for the current limiting inverter 405 is the maximum size, the transistor size is sequentially reduced, and the size of the transistor used for the current limiting inverter 409 is minimized. ing. The output stage driver 1 has the same configuration as that of the fifth embodiment shown in FIG.

As described above, in the sixth embodiment, the temporal bit sequence data of the signal SS is received by a plurality of constant current output drivers (current limiting inverters 405 to 409), and the common output (S1) To the input terminal of the current-voltage conversion driver (output stage driver) 1. Thus, also in the sixth embodiment, accurate signal transmission can be performed by compensating the frequency characteristics of the signal transmission line 3 on the driver side.

FIG. 14 is a circuit diagram schematically showing a seventh embodiment of the signal transmission driver circuit of the present invention. As is clear from the comparison between FIG. 14 and FIG. 15, in the seventh embodiment, the pre-stage driver 4 includes one delay stage 411, an inverter 412, and two current limiting inverters 413 and 414. Have been. The current limiting inverter 413 delays the signal SS by the delay stage 411, receives a signal obtained by inverting the delayed signal by the inverter 412, and multiplies the signal by x (0 <x <1) with respect to the current limiting inverter 414. Output. Therefore, the output signal S1 of the pre-stage driver 4 is S1 =
1−xD. This is the so-called PRD (Partial Re
This is equivalent to causing the output stage driver 1 to perform the same equalization processing (equalization operation) as the sponse detection.

As described above, the sixth embodiment is effective in transmitting a high-speed signal through a band-limited signal transmission line with a simple circuit. FIG. 15 is a circuit diagram schematically showing an eighth embodiment of the signal transmission driver circuit of the present invention. FIG.
As shown in FIG. 5, in the eighth embodiment, the pre-stage driver 4 includes, for example, a 300 MHz four-phase clock E1,
It comprises four current limiting inverters 421, 422, 423, 424 that are enabled and controlled by E2, E3, E4. Here, each current limiting inverter 42
For example, different signals (data) SS1 to SS4 synchronized with a 300 MHz clock are supplied to the 1 to 424, respectively, and sequentially enabled by the four-phase clocks E1 to E4, and the output signal S1 becomes 1.2 GHz (300 MHz).
× 4) is configured to be serial data.
The configuration of each of the current limiting inverters 421 to 424 is the same as that of FIG. 8, and the output stage driver 1 has the same configuration as that of the above-described fifth to seventh embodiments.

As described above, in the eighth embodiment, the pre-stage driver 4 is configured as a four-to-one multiplexer by the four current limiting inverters 421 to 424 operating by interleaving with a four-phase clock. The parallel-to-serial conversion, which is always required for transmission, is performed in the driver (pre-stage driver 4). In FIG. 15, four different input signals SS1 to SS4 synchronized with a 300 MHz clock are
Although an example in which the processing is performed by the four current limiting inverters 421 to 424 that are enabled and controlled by the four-phase clocks E1 to E4 of MHz has been described, the signal transmission driver circuit of the present invention is not limited to this configuration. 10 different input signals synchronized with the clock of
z, which is constituted by ten current limiting inverters that are enabled and controlled by a 10-phase clock of z
(Configured as a 0-to-1 multiplexer).

FIG. 16 is a circuit diagram showing a specific example of the configuration of the preceding driver in the signal transmission driver circuit of FIG. As shown in FIG. 16, the pre-stage driver 4
Configured to operate as a one-to-one multiplexer,
Data latches 431 to 434 to which input signals SS1 to SS4 are respectively supplied, and flip-flops 451 to 45
4 and a four-channel multiplexer 400.

The multiplexer section 400 includes an inverter 461, a pre-emphasis driver 462, and a pre-emphasis driver 462 for each of the channels (ch1 to ch4) 400a to 400d.
The pre-driver 463 is provided. here,
Input signals SS1 to SS4 are applied to data latches 431 to 434.
, The signal lines from which the outputs of the data latches 431 to 434 are supplied to the flip-flops 451 to 454, and the signal lines from which the outputs of the flip-flops 451 to 454 are supplied to the multiplexer unit 400, for example. , 4 channels of 312.5 MHz data lines, and a multiplexer 400 (each channel 4
00a to 400d) pre-emphasis driver 462
And outputs DD, / DD (S1,
/ S1) is, for example, complementary (differential)
1.25 Gbps signal line.

Here, the pre-emphasis driver 462
Is to adjust the level of the output signal (emphasis processing of the edge portion of the signal waveform) in accordance with the data series of the supplied signals (SS1 to SS4) and output a complementary signal. In FIG. The output level is adjusted according to the signal (emphasis control signal) CS0. FIG.
FIG. 7 is a circuit diagram showing a specific configuration example of an output stage driver in the signal transmission driver circuit of FIG.

The signals DD and / D output from the multiplexer 400 of the preceding driver 4 in FIG.
D (S2, / S2) is, for example, a 1.25 Gbps complementary signal, but is supplied to the output stage driver 1 and transmitted to the signal transmission line 3 as complementary signals DDo, / DDo (S2, / S2). As shown in FIG. 17, output stage driver 1 is configured as two sets of drivers including an inverter 111 and a transfer gate 112 to amplify each of complementary signals DD (S2) and / DD (/ S2). Have been. Here, the transfer gate 112
Are used to feed back the output of the inverter 111 to the input.

FIG. 18 is a circuit diagram showing a specific configuration example of the pre-driver circuit in the pre-stage driver of FIG.
The pre-driver circuit 463 is provided for each of the channels Ch1 to Ch4.
, Two for each complementary signal Data, / Data (output signals DD, / DD). here,
Four-phase clock signals Clk (A), Clk (B), Cl
k (C) and Clk (D) are signals whose rising timings differ from each other by 90 degrees.
Data of each of the channels 1 to Ch4 of 12.5 MHz is sequentially selected (multiplexed) to 1.25 Gbp.
Output signals DD and / DD complementary to s are generated.

The pre-emphasis driver 462
Basically, the pre-driver circuit 463 shown in FIG.
The configuration is the same as described above. However, in the pre-emphasis driver 462, the emphasis control signal CS
0 adjusts the output level (emphasis processing). More specifically, for example, the current sources IA and IB in the output stage are configured by pMOS transistors and nMOS transistors, and the gates of these current source transistors are emphasized. Control signal CS0 (current control voltage CS0p, C
S0n) is applied to enhance the output level.

The circuit shown in FIG. 18 is merely an example of the pre-driver circuit 463 (pre-emphasis driver 462), and various circuits having various circuit configurations can be used. FIGS. 19 and 20 are diagrams showing examples of simulation waveforms in a signal transmission driver circuit to which the circuits shown in FIGS. 16 to 18 are applied.

As shown in FIG. 19, in the multiplexer section 400 (each channel 400a to 400d),
For example, each channel CH1 to CH4 (400a to 400
d) input data signal (T-
1, T) are four-phase clocks Clk (A) to Clk
The signals are sequentially selected by each pre-driver circuit 463 controlled by (D), and are converted into complementary signals of 1.25 Gbps. At this time, each channel C of the multiplexer 400
Pre-emphasis driver 462 for H1 to CH4
Also outputs complementary signals of 1.25 Gbps that perform signal level emphasizing processing according to the series of output signals. Complementary output signals DD and / DD are output by the pre-driver circuit 463 and the pre-emphasis driver 462 of each channel. Will be obtained.

That is, as shown by reference numeral PE in FIGS. 19 and 20, the level is inverted (“1” → “0” or “0” →) in a continuous output signal sequence.
At the position where “1”) is performed, processing (emphasizing processing) for emphasizing the edge of the waveform of the output signal is performed. Note that FIG.
, The reference symbol T is the data cycle (3.2n) of each channel Ch1 to Ch4 supplied at 312.5 MHz.
s), where t is the multiplexed 1.25 Gb
ps complementary output signals DD, / DD cycle (0.8n
s).

FIG. 21 is a circuit diagram schematically showing an output stage driver as a ninth embodiment of the signal transmission driver circuit of the present invention. As shown in FIG. 21, in the ninth embodiment, the output stage driver 1 includes a pMOS transistor 121 having a common source and an nMOS transistor 1 having a common source.
22 as a push-pull circuit (inverter). As described above, when the output stage driver 1 is configured as an inverter, there is an advantage that an output in an output range (rail-to-rail) that fully covers the potential of the high potential power supply Vdd and the potential of the low potential power supply Vss is obtained. .

FIG. 22 is a circuit diagram schematically showing an output stage driver as a tenth embodiment of the signal transmission driver circuit of the present invention. As shown in FIG. 22, in the tenth embodiment, the output stage driver 1 is configured as a source follower circuit including a common drain nMOS transistor 133 and a common drain pMOS transistor 134. Note that the amplifiers 131 and 132 are for shifting the gate voltages of the transistors 133 and 134 by the threshold voltage of each transistor, respectively.
32, nMOS transistor 133 and pM
An offset is provided so that the period during which the OS transistor 134 is simultaneously turned on is minimized.

As described above, the output stage driver 1 is connected to the nMOS
Transistor 133 and pMOS transistor 134
, It is possible to obtain a wideband output by lowering the output impedance. FIG. 23 is a circuit diagram schematically showing an eleventh embodiment of the signal transmission driver circuit of the present invention.

As shown in FIG. 23, in the eleventh embodiment, the final stage of the output stage driver 1 is configured as an inverter including a pMOS transistor 145 and an nMOS transistor 148, and the potential of the high potential power supply Vdd and the potential of the low potential An output in an output range that fully covers the potential of the power supply Vss is obtained. Further, a pull-up element (a diode-connected pMOS transistor 14) is connected to the gate of the pMOS transistor 145 of the last inverter.
4), the gate potential of the pMOS transistor 145 is shifted to the high potential (Vdd) side, and a pull-down element (a diode-connected nMOS transistor 147) is provided for the gate of the nMOS transistor 148.
The gate potential of the nMOS transistor 148 is shifted to a low potential (Vss). As a result, the transistors 145 and 148 constituting the inverter are simultaneously turned on to prevent a through current from flowing, thereby reducing current consumption. In addition,
The pMOS transistor 143 and the nMOS transistor 146 function as resistors for stabilizing the circuit. Further, the inverters 141 and 142 to which the signal S1 is input are configured by transistors having a small size, and the inverters (145, 1
The problem of current consumption as in 48) does not occur.

FIG. 24 is a circuit diagram schematically showing a modification of the eleventh embodiment of FIG. As shown in FIG.
In the present modification, as in the eleventh embodiment of FIG. 23, the last stage of the output stage driver 1 is configured as an inverter including a pMOS transistor 154 and an nMOS transistor 157, and the potential of the high potential power supply Vdd and the low potential power supply Vss
Is obtained in an output range that fully covers the potential. In this modification, the gate of pMOS transistor 154 of the last-stage inverter has pMO
S transistor 152 and nMOS transistor 15
3 and the pMOS transistor 1 is connected to the gate of the nMOS transistor 157.
55 and an output of an inverter composed of an nMOS transistor 156.

Here, pM in the last-stage inverter
The size of the pMOS transistor 152 in the inverter that drives the OS transistor 154 is larger than that of a normal one (about 30% larger), and is substantially a pull-up element (the transistor in the eleventh embodiment of FIG. 23). 144). Similarly, nM in the last-stage inverter
The nMOS transistor 156 in the inverter that drives the OS transistor 157 has a size larger than that of a normal one (about 30% larger), and is substantially a pull-down element (the transistor 147 in the eleventh embodiment of FIG. 23). ). Further, in this modification, the output side (S
2) and the input side (S1) are connected by a feedback resistor 158 to lower the output impedance.

FIG. 25 is a circuit diagram schematically showing an output stage driver as a twelfth embodiment of the signal transmission driver circuit of the present invention. As shown in FIG. 25, in the twelfth embodiment, a source follower circuit including an nMOS transistor 161 and a pMOS transistor 164 is provided as a first stage of the output stage driver 1, and a pMOS transistor (pull-up element) applied to a control voltage Vcp gate is used. ) 162
And an nMOS transistor (pull-down element) 165 applied to the gate of the control voltage Vcn and a pMOS transistor 163 and n in the final stage whose source is grounded.
The MOS transistor 166 is driven.

According to the twelfth embodiment, the period during which the pMOS 163 and the nMOS transistor 166 in the output stage are simultaneously turned on is reduced by the shift of the threshold voltage by the source follower circuits (161, 164) in the first stage. The power is reduced. In addition, the twelfth
According to the embodiment, since the output stage driver 1 can be constituted by two-stage amplifier circuits (source follower circuits 161 and 164 and grounded source circuits 163 and 166), there is an advantage that the frequency characteristics are good.

FIG. 26 is a circuit diagram schematically showing an output stage driver as a thirteenth embodiment of the signal transmission driver circuit of the present invention. As shown in FIG. 26, in the thirteenth embodiment, the output stage driver 1 basically includes an inverter including a pMOS transistor 174 and an nMOS transistor 175, and a feedback resistor 177 for connecting the output and input of the inverter. The power supply voltage applied to the inverters (174, 175) is made lower than the normal power supply voltages (Vdd and Vss) to reduce the through current. That is, the voltage applied to the source (node N1) of the pMOS transistor 174 is set to Vddi, and the voltage applied to the source (node N2) of the nMOS transistor 175 is set to Vssi. Here, for example, the high potential power supply voltage Vd
When d is 2.5V, the voltage Vddi of the node N1 becomes 2.
About 1 V, and the low-potential power supply voltage Vdd is 0 V
At this time, the voltage Vssi of the node N2 is about 0.4 V, which makes it possible to reduce the through current flowing through the inverters (174, 175) by about one digit.

Referring to FIG. 26, amplifying circuit 171 and p
MOS transistor 173 is for generating voltage Vddi, and has an amplifying circuit 172 and nMO
The S transistor 176 is for generating the voltage Vssi. Here, an amplification circuit (operational amplifier) 171
Is input with a reference voltage Vref + (= Vddi), and the input of the positive logic side of the amplifier circuit 171 is a node N.
1 and the output of the amplifier circuit 171 is supplied to the gate of the transistor 173. This allows
The amplifier 171 converts the potential of the node N1 to the reference voltage Vref +
The transistor 173 is controlled so that (= Vddi). Similarly, a reference voltage Vref- (= Vssi) is applied to the negative logic side input of the amplifier circuit (operational amplifier) 172, and the positive logic side input of the amplifier circuit 172 is connected to the node N2. The output of 172 is provided to the gate of transistor 176. Accordingly, the amplifier 172 changes the potential of the node N2 to the reference voltage Vref-(= Vs
The transistor 176 is controlled so as to satisfy si).

As described above, in the thirteenth embodiment, the output stage driver 1 basically includes a feedback resistor (177).
Are configured as inverters (174, 175) having
High potential side power supply voltage (Vddi) given to the inverter
Is lower than the normal high-potential power supply voltage (Vdd), and the low-potential-side power supply voltage (Vssi) is higher than the normal low-potential power supply voltage (Vss). It is designed to reduce it. Thus, sufficient frequency characteristics as an output stage driver can be provided while suppressing power consumption.

FIG. 27 is a circuit diagram schematically showing a modification of the thirteenth embodiment of FIG. As shown in FIG.
In the modification of the thirteenth embodiment, as in the thirteenth embodiment, the output stage driver 1 basically includes an inverter including a pMOS transistor 184 and an nMOS transistor 185 and an output and an input of the inverter. A power supply voltage applied to the inverters (184, 185) is made lower than normal power supply voltages (Vdd and Vss) to reduce a through current. That is, the voltage applied to the source (node N1) of the pMOS transistor 184 is set to Vddi, and the voltage applied to the source (node N2) of the nMOS transistor 185 is set to Vssi. Here, the amplifier circuit (operational amplifier) 181 and the pMOS transistor 183 for generating the voltage Vddi are the same as those in the thirteenth embodiment shown in FIG. 26, but the circuits for generating the voltage Vssi are different.

That is, in the present modification, the intermediate voltage Vdd / 2 is applied as a reference voltage to the input on the negative logic side of the amplifier circuit (operational amplifier) 182, and the input of the resistor on the positive logic side input of the amplifier circuit 182. The intermediate voltage of the replica driver 188 by 189 and 190 is applied, and the output of the amplifier circuit 182 is supplied to the gate of the transistor 186. Here, voltages Vddi and Vssi of nodes N1 and N2 are used as power supply voltages of replica driver 188, and these voltages Vdd are used.
The intermediate voltage between i and Vssi is the normal power supply voltage Vd
Control is performed so as to match the intermediate voltage (Vdd / 2) between d and Vss.

FIG. 28 is a circuit diagram showing an example of a configuration of a replica driver in a modification of FIG. As shown in FIG. 28, the replica driver 188 includes an inverter 1881 that receives a low-potential power supply voltage Vss and an inverter 1882 that receives a high-potential power supply voltage Vdd. Here, these inverters 188
1 and 1882 are supplied with the voltage Vddi of the node N1 and the voltage Vssi of the node N2 as power supply voltages. In addition, these inverters 1881 and 1882
Is configured as a small-sized transistor so as to make the current flowing constantly small.

Voltage Vs output from inverter 1881
si and the voltage Vdd which is the output of the inverter 1882
i is applied to both ends of two resistors 189 and 190 having the same resistance value, and a signal (voltage) supplied to a positive logic input of the amplifier 182 is extracted from a connection node N3 of the resistors 189 and 190. Here, the voltage of the node N3 is an intermediate voltage between the voltages Vssi and Vddi,
It only needs to be equal to the intermediate voltage Vdd / 2 between the power supply voltages Vdd and Vss, and as such, the amplifier 182 will control the transistor 186 to control the voltage at the node N2.

As described above, in the modification of the thirteenth embodiment shown in FIGS. 27 and 28, even if there is a difference in the characteristics and the like of the transistor at the stage of manufacturing the semiconductor,
The final stage inverter (18 in the output stage driver 1)
4,185) can be correctly controlled.

[0065]

As described above in detail, according to the signal transmission driver circuit of the present invention, it is possible to prevent waveform distortion and interference between codes which occur in the process of transmitting a signal through a transmission line. Accurate signal transmission can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing an example of a conventional signal transmission driver circuit.

FIG. 2 is a block diagram schematically showing a principle configuration of a signal transmission driver circuit according to the present invention.

FIG. 3 is a waveform diagram showing an operation of the driver circuit for signal transmission according to the present invention in comparison with a conventional driver circuit.

FIG. 4 is a circuit diagram schematically showing a first embodiment of a signal transmission driver circuit of the present invention.

FIG. 5 is a circuit diagram showing one configuration example of a gain variable section in the signal transmission driver circuit of FIG. 4;

FIG. 6 is a circuit diagram showing one configuration example of an amplifier circuit in the signal transmission driver circuit of FIG. 4;

FIG. 7 is a circuit diagram schematically showing a second embodiment of the signal transmission driver circuit of the present invention.

FIG. 8 is a circuit diagram showing a configuration example of a pre-stage driver in a third embodiment of the signal transmission driver circuit of the present invention.

FIG. 9 is a circuit diagram showing a configuration example of an output stage driver in a third embodiment of the signal transmission driver circuit of the present invention.

FIG. 10 is a circuit diagram showing a modification of the third embodiment of the signal transmission driver circuit of the present invention.

FIG. 11 is a circuit diagram schematically showing an output stage driver as a fourth embodiment of the signal transmission driver circuit of the present invention.

FIG. 12 is a circuit diagram schematically showing a fifth embodiment of the signal transmission driver circuit of the present invention.

FIG. 13 is a circuit diagram schematically showing a sixth embodiment of the signal transmission driver circuit of the present invention.

FIG. 14 is a circuit diagram schematically showing a seventh embodiment of the signal transmission driver circuit of the present invention.

FIG. 15 is a circuit diagram schematically showing an eighth embodiment of the signal transmission driver circuit of the present invention.

16 is a circuit diagram showing a specific configuration example of a pre-stage driver in the signal transmission driver circuit of FIG.

17 is a circuit diagram showing a specific configuration example of an output stage driver in the signal transmission driver circuit of FIG.

FIG. 18 is a circuit diagram showing a specific configuration example of a pre-driver circuit in the pre-stage driver of FIG.

19 is a diagram (part 1) illustrating an example of a simulation waveform in a signal transmission driver circuit to which the circuits illustrated in FIGS. 16 to 18 are applied;

20 is a diagram (part 2) illustrating an example of a simulation waveform in the signal transmission driver circuit to which the circuits illustrated in FIGS. 16 to 18 are applied;

FIG. 21 is a circuit diagram schematically showing an output stage driver as a ninth embodiment of the signal transmission driver circuit of the present invention.

FIG. 22 is a circuit diagram schematically showing an output stage driver as a tenth embodiment of the signal transmission driver circuit of the present invention.

FIG. 23 is a circuit diagram schematically showing an output stage driver as an eleventh embodiment of the signal transmission driver circuit of the present invention.

FIG. 24 is a circuit diagram schematically showing a modification of the eleventh embodiment of FIG. 23;

FIG. 25 is a circuit diagram schematically showing an output stage driver as a twelfth embodiment of the signal transmission driver circuit of the present invention.

FIG. 26 is a circuit diagram schematically showing an output stage driver as a thirteenth embodiment of the signal transmission driver circuit of the present invention.

FIG. 27 is a circuit diagram schematically showing a modification of the thirteenth embodiment of FIG. 26;

FIG. 28 is a circuit diagram showing a configuration example of a replica driver in a modification of FIG. 27;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Output stage driver 2 ... Receiver 3 ... Signal transmission line 4 ... Pre-stage driver 5 ... Level adjustment circuit (control signal generation circuit)

Claims (19)

[Claims] 1. A signal transmission driver circuit for transmitting a signal, comprising: an output stage driver; a pre-stage driver for driving the output stage driver; and level adjusting means for adjusting an output level of the pre-stage driver. A driver circuit for signal transmission, wherein the output stage driver outputs a signal of a variable level according to the output level of the preceding stage driver. 2. The signal transmission driver circuit according to claim 1, wherein the output stage driver has a common-drain push-pull structure using a pMOS transistor and an nMOS transistor. 3. The signal transmission driver circuit according to claim 1, wherein the output stage driver is configured as a voltage amplifying circuit, and the output level of the output stage driver is changed by adjusting the output level of the preceding stage driver. A signal transmission driver circuit characterized in that: 4. The signal transmission driver circuit according to claim 1, wherein the output stage driver is configured as a current-voltage conversion circuit, and an output voltage level of the output stage driver is adjusted by adjusting an output current level of the preceding stage driver. A signal transmission driver circuit, characterized in that: 5. The signal transmission driver circuit according to claim 1, wherein the output stage driver includes a feedback circuit for lowering an output impedance. 6. The signal transmission driver circuit according to claim 1, wherein the pre-stage driver includes a gain variable unit that adjusts a level of an input signal by the level adjustment unit, and an amplification unit that amplifies the input signal whose level has been adjusted. And a signal transmission driver circuit comprising: 7. The signal transmission driver circuit according to claim 1, wherein said pre-stage driver is configured as a current limiting inverter supplied with an input signal, and said current limiting inverter controls a current flowing by said level adjusting means. A signal transmission driver circuit wherein the output level is adjusted by adjusting the output level. 8. The signal transmission driver circuit according to claim 1, wherein an output of said output stage driver is changed depending on a series of digital values output in the past to obtain an effect of equalizing transmission path characteristics. A signal transmission driver circuit, characterized in that: 9. The signal transmission driver circuit according to claim 1, wherein a plurality of said pre-stage drivers are provided, said plurality of pre-stage drivers are connected to a common output stage driver, and said pre-stage drivers are connected to said pre-stage drivers by said output stage drivers. A signal transmission driver circuit, characterized in that data generated from a digital sequence output in the past is input to obtain an effect of equalizing transmission path characteristics. 10. The signal transmission driver circuit according to claim 9, wherein each of the plurality of pre-stage drivers has a predetermined coefficient, and multiplies the data generated from the digital sequence by a coefficient to supply the multiplied data to the output stage driver. A signal transmission driver circuit characterized in that: 11. The signal transmission driver circuit according to claim 1, wherein two of said first-stage drivers are provided, and one of said first-stage drivers delays a digital signal sequence input to said signal transmission driver circuit by one bit time. A signal transmission driver circuit characterized in that an effect of equalizing transmission path characteristics is obtained by inverting and inputting the inverted signal. 12. The signal transmission driver circuit according to claim 11, wherein said one pre-stage driver has a predetermined coefficient and is provided in parallel with the other pre-stage driver, and said one pre-stage driver controls said one bit time by said one pre-stage driver. A signal transmission driver circuit, characterized in that a signal delayed and inverted by a factor is multiplied by a coefficient and added to the output of the other preceding driver, thereby driving the output driver. 13. The signal transmission driver circuit according to claim 8, wherein the equalization effect of the transmission path characteristic is obtained by transmitting an output signal of the output stage driver via the transmission path. A signal transmission driver circuit for compensating attenuation of a high-frequency component when the signal is transmitted. 14. The signal transmission driver circuit according to claim 1, wherein a plurality of sets of said pre-stage drivers are provided, and said plurality of sets of pre-stage drivers are interleaved to perform parallel-serial conversion. Driver circuit for signal transmission. 15. The signal transmission driver circuit according to claim 1, wherein the output stage driver has a common-source push-pull structure using a pMOS transistor and an nMOS transistor. 16. The signal transmission driver circuit according to claim 15, wherein the output stage driver outputs an intermediate voltage substantially at the center between a high-potential power supply voltage and a low-potential power supply voltage.
A driver circuit for signal transmission, wherein a gate voltage of the pMOS transistor is set higher than the intermediate voltage and a gate voltage of the nMOS transistor is set lower than the intermediate voltage. 17. The signal transmission driver circuit according to claim 15, wherein a gate of said nMOS transistor is nMO.
Driven by a common drain circuit of the S transistor, and
A signal transmission driver circuit, wherein a gate of the pMOS transistor is driven by a grounded drain circuit of the pMOS transistor. 18. The signal transmission driver circuit according to claim 15, wherein the output stage driver uses a voltage lower by a predetermined voltage than the high-potential-side power supply voltage and a voltage higher by a predetermined voltage than the low-potential-side power supply voltage. A signal transmission driver circuit, which is adapted to be driven. 19. The signal transmission driver circuit according to claim 18, wherein the output stage driver has a replica driver, and the replica driver changes an intermediate voltage of a voltage for driving the output stage driver to the high potential side power supply voltage. And a signal transmission driver circuit that controls the voltage to match the intermediate voltage of the low-potential-side power supply voltage.