KR102253789B1 - Electronic interlocking system of independent two-channel structure and control method - Google Patents

Abstract

The present invention relates to an electronic interlocking system of an independent two-channel structure and a control method thereof and, more specifically, to an electronic interlocking system of an independent two-channel structure and a control method thereof about a method of synchronization and data comparison between channels/systems and a safety processing control method in case of inconsistency in comparison by configuring an electronic interlocking system by a dual system of an independent two-channel structure.

Description

Electronic interlocking system of independent two-channel structure and control method

The present invention relates to an independent two-channel structured electronic interlocking device and a control method, and more particularly, the present invention comprises an electronic interlocking device as an independent two-channel structured redundant system to provide synchronization and data comparison between channels and systems. The present invention relates to an independent two-channel electronic interlocking device and a control method for the method, and the control method for safety processing in case of comparison inconsistency.

The conventional electronic interlocking device configuration method applied in the railway field constitutes a dual system of 1st and 2nd systems.

Each system uses one CPU module to perform interlocking logic processing, compares the interlocking processing results performed by each system, and performs final output when they are the same.

If one system is in the OFF state or in a fault state, the other system operates independently without comparison processing.

A general electronic interlocking device is a device responsible for the safety of the final stage of train operation from a railroad signal, and it is required to deal with it because it is directly connected to a human accident when there is an incorrect control command or wrong output from the driver. When there is such a human error or system error (input or output error, etc.), the electronic interlocking device internally determines the error by interlocking logic processing and handles it to the safety side.

However, comparative logic processing is required to determine human or systemic errors. If input information or output information is compared with each other and output is performed only when they are identical, the possibility of an error can be minimized.

For this reason, in the conventional system, the system is configured as a dual system, and the possibility of errors is reduced by processing only the same cases through quarterly data comparison.

However, there is a problem in that a person with a disability handles it alone.

Korean Patent Registration No. 0945854 Korean Patent Publication No. 2007-0048891

The present invention has been made to solve the above problems, and is an independent two-channel electronic interlocking device that performs independent interlocking logic processing for each channel, and compares the interlocking processing results performed by each channel step by step, and termination of inconsistency. An object of the present invention is to provide an electronic interlocking device of an independent two-channel structure that implements blocking control.

An object of the present invention is to provide an independent two-channel structured electronic interlocking device that prevents the possibility of an error by configuring a dual system of an independent two-channel structure and performing comparison logic processing between channels in a single system even in the event of a one-quarter failure. have.

In addition, the present invention operates as a safety side by blocking the final output in case of a continuous comparison logic processing error or system failure, and performs a comparison process for each processing step between each channel, and when the processing result is inconsistent, a safety side process is performed. An object of the present invention is to provide an electronic interlocking device of an independent two-channel structure that can enhance safety by performing synchronization and comparison processing.

In order to solve the above problems, the present invention is in charge of interlocking logic processing, which is a core function of an electronic interlocking device, and when control information is received from CTC (Centralized Traffic Control) or display control unit, internal interlocking logic processing is performed and the result is transmitted to the input/output unit. An interlocking logic unit; An input/output unit in charge of digital input/output processing for the input/output module, and controlling a corresponding output module according to a processing result of the interlocking logic unit to perform digital output; Including; a relay rack for energizing a corresponding relay by the digital output of the input/output unit and for operating a field facility including a signal device or a line switcher according to the relay contact condition, and the operation state of the field facility changes the relay rack of the relay rack. When excited and the status is input to the input module of the input/output unit according to the relay contact condition, the input/output unit transmits this status to the interlocking logic unit, and the interlocking logic unit that receives this information performs interlocking logic processing according to the internal interlocking condition and then displays it. The information is transmitted to the CTC and the display control unit.

The interlocking logic unit includes an interlocking logic unit CPU module responsible for processing interlocking logic, which is a core function of an electronic interlocking device; A communication module in charge of an external communication function; and, when data synchronization or comparison logic processing results in the CPU module of the interlocking logic unit or the CPU module of the input/output unit are inconsistent, channel A or B of the input/output unit blocks the final output currently being output. Fault signal is output from the channel CPU, and the final output is controlled as'L' in AND logic, and the final output is blocked by the cut-off unit.

The input/output unit includes an input/output CPU module and an input/output module for controlling the input/output module and in charge of digital input/output processing, and the data synchronization or comparison logic processing result is inconsistent in the CPU module of the interlocking logic unit or the CPU module of the input/output unit. Then, a fault signal is output from the A-channel or B-channel CPU of the input/output unit to block the final output currently being output, and the final output is controlled to'L' in the AND logic, and the final output is blocked by the blocking unit.

When the channel A CPU and the channel B CPU of the interlocking logic unit receive the status input data of the field facility from the input/output unit, the first synchronization step checks whether the digital signal value received from the counterpart CPU and the value outputted by itself match. In case of disagreement, the digital input value is read repeatedly for the wait time and compared with the output value. If the synchronization value is matched, the input data is exchanged with each other, and if there is a discrepancy more than 3 times, enters the safe mode, and if the input data comparison matches, the second For the synchronization step, the digital signal value is input from the counterpart CPU, checks whether the received digital signal value matches the value output by itself, and if it does not match, repeats the digital input value during the Wait time and compares it with the output value. If the synchronization values match, interlocking logic processing is performed, and when the interlocking logic processing is completed, a digital signal value is input from the counterpart CPU for the third synchronization step, and the input digital signal value and the value output by itself are checked to see if they match. In case of inconsistency, the digital input value is read repeatedly for the wait time and compared with the output value. If the synchronization value matches, the output data is exchanged. If the comparison result is not matched more than 3 times, it enters the safe mode. It sends data to the input/output unit and receives the first input data.

In the present invention, the channel A CPU and the channel B CPU of the interlocking logic unit receive state input data of the field facility from the input/output unit; A first synchronization step in which the channel A CPU receives a digital signal value for synchronization with the channel B CPU; It checks whether the received digital signal value and the value outputted by itself match, and if it does not match, it reads the digital input value repeatedly for the wait time and compares it with the output value. If the synchronization value matches, the input data is exchanged and compared. step; If the comparison result does not match, data exchange is performed up to 3 times, and if the comparison result is not matched more than 3 times, entering a safe mode; Receiving a digital input from the counterpart CPU for synchronization in a second step if the input data comparison matches; Checking whether the received digital signal value and the self-output value match, and if not, repeatedly reading the digital input value for a wait time and comparing the output value with the output value, and performing interlocking logic processing if the synchronization value matches; If the synchronization values do not match for a specified time, moving to a first synchronization step and performing synchronization again; Receiving a digital input from a counterpart CPU for a third synchronization step when the interlocking logic processing is completed; It checks whether the received digital signal value and the value outputted by itself match, and if it does not match, it reads the digital input value repeatedly for a wait time and compares it with the output value. If the synchronization value matches, the output data is exchanged and compared. step; If the comparison result of the output data does not match, data exchange is performed up to 3 times to check whether the data is matched, and if 3 or more times do not match, entering a safe mode; If the synchronization values do not match for a specified time, moving to the first synchronization step and performing synchronization again; And if the output data match, transmitting the data to the input/output unit and moving to the first step.

A first synchronization step in which the channel A CPU and the channel B CPU of the input/output unit receive output data from the interlocking logic unit, and the channel A CPU receives a digital input from the channel B CPU for synchronization with the channel B CPU; Checking whether the received digital signal value and the self-output value match, and if not, repeatedly reading the digital input value for a wait time and comparing the output value with the output value; Checking whether the data is an output cut-off request if the synchronization value coincides, and performing final output cut-off control when the data is an output cut-off request to cut off the output of the output module; Setting a comparison fail to a non-matching output port when the output data is not matched three or more times in exchange for comparison by exchanging with each other if the blocking request is not made; Receiving a digital input from the counterpart CPU for synchronization in a second step if the output data comparison is matched; Steps to check whether the received digital signal value and the self-output value match, and if it does not match, read the digital input value repeatedly for the wait time and compare it with the output value, and if the synchronization value matches, output the output data to the output module. ; If the synchronization values do not match for a specified time, moving to the first synchronization step and performing synchronization again; Receiving a digital input from the counterpart CPU for synchronization in a third step when processing of the output data is completed; Steps to check whether the received digital signal value and the self-output value match, and if it does not match, read the digital input value repeatedly for a wait time and compare it with the output value, and if the synchronization value matches, exchange and compare the input data with each other. ; In the comparing step, if the comparison result does not match, data exchange is performed up to 3 times to check whether it is matched, and if it does not match more than 3 times, a comparison fail is set for the inconsistent input port, and if the synchronization value does not match for the specified time, step again. Moving to 1 and performing synchronization again; And if the input data match, transmitting the input data together with the input and output comparison results to the interlocking logic unit and moving to the first step.

In the present invention, when the CPU module of the input/output unit operates normally, the output is operated to operate'VCR_A' Relay and'VCR_B' Relay, which are vital cut-off control relays; +24V power is supplied to the first output port of the first output module through the relay operation condition of the output module of the I/O part, and the outputs of the first output port of channel A and channel B of the first output module are'VRD_A' Relay and'VRD_B', respectively. Operating the relay; After the first output port, the output module is supplied with +24V power according to the operating conditions of VRD_A and VRD_B, and the output of each output port of channels A and B after the first output port is configured in a serial condition. A step in which the final'R' relay is operated only when the output state of is output identically; When the CPU module of the I/O part receives an output blocking request from the interlocking logic part, it controls the Safe output control signal to drop the'VCR_A' Relay and the'VCR_B' Relay, or if the channel itself detects a failure, the VCR_A'Relay of the detected channel Or dropping the'VCR_B' Relay; Since the VCR_A'Relay 62 or the'VCR_B'Relay 64 falls and the operation condition 65 is not satisfied, the power supply to the first output module is cut off, and VRD_A and VRD_B Realy (66) are operated by the first output module. , The step of dropping 67); including, the output state of the output module is blocked even when the operating R Relay is dropped or the individual output port circuit of the output module is disabled as all outputs currently being output are cut off under a certain condition. If they are not the same, the final output is blocked by the AND structure to ensure a safe state.

Inside the CPU module of the input/output unit, a digital output circuit capable of controlling an output when switching to a safe state is built for each channel, and a signal of the digital output circuit is input to a watchdog circuit to periodically control the signal.

The present invention made as described above enables safer processing because the interlocking processing results are compared and processed according to the comparison logic between two channels as a single system even in a state in which one system is faulty or power is OFF.

In addition, through the present invention, it is possible to reinforce safety by processing comparative logic even in case of failure of one system in an electronic interlocking device having a dual system structure.

In addition, through the present invention, it is possible to process the safety side by means of a Safe output control signal in case of a failure of either channel by a two-channel CPU.

In addition, the present invention can enhance safety by configuring an output module output port and a final output blocking method according to an operating condition of a vital relay of a CPU module.

1 is an overall system configuration and operation process according to an embodiment of the present invention.
2 is a diagram illustrating an entire internal configuration of an electronic interlocking device according to an embodiment of the present invention.
3 is a diagram illustrating a configuration of communication and digital signals between channels A/B of a CPU module according to an embodiment of the present invention.
4 is a flowchart illustrating synchronization and comparison logic processing between channels of a CPU module of an interlocking logic unit according to an embodiment of the present invention.
5 is a flowchart illustrating synchronization and comparison logic processing between channels of a CPU module of an input/output unit according to an embodiment of the present invention.
6 is a block diagram illustrating an output configuration of an output module of an input/output unit and a final output blocking method according to an embodiment of the present invention.
7 is a block diagram of an overall system structure of an electronic interlocking device (EIS) according to an embodiment of the present invention.

In order to fully understand the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments of the present invention may be modified in various forms, and the scope of the present invention should not be construed as being limited to the embodiments described in detail below. This embodiment is provided to more completely explain the present invention to those of ordinary skill in the art. Accordingly, the shape of the element in the drawings may be exaggerated to emphasize a clearer description. It should be noted that in each drawing, the same member may be indicated by the same reference numeral. In addition, detailed descriptions of known functions and configurations that are determined to unnecessarily obscure the subject matter of the present invention will be omitted.

Referring to FIG. 1, the entire system configuration and operation process of the electronic interlocking device of an independent two-channel structure according to the present invention will be described as follows.

The electronic interlocking device is composed of an interlocking logic unit 11 and an input/output unit 12, and transmits and receives information through an EtherCAT communication method.

The interlocking logic unit 11 is in charge of interlocking logic processing, which is a core function of the electronic interlocking device, and the input/output unit 12 is in charge of digital input/output processing for the input/output module.

When control information is received from the CTC 13 or the display control unit 14, the interlocked logic unit 11 performs internal interlocking logic processing and transmits the result to the input/output unit. Control to make digital output.

The corresponding relay of the relay rack 15 is excited by the digital output of the input/output unit 12, and the field equipment 16 such as a signal device or a line switch is operated according to the relay contact condition.

Conversely, the operating state of the field facility 16 energizes the relay of the relay rack 15, and the state is input to the input module of the input/output unit 12 according to the relay contact condition.

The input/output unit 12 transmits this state to the interlocking logic unit 11, and the interlocking logic unit 11 receiving this information performs interlocking logic processing according to the internal interlocking condition, and then sends the display information to the CTC 13 and It is transmitted to the display control unit 14.

2 is an overall internal configuration diagram for implementing the present invention. The electronic interlocking device system is composed of an interlocking logic unit 11 and an input/output unit 12, and the interlocking logic unit 11 includes interlocking logic, which is a core function of the electronic interlocking device. An interlocking logic unit CPU module 21 in charge of processing and a communication module 33 in charge of external communication functions are installed, and in the input/output unit 12, the input/output unit CPU module ( 22) and an input/output module 23.

The CPU modules 21 and 22 are configured with the same H/W of a two-channel structure.

That is, the EtherCAT master (EMC) 24 is installed on the CPU module 21 of the interlocking logic unit 11, and the Ethercat slave (ESC) 25 is installed on the CPU module 22 of the input/output unit 12. As a result, information is transmitted and received with each other using the EtherCAT communication method.

In addition, the CPU module 21 of the interlocking logic unit 11 internally performs data synchronization and comparison logic processing unit 26 for interlocking logic processing between channels to ensure safety.

Similarly, the CPU module 22 of the input/output unit 12 internally performs the comparison logic processing again before controlling the final input/output module 23 by synchronizing the input information and output information between channels and performing the comparison logic processing unit 27. To ensure safety.

In addition, if the data synchronization or comparison logic processing results in the CPU module 21 of the interlocking logic unit 11 or the CPU module 22 of the input/output unit 12 are inconsistent, the input/output unit blocks the final output 28 currently being output. Fault signal (Active'L') is output (29) from A-channel CPU (20-1) or B-channel CPU (20-2), and the final output is controlled as'L' in the logic composed of AND structure. The output is blocked by the blocking unit 30.

In addition, the CPU module 21 of the interlocking logic unit 11 also performs data synchronization and comparison logic processing 31 with the other system, thus performing the double safety processing.

This series of processing is performed in the same manner in the counterpart system 32, and error processing can be prevented because the single system performs synchronization and comparison logic processing between channels even when one system fails.

3 is a diagram illustrating a configuration of communication and digital signals between channels A/B of a CPU module.

In one CPU module (21, 22), the independent type of CPU (20-1, 20-2) circuit is composed of two channels.

Data is exchanged between the two channels of the CPU modules (21, 22) through SPI communication (35), and each two ports of the digital input (37) and the output (36) are connected to each other for synchronization for each processing step for internal processing. It connects and outputs a digital signal at each processing step, and performs synchronization by receiving a relative output state.

4 is a flowchart of synchronization of processing steps between channels of a CPU module of an interlocking logic unit and comparison logic processing.

The channel A CPU 20-1 and the channel B CPU 20-2 of the interlocking logic unit 11 receive state input data of the field facility from the input/output unit (S41).

In the first synchronization step (S42), a digital output '01' is output for synchronization with the counterpart CPU, and a digital input is received from the counterpart CPU.

In addition, it checks whether the received digital signal value and the value outputted by itself match, and if it does not match, it reads the digital input value repeatedly during the wait time and compares it with the output value. If the synchronization values match, the input data is exchanged and compared.

If the comparison results do not match, data is exchanged up to 3 times to check whether they match. At this time, if there is a discrepancy more than 3 times, it enters the safe mode.

If the input data comparison matches, a digital output '10' is output for the second stage of synchronization (S43), and a digital input is received from the counterpart CPU.

It checks whether the received digital signal value and the value outputted by itself match, and if it does not match, it reads the digital input value repeatedly for Wait time and compares it with the output value. If the synchronization values match, interlocking logic processing is performed.

If the synchronization value does not match for the specified time, it moves to step 1 (S41) again, and synchronization is performed again.

And when the interlocking logic processing is completed, the digital output '11' is output for the third step of synchronization (S44), and a digital input is received from the counterpart CPU.

In this way, it checks whether the received digital signal value and the value outputted by itself match, and if it does not match, it reads the digital input value repeatedly during the wait time and compares it with the output value. If the synchronization values match, the output data is exchanged and compared.

If the above comparison results do not match, data is exchanged up to three times to check whether they match. If there is a discrepancy more than 3 times, it enters the safe mode.

If the synchronization values do not match for the specified time, the process moves to step 1 (S41) again to perform synchronization again.

And if the output data match, this data is transmitted to the input/output unit (S45), and the process moves to the first step.

5 is a flowchart of synchronization of processing steps between channels of a CPU module of an input/output unit and comparison logic processing.

When channel A CPU and channel B CPU of the input/output unit receive output data from the interlocking logic unit 11 (S51), they output digital output '01' for synchronization with the counterpart CPU in the first synchronization step (S52), and then output digital output from the counterpart CPU (S52). It receives input.

It checks whether the received digital signal value and the value outputted by itself match, and if it does not match, it reads the digital input value repeatedly for Wait time and compares it with the output value.

If the synchronization values match, it checks whether the data is an output cutoff request, and if the output cutoff request is performed, the output of the output module is cut off by performing final output cutoff control.

If the blocking request is not made, the output data is exchanged and compared (S53). If the comparison results do not match, data is exchanged up to 3 times to check whether they match.

In this case, if there is a discrepancy more than 3 times, set the comparison fail to the mismatched output port.

If these output data comparisons match, a digital output '10' is output for the second stage of synchronization (S54) and a digital input is received from the counterpart CPU.

It checks whether the received digital signal value and the value outputted by itself match, and if it does not match, it reads the digital input value repeatedly for Wait time and compares it with the output value. If the synchronization values match, the output data is output to the output module.

If the synchronization values do not match for the specified time, the process moves to step 1 (S51) again to perform synchronization again.

And when the processing of the output data is completed, the digital output '11' is output for the third step synchronization (S55), and a digital input is received from the counterpart CPU.

It checks whether the received digital signal value and the value outputted by itself match, and if it does not match, it reads the digital input value repeatedly for Wait time and compares it with the output value. If the synchronization values match, the input data is exchanged and compared.

If these comparison results do not match, data is exchanged up to 3 times to check whether they match. If there is a discrepancy more than 3 times, set the comparison fail for the inconsistent input port. If the synchronization values do not match for the specified time, the process moves to step 1 (S51) again to perform synchronization again.

If the input data match, the input data is transmitted to the interlocking logic unit together with the input and output comparison results, and the process moves to the first step.

6 is a block diagram of an output module output configuration of an input/output unit and a final output blocking method.

Inside the CPU module of the input/output unit, a digital output circuit (Safe output control) 61, 63 that can control the output when switching to a safe state is built for each channel.

This signal is made up of a watchdog circuit so that the output operates normally only when the signal is controlled periodically.

When the CPU module operates normally, the output is activated to operate (excitation) the'VCR_A' Relay 62 and the'VCR_B' Relay 64, which are vital cut-off relays (VCR).

Through this relay operation condition (65), +24V power is supplied to the first output port of the first output module. In addition, the outputs of the first output port of channel A and channel B of the first output module operate'VRD_A' Relay (66) and'VRD_B' Relay (67), respectively.

After the first output port, the output module is supplied with +24V power according to the operating conditions 68 of VRD_A and VRD_B.

In addition, since the output of each output port of channel A and channel B after the first output port is composed of serial (AND) condition (69), the final'R' relay (70) only when the output status of channels A and B are output identically. Is activated.

When an output blocking request is received from the interlocking logic unit in the CPU module of the input/output unit, the'VCR_A' Relay (62) and the'VCR_B' Relay (64) are dropped by controlling the Safe output control signal.

Alternatively, if the channel itself detects a failure, the VCR_A'Relay 62 or the'VCR_B'Relay 64 of the detected channel is dropped.

Since the VCR_A'Relay 62 or the'VCR_B'Relay 64 falls and the operation condition 65 is not satisfied, the power supply to the first output module is cut off, and VRD_A and VRD_B Realy (66) are operated by the first output module. , 67) will fall.

Under the condition (68), all outputs currently being output are cut off, and the operating R Relay (70) falls to secure a safety state.

Alternatively, even when the individual output port circuit of the output module is disabled, the output state of the output module is not the same, so the final output is blocked by the AND structure 69 to secure a safety state.

Hereinafter, the inherent reliability value of EIS is derived based on the predicted failure rate (unique MTBF) for each module.

As a derivation technique, it is calculated using the following reliability approximation Equation 1 through RBD.

(Where n = number of units, λ = failure rate of each module, q = number of units that maintain a function after a defect occurs)

The overall system structure of the electronic interlocking device (EIS) according to the present invention is shown in FIG. 7, and accordingly, a Reliability Block Diagram (RBD) was performed.

As shown in Table 1 below, the CPU modules 21 and 22 of the interlocking logic unit (ILS) are applied as FSC202. Therefore, the reliability values of the EIS CPU modules 21 and 22 were calculated based on the existing failure rate prediction data of the FSC202.

The EIS CPU modules 21 and 22 excluded the following blocks that do not affect the operation in the existing FSC202 from the prediction target.

The EIS reliability result value according to the station size in which the EIS is installed is presented. EIS is classified as shown in Table 2 below according to the station scale, that is, the number of inputs/outputs.

The configuration modules of EIS installed in small stations are shown in Table 3 below.

[Small station EIS]

FR: 3.6037X10-5/h

MTBF: 27,749[time]

The configuration modules of EIS installed in mid-sized stations are shown in Table 4 below.

[Medium station EIS]

FR: 2.2204X10-4/h

MTBF: 4,504[time]

The configuration modules of EIS installed in large stations are shown in Table 5 below.

[Large station EIS]

FR: 4.0274X10-4/h

MTBF: 2,483[time]

In conclusion, as a result of deriving the device failure rate for each module and performing RBD, the reliability of the EIS is shown in Table 6 below.

Therefore, the present invention compares and processes interlocking processing results by comparison logic between two channels as a single system even in a state in which one system is faulty or power is OFF. Processing is possible.

11: interlocking logic unit
12: input/output unit
20-1, 20-2: CPU
21: Interlocking logic unit CPU module
22: I/O unit CPU module
23: input/output module of the interlocking logic unit
32: Electronic interlocking device 2nd series

Claims (8)

An interlocking logic unit 11 in charge of processing interlocked logic, which is a core function of the electronic interlocking device, and when control information is received from the CTC 13 or the display control unit 14, performs internal interlocking logic processing and transmits the result to the input/output unit;
An input/output unit 12 in charge of digital input/output processing for the input/output module and controlling the corresponding output module according to the processing result of the interlocking logic unit 11 to perform digital output;
Including; a relay rack 15 for energizing a corresponding relay by the digital output of the input/output unit 12 and for operating the field equipment 16 including a signal device or a line switcher according to the relay contact condition.
When the operating state of the field facility 16 excites the relay of the relay rack 15 and the state is input to the input module of the input/output unit 12 according to the relay contact condition,
The input/output unit 12 transmits this state to the interlocking logic unit 11, and the interlocking logic unit 11 receiving this information performs interlocking logic processing according to the internal interlocking condition, and then sends the display information to the CTC 13 And transmission to the display control unit (14). The method of claim 1,
The interlocking logic unit 11 includes an interlocking logic unit CPU module 21 for processing interlocking logic, which is a core function of an electronic interlocking device; And
Includes; a communication module 33 in charge of an external communication function,
When the data synchronization or comparison logic processing results in the CPU module 21 of the interlocking logic unit 11 or the CPU module 22 of the input/output unit 12 are inconsistent, the input/output unit blocks the final output 28 currently being output. Independent 2-channel electronic interlocking, characterized in that a fault signal is output (29) from the A-channel or B-channel CPU, and the final output is controlled to'L' in the AND logic, and the final output is blocked by the blocking unit (30). Device. The method of claim 1,
The input/output unit 12 includes an input/output unit CPU module 22 and an input/output module 23 for controlling the input/output module and in charge of digital input/output processing, and
When the data synchronization or comparison logic processing results in the CPU module 21 of the interlocking logic unit 11 or the CPU module 22 of the input/output unit 12 are inconsistent, the input/output unit blocks the final output 28 currently being output. Independent two-channel electronic interlocking, characterized in that a fault signal is output (29) from the A-channel or B-channel CPU and the final output is controlled to'L' in the AND logic, and the final output is blocked by the blocking unit (30) Device. The method of claim 1,
When the channel A CPU and the channel B CPU of the interlocking logic unit 11 receive the status input data of the field facility from the input/output unit (S41), the digital signal value received from the counterpart CPU in the first synchronization step (S42) It checks whether the output value of and itself is identical, and if it does not match, reads the digital input value repeatedly for the wait time and compares it with the output value. If the synchronization value matches, exchanges the input data with each other and enters the safe mode when there is a discrepancy more than 3 times. and,
If the input data comparison matches, it receives a digital signal value from the counterpart CPU for the second synchronization step (S43), checks whether the received digital signal value matches the value output by itself, and if it does not match, repeats the digital input for the wait time. It reads the value and compares it with the output value, and if the synchronization value matches, it performs interlocking logic processing.
When the interlocking logic processing is completed, the digital signal value is received from the counterpart CPU for the third synchronization step (S44), and it checks whether the received digital signal value matches the value output by itself. If the synchronization value is identical by reading the input value and comparing the output value, the output data is exchanged with each other, and if the comparison result is inconsistent more than 3 times, it enters the safe mode, and if the output data matches, it transmits this data to the input/output unit (S45). Independent two-channel electronic interlocking device, characterized in that for receiving the first input data (S41). The channel A CPU and the channel B CPU of the interlocking logic unit 11 receive (S41) state input data of the field facility from the input/output unit;
A first synchronization step in which the channel A CPU receives a digital signal value for synchronization with the channel B CPU (S42);
It checks whether the received digital signal value and the value outputted by itself match, and if it does not match, it reads the digital input value repeatedly for the wait time and compares it with the output value. If the synchronization value matches, the input data is exchanged and compared. step;
If the comparison result does not match, data exchange is performed up to 3 times, and if the comparison result is not matched more than 3 times, entering a safe mode;
Receiving a digital input from the counterpart CPU for a second synchronization step (S43) if the input data comparison is matched;
Checking whether the digital signal value received digitally and the value outputted by the digital signal match, and if not, repeatedly reading the digital input value for a wait time and comparing the output value with the output value, and performing interlocking logic processing if the synchronization value matches;
If the synchronization values do not match for a specified time, moving to a first synchronization step (S42) and performing synchronization again;
Receiving a digital input from a counterpart CPU for a third synchronization step (S44) when the interlocking logic processing is completed;
It checks whether the received digital signal value and the value outputted by itself match, and if it does not match, it reads the digital input value repeatedly for a wait time and compares it with the output value. If the synchronization value matches, the output data is exchanged and compared. step;
If the comparison result of the output data does not match, data exchange is performed up to 3 times to check whether the data is matched, and if 3 or more times do not match, entering a safe mode;
If the synchronization values do not match for the specified time, moving to the first synchronization step (S42) and performing synchronization again;
When the output data match, transmitting the data to the input/output unit (S45) and moving to the first step. The method of claim 5,
When the channel A CPU and the channel B CPU of the input/output unit receive output data from the interlocking logic unit 11 (S51), the channel A CPU receives a digital input from the channel B CPU for synchronization with the channel B CPU (S52). );
Checking whether the received digital signal value and the self-output value match, and if not, repeatedly reading the digital input value for a wait time and comparing the output value with the output value;
Checking whether the data is an output cut-off request if the synchronization value coincides, and performing final output cut-off control when the data is an output cut-off request to cut off the output of the output module;
If not blocked, the output data is exchanged and compared (S53). If there is a discrepancy more than 3 times, setting Fail to the mismatched output port;
Receiving a digital input from the counterpart CPU for a second synchronization step (S54) if the output data comparison matches;
Steps to check whether the received digital signal value and the self-output value match, and if it does not match, read the digital input value repeatedly for the wait time and compare it with the output value, and if the synchronization value matches, output the output data to the output module. ;
If the synchronization values do not match for the specified time, moving to the first synchronization step (S52) and performing synchronization again;
Receiving a digital input from the counterpart CPU for a third synchronization step (S55) when processing of the output data is completed;
Steps to check whether the received digital signal value and the self-output value match, and if it does not match, read the digital input value repeatedly for a wait time and compare it with the output value, and if the synchronization value matches, exchange and compare the input data with each other. ;
In the comparing step, if the comparison result does not match, data exchange is performed up to 3 times to check whether it is matched, and if it does not match more than 3 times, Fail is set for the inconsistent input port, and if the synchronization value does not match for the specified time, step S51 again. Moving to and performing synchronization again;
When the input data match, transmitting the input data together with the input and output comparison results to the interlocking logic unit, and moving to the first step. The method of claim 5,
When the CPU module of the input/output unit operates normally, an output is operated to operate'VCR_A' Relay 62 and'VCR_B' Relay 64, which are vital cut-off relays (VCR);
+24V power is supplied to the first output port of the first output module through the relay operation condition (65) of the output module of the input/output unit, and the outputs of the first output ports of channel A and channel B of the first output module are respectively'VRD_A' relays. Operating (66) and'VRD_B' Relay (67);
After the first output port, the output module is supplied with +24V power according to the operation condition (68) of VRD_A and VRD_B, and the output of each output port of channel A and channel B after the first output port is serial (AND) condition (69 ), the final'R' Relay 70 is operated only when the output states of channels A and B are output identically;
When the CPU module of the I/O part receives an output blocking request from the interlocking logic part, it controls the Safe output control signal to drop the'VCR_A' Relay (62) and the'VCR_B' Relay (64), or detects when the channel itself detects a failure. Dropping the VCR_A'Relay 62 or the'VCR_B'Relay 64 of the selected channel;
Since the VCR_A'Relay 62 or the'VCR_B'Relay 64 falls and the operation condition 65 is not satisfied, the power supply to the first output module is cut off, and VRD_A and VRD_B Realy (66) are operated by the first output module. Including; step of falling, 67),
The AND structure when the output status of the output module is not the same even when the operating R Relay (70) falls or the individual output port circuit of the output module is disabled because all outputs currently being output are blocked by a certain condition (68). Independent two-channel structure electronic interlocking device control method, characterized in that the safety state is secured by blocking the final output by (69). The method of claim 7,
Inside the CPU module of the input/output unit, a digital output circuit (Safe output control) 61, 63 capable of controlling the output when switching to a safe state is built for each channel, and the signal of the digital output circuit is a watchdog. An independent two-channel structure electronic interlocking device control method, characterized in that it is input to a circuit and periodically controls a signal.

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