KR102248877B1 - Liquid crystal display device and method for fabricating the same - Google Patents

Abstract

In the present invention, a lower substrate and an upper substrate having an image display portion and a bezel portion defined opposite to each other, a thin film transistor and a color filter provided on the lower substrate, and provided on an upper portion of the color filter, and in contact with the thin film transistor. A liquid crystal display device including a pixel electrode, a plurality of circuit patterns provided on a bezel part of the lower substrate, and a dummy pattern provided between circuit patterns of the bezel part is provided.

Description

Liquid crystal display device and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving visibility of an outer bezel part without a black matrix or a black column spacer, and a manufacturing method thereof.

In general, a liquid crystal display device expresses an image using optical anisotropy and birefringence characteristics of liquid crystal molecules. When an electric field is applied, the arrangement of liquid crystals is changed, and light transmission characteristics are also changed according to the changed arrangement direction of the liquid crystals.

In a liquid crystal display, an electric field generated by placing two substrates on which each field generating electrode is formed so that the surfaces on which the two electrodes are formed are opposite to each other, injecting a liquid crystal material between the two substrates, and then applying a voltage to the two electrodes By moving the liquid crystal molecules, it is a device that expresses an image with a light transmittance that varies accordingly.

In the case of such a general liquid crystal display, a thin film transistor is formed on the lower substrate, a black matrix and a color filter are formed on the upper substrate, and the lower substrate and the upper substrate are bonded to face the pattern surface. Thus, a liquid crystal screen is implemented by injecting liquid crystals between them.

In addition, ITO (Indium Tin Oxide) is formed on the rear surface of the upper substrate, and a mechanism part and a ground line are formed to be used as an ESD path of the panel.

Moreover, the bezel part BA at the outer part of the panel is formed by using the black matrix formed on the upper substrate.

However, in the case of such a general liquid crystal display device, since a separate mask and material for forming the black matrix are additionally required when the black matrix is used, the manufacturing process becomes complicated and production efficiency is lowered.

In order to replace the black matrix having such a problem, a liquid crystal display device having a color filter on transistor (COT) structure using a black column spacer has been proposed. In this case, the liquid crystal display device having a color filter on transistor (COT) structure refers to a liquid crystal display device in which a color filter is formed on a lower substrate instead of an upper substrate.

However, in the case of a liquid crystal display having a color filter on transistor (COT) structure using a black column spacer, a separate mask process is required to form an additional column spacer (CS).

A conventional liquid crystal display having a COT structure that does not use a black column spacer requiring a separate mask process will be described with reference to FIGS. 1 to 3.

1 is a schematic plan view of a liquid crystal display according to the prior art, and schematically shows a bezel part provided outside a panel.

FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1 and is a schematic cross-sectional view of a liquid crystal display device having a COT structure according to the prior art.

3 is a plan view schematically illustrating driving circuit patterns of a bezel part of a panel of a liquid crystal display according to the prior art.

The liquid crystal display device 10 according to the prior art, as shown in FIGS. 1 and 2, includes an image display unit AA and a bezel unit BA provided at an outer periphery of the image display unit AA.

The liquid crystal display device 10 according to the prior art, as shown in FIG. 2, includes a lower substrate 11 having a thin film transistor array and a color filter formed thereon, and an upper substrate having a black pattern and a common electrode (not shown). 41).

In detail, the switching region (not shown) of the display unit AA of the lower substrate 11 includes a gate electrode 13, a semiconductor layer 17, a source electrode 19, and a drain electrode 21. A thin film transistor T is formed, and a color filter 25 and a pixel electrode 31 contacting the drain electrode 21 are formed in a pixel region (not shown) of the display unit AA.

Column spacers 35 are respectively formed on the lower substrate 11 to correspond to portions of the thin film transistor T and the pixel region (not shown).

A lower alignment layer (not shown) is formed on the lower substrate 11 including the column spacers 35.

Further, circuit patterns 33 used for the GIP driving circuit are formed on the bezel part BA of the lower substrate 11.

Meanwhile, a black matrix (not shown) is formed in a region of the upper substrate 41 corresponding to the thin film transistor T, a gate line (not shown), and a data line (not shown).

In addition, a transparent common electrode (not shown) is formed on the front surface of the upper substrate 41, and a column spacer (not shown) corresponds to a portion of the thin film transistor T and the pixel region (not shown) on the common electrode (not shown). 35) is formed.

An upper alignment layer (not shown) is formed on the entire surface of the upper substrate 41 on which the column spacers 35 are formed.

Moreover, a liquid crystal layer (not shown) is interposed between the lower substrate 11 and the upper substrate 41, and a seal pattern 51 is formed at the edge between the lower substrate 11 and the upper substrate 41. Formed to seal the liquid crystal layer (not shown).

As described above, in the case of a liquid crystal display having a COT structure according to the prior art, the problem of adding a new material separately has been solved because the black column spacer previously used is not used. The circuit patterns located at) are observed with the naked eye of the observer, thereby causing a visual perception problem of the bezel part.

An object of the present invention is to provide a liquid crystal display device capable of improving the visibility of a bezel part BA outside a panel without a black matrix or a black column spacer, and a method of manufacturing the same.

In order to solve the above-described problems, in one aspect, the present invention provides a lower substrate and an upper substrate which are bonded to face each other and define an image display portion and a bezel portion, a thin film transistor and a color filter provided on the lower substrate, and the color filter. A liquid crystal display device including a pixel electrode provided on the upper side of and contacting the thin film transistor, a plurality of circuit patterns provided on the bezel part of the lower substrate, and a dummy pattern provided between the circuit patterns of the bezel part. Can provide.

In such a liquid crystal display device, the dummy pattern may be formed of the same material layer as the pixel electrode.

In such a liquid crystal display device, the dummy pattern may be independently separated from the circuit patterns of the lower substrate.

In such a liquid crystal display device, a dummy pattern may be additionally formed on a front surface of another area of a bezel portion in which the circuit patterns are not provided.

In another aspect, the present invention provides a lower substrate and an upper substrate in which an image display portion and a bezel portion are defined, forming a thin film transistor and a color filter on the lower substrate, and forming a planarization film on the color filter. And forming a pixel electrode on the planarization layer in contact with the thin film transistor, and forming a plurality of circuit patterns on the planarization layer corresponding to the bezel and on the planarization layer between the circuit patterns. It is possible to provide a method of manufacturing a liquid crystal display device including the step of forming a dummy pattern on the screen.

In such a method of manufacturing a liquid crystal display, the dummy pattern may be formed of the same material layer as the pixel electrode.

In such a method of manufacturing a liquid crystal display, the dummy pattern may be additionally formed on the entire surface of a region in which the circuit pattern is not formed among the bezel portions of the lower substrate.

In this method of manufacturing a liquid crystal display device, the dummy pattern may be independently separated from circuit patterns of the lower substrate.

The liquid crystal display according to the present invention and a manufacturing method thereof include forming a dummy pattern between circuit patterns provided in a bezel part outside a panel without a black matrix and a black column spacer, and forming a front surface of another area of the bezel part in which the circuit patterns are not formed. By additionally forming a dummy pattern on the panel, the visibility of the bezel part outside the panel can be improved.

1 is a schematic plan view of a liquid crystal display according to the prior art, and schematically shows a bezel part provided outside a panel.
FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1 and is a schematic cross-sectional view of a liquid crystal display device having a COT structure according to the prior art.
3 is a plan view schematically illustrating driving circuit patterns of a bezel part of a panel of a liquid crystal display according to the prior art.
4 is a schematic cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention.
5 is a plan view schematically illustrating driving circuit patterns and dummy patterns of a bezel part of a panel of a liquid crystal display according to an exemplary embodiment of the present invention.
6A to 6H are cross-sectional views illustrating a manufacturing process of a liquid crystal display according to an exemplary embodiment.
7 is a schematic cross-sectional view of a liquid crystal display according to another exemplary embodiment of the present invention.
8 is a plan view schematically illustrating a dummy pattern provided on a front surface of a bezel part outside a panel of a liquid crystal display according to another exemplary embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail through exemplary drawings. In adding reference numerals to elements of each drawing, it should be noted that the same elements are assigned the same numerals as possible, even if they are indicated on different drawings. In addition, in describing the embodiments of the present invention, when it is determined that a detailed description of a related known configuration or function may obscure the subject matter of the present invention, a detailed description thereof will be omitted.

In addition, in describing the constituent elements of the invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are for distinguishing the constituent element from other constituent elements, and the nature, order, or order of the constituent element is not limited by the term. When a component is described as being "connected", "coupled" or "connected" to another component, the component may be directly connected or connected to that other component, but another component between each component It will be understood that elements may be “connected”, “coupled” or “connected”. In the same context, when it is described that a component is formed "above" or "below" another component, the component is all formed directly on the other component or indirectly through another component. It should be understood as including.

A liquid crystal display according to an embodiment of the present invention will be described with reference to FIGS. 4 and 5 as follows.

4 is a schematic cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a plan view schematically illustrating driving circuit patterns and dummy patterns of a bezel part of a panel of a liquid crystal display according to an exemplary embodiment of the present invention.

The liquid crystal display device 100 having a COT structure according to an embodiment of the present invention includes an image display unit AA in which an image is implemented, and an outer edge portion of the image display unit AA, as shown in FIGS. 4 and 5. It is divided into a bezel part (BA).

A seal pattern 151 for bonding the lower substrate 101 and the upper substrate 141 is provided on the bezel portion BA positioned outside the image display unit AA. Further, GIP driving circuit patterns 127 are provided on the lower substrate 101 corresponding to the bezel part BA, and a dummy pattern 129 is provided between the circuit patterns 127.

In more detail, the liquid crystal display 100 having a COT structure according to an embodiment of the present invention includes a thin film transistor array and a color filter, as shown in FIG. 4. The lower substrate 101 on which the array) is formed, the upper substrate 141 disposed to correspond to the lower substrate 101, and the substrates 101 and 141 are bonded to maintain a uniform cell gap. And a liquid crystal layer (not shown) formed in a cell gap between the lower substrate 101 and the upper substrate 141.

A gate wiring (not shown) and a gate electrode 103 extending from the gate wiring are formed on the lower substrate 101 in which the image display portion AA and the bezel portion BA are defined.

In addition, a gate insulating film 105 is formed on the entire surface of the lower substrate 101 including the gate electrode 103 and the gate wiring (not shown).

On the gate insulating layer 105 over the gate electrode 103, a semiconductor layer 107 and an ohmic contact layer 108 separated from each other are stacked.

A source electrode 113a and a drain electrode 113b separated from each other are formed on the semiconductor layer 107 and the ohmic contact layer 108. In this case, a data line (not shown) extends from the source electrode 113a, and the data line (not shown) is formed in the other direction crossing the gate line (not shown).

The gate electrode 103, the semiconductor layer 107, and the source electrode 113a and the drain electrode 113b form a thin film transistor T.

In addition, a protective layer 115 is formed on the entire surface of the lower substrate 101 including the source electrode 113a and the drain electrode 113b.

On the lower substrate 101 corresponding to the pixel area (not shown) of the image display unit AA, red, green, and blue color filters 117R, 117G, not shown. A color filter 117 is formed. At this time, a black matrix (not shown) is formed on the lower substrate 101 corresponding to the boundary area of the red, green, and blue color filters 117R, 117G, not shown, or A portion overlapping between the red, green, and blue color filters 117R, 117G (not shown) may serve as a black matrix function, that is, to block light.

In addition, a planarization layer 121 is formed on the entire surface of the passivation layer 115 including the color filter 117. In this case, the planarization layer 121 serves to planarize the surface of the lower substrate 101.

Further, a drain contact hole (not shown, see 123 in FIG. 6E) exposing a portion of the drain electrode 113b of the thin film transistor T is formed in the planarization layer 121, the color filter 117, and the passivation layer 115. Has been.

Further, a pixel electrode 125 in electrical contact with the drain electrode 115 is formed on the planarization layer 121 including the drain contact hole 123. In this case, the pixel electrode 125 is formed for each pixel area (not shown) of the image display unit AA.

Moreover, as shown in FIG. 5, GIP driving circuit patterns 127 are formed to be spaced apart on the planarization layer 121 of the lower substrate 101 corresponding to the bezel part BA, and the circuit patterns A dummy pattern 129 is formed on the planarization layer 121 between 127. In this case, the dummy pattern 129 is formed separately from the circuit patterns 127. Further, the circuit patterns 127 and the dummy patterns 129 are formed of the same material layer as the pixel electrode 125.

Column spacers 131 are formed on the planarization layer 121 so that the lower substrate 101 and the upper substrate 141 maintain a constant cell gap. In this case, the column spacer 131 may be formed at a position overlapping with a thin film transistor T, a gate line (not shown), or a data line (not shown) in the image display unit AA, and the column spacer ( The 131 may be formed on the planarization layer 121 positioned on the bezel part BA.

In addition, a lower alignment layer (not shown) may be formed on the exposed surface of the lower substrate 101 including the column spacer 131 and the pixel electrode 125.

On the other hand, the upper substrate 141 is disposed on the lower substrate 101 with a certain cell gap, and a seal pattern 151 is formed along the outer rims of the substrates 101 and 141, The upper substrate 141 is bonded together. In this case, a common electrode (not shown) and an upper alignment layer (not shown) may be formed on the front surface of the upper substrate 141. In addition, the common electrode (not shown) may be selectively formed on the upper substrate 141 or the lower substrate 101 according to the liquid crystal driving mode.

In addition, a liquid crystal layer (not shown) is formed between the lower substrate 101 and the upper substrate 141 in which a constant cell gap is maintained by the column spacers 131.

As described above, in the liquid crystal display according to an embodiment of the present invention, a dummy pattern is formed to be separated from the circuit patterns between the circuit patterns provided in the bezel part of the outer panel without the black matrix and the black column spacer. The visibility from the bezel part can be improved.

A method of manufacturing a liquid crystal display device according to an embodiment of the present invention having such a configuration will be described with reference to FIGS. 6A to 6H as follows.

6A to 6H are cross-sectional views illustrating a manufacturing process of a liquid crystal display according to an exemplary embodiment of the present invention.

First, a gate metal layer (not shown) is formed on the transparent lower substrate 101 in which the image display portion AA and the bezel portion BA are defined through a deposition method such as a sputtering deposition method. In this case, as the gate metal layer (not shown), a single layer or double layer structure made of chromium (Cr), molybdenum (Mo), aluminum-based metal, or the like may be used.

Next, as shown in FIG. 6A, by patterning the gate metal layer (not shown) by a photolithography process and an etching process using a first mask, a gate wiring (not shown) and a gate extending from the gate wiring An electrode 103 is formed. In this case, when forming the gate wiring, patterns such as a common wiring (not shown) and a common electrode (not shown) receiving a reference voltage from the common wiring may be formed. In addition, the common electrode (not shown) may be formed on the upper substrate 131 in the case of a liquid crystal driving mode, for example, a TN mode.

Thereafter, a gate insulating layer 105 is formed on the lower substrate 101 on which the patterns are formed through a deposition method such as PECVD or sputtering. In this case, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) may be used as the material of the gate insulating layer 105.

Next, an amorphous silicon layer (not shown) and an n+ amorphous silicon layer (not shown) are sequentially formed on the gate insulating layer 105.

Thereafter, as shown in FIG. 6B, by patterning the n+ amorphous silicon layer (not shown) and the amorphous silicon layer (not shown) by a photolithography process and an etching process using a second mask, the semiconductor layer 107 And an ohmic contact layer 108 is formed.

Next, as shown in FIG. 6C, after forming a source/drain metal layer (not shown) on the entire surface of the lower substrate 101 including the ohmic contact layer 108 and the semiconductor layer 107, a third mask is formed. By patterning the source/drain metal layer (not shown) by using a photolithography process and an etching process, a data line (not shown) crossing the gate line (not shown), and a source electrode 113a and a drain separated from each other. An electrode 113b is formed. In this case, molybdenum (Mo), titanium, tantalum, molybdenum alloy, or the like is used as the source/drain metal layer (not shown). Accordingly, the gate electrode 103, the semiconductor layer 107, and the source electrode 113a and the drain electrode 113b form a thin film transistor T.

Thereafter, a protective layer 115 is formed on the gate insulating layer 105 including the source electrode 113a and the drain electrode 113b by a deposition method such as PECVD. In this case, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) may be used as the material of the passivation layer 115.

Next, as shown in FIG. 6D, red, green, and blue (red), green, and blue ( Blue) A color filter 117 composed of color filters 117R and 117G (not shown) is formed. At this time, in the step before forming the color filter 117, the lower substrate 101 corresponding to the boundary area of the red, green, and blue color filters 117R, 117G, not shown. A black matrix (not shown) may be formed thereon, or a portion overlapping between the red, green, and blue color filters 117R, 117G, not shown, has a black matrix function, that is, It can also play a role of blocking light.

Thereafter, as shown in FIG. 6E, a planarization layer 121 is formed on the entire surface of the passivation layer 115 including the color filter 117. In this case, the planarization layer 121 serves to planarize the surface of the lower substrate 101. The planarization layer 121 may be formed of an inorganic insulating material such as the gate insulating layer 105, an acrylic organic compound having a small dielectric constant, or an organic insulating material such as BCB or PFCB.

Next, the planarization layer 121, the color filter 117, and the passivation layer 115 are sequentially patterned through a photolithography process and an etching process using a fourth mask, thereby exposing a portion of the drain electrode 113b. A contact hole 123 is formed.

Thereafter, a transparent electrode material layer (not shown) is deposited on the planarization layer 121 including the drain contact hole 123 by a deposition method such as sputtering.

Next, as shown in FIG. 6F, the pixel electrode 125 in contact with the drain electrode 113b is patterned by patterning the transparent electrode material layer (not shown) through a photolithography process and an etching process using a fifth mask. ) To form. In this case, as the material for the transparent electrode material layer, indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide may be used. Further, the pixel electrode 125 is formed for each pixel area (not shown) of the image display unit AA.

Moreover, when patterning the transparent electrode material layer (not shown), the GIP driving circuit patterns 127 are formed to be spaced apart on the planarization layer 121 of the lower substrate 101 corresponding to the bezel part BA. , A dummy pattern 129 is formed on the planarization layer 121 between the circuit patterns 127. In this case, the dummy pattern 129 is formed separately from the circuit patterns 127. Further, the circuit patterns 127 and the dummy patterns 129 are formed of the same material layer as the pixel electrode 125, that is, a transparent electrode material layer (not shown).

Thereafter, as shown in FIG. 6G, a column spacer 131 is formed on the planarization layer 121 so that the lower substrate 101 and the upper substrate 141 maintain a constant cell gap. . In this case, the column spacer 131 may be formed at a position overlapping with a thin film transistor T, a gate line (not shown) or a data line (not shown) in the image display unit AA, and the column spacer ( The 131 may be formed on the planarization layer 121 positioned on the bezel part BA.

Next, a lower alignment layer (not shown) may be formed on the exposed surface of the lower substrate 101 including the column spacer 131 and the pixel electrode 125.

Thereafter, although not shown in the drawing, a common electrode (not shown) may be formed on the entire surface of the upper substrate 141 and then an upper alignment layer (not shown) may be formed. In this case, the common electrode (not shown) may be selectively formed on the upper substrate 141 or the lower substrate 101 according to the liquid crystal driving mode.

Next, as shown in FIG. 6H, a liquid crystal layer (not shown) is formed between the substrates 101 and 141 while the upper substrate 141 is disposed on the lower substrate 101 with a constant cell gap. .

Thereafter, by forming a seal pattern 151 along the outer edge of the lower substrate 101 and the upper substrate 141 to bond the lower substrate 101 and the upper substrate 141 together, an embodiment of the present invention The manufacturing process of the liquid crystal display device of the COT structure according to the following is completed.

As described above, in a method of manufacturing a liquid crystal display according to an embodiment of the present invention, a dummy pattern is formed to be separated from the circuit patterns between the circuit patterns provided in the bezel part outside the panel without a black matrix and a black column spacer. Visibility from the outer bezel can be improved.

Meanwhile, a liquid crystal display device according to another exemplary embodiment of the present invention will be described with reference to FIG. 7.

7 is a schematic cross-sectional view of a liquid crystal display according to another embodiment of the present invention, and FIG. 8 schematically shows a dummy pattern provided on the front of a bezel part outside a panel of a liquid crystal display according to another embodiment of the present invention. It is a floor plan.

In the liquid crystal display 200 having a COT structure according to another embodiment of the present invention, as shown in FIGS. 7 and 8, an image display unit AA in which an image is implemented, and an outer edge portion of the image display unit AA It is divided into a bezel part (BA).

A seal pattern 251 for bonding the lower substrate 201 and the upper substrate 241 is provided on the bezel portion BA positioned outside the image display unit AA. In addition, a dummy pattern 229 is provided on the front surface of the lower substrate 201 corresponding to the bezel part BA.

In more detail, the liquid crystal display 200 having a COT structure according to another embodiment of the present invention includes a thin film transistor array and a color filter, as shown in FIG. 7. The lower substrate 201 on which the array) is formed, the upper substrate 241 disposed to correspond to the lower substrate 101, and the substrates 201 and 241 are bonded to maintain a uniform cell gap. It includes a liquid crystal layer (not shown) formed in a cell gap between the lower substrate 201 and the upper substrate 241.

A gate wiring (not shown) and a gate electrode 203 extending from the gate wiring are formed on the lower substrate 201 on which the image display portion AA and the bezel portion BA are defined.

In addition, a gate insulating film 205 is formed on the entire surface of the lower substrate 201 including the gate electrode 203 and the gate wiring (not shown).

A semiconductor layer 207 and an ohmic contact layer 208 separated from each other are stacked on the gate insulating layer 205 over the gate electrode 203.

A source electrode 213a and a drain electrode 213b separated from each other are formed on the semiconductor layer 207 and the ohmic contact layer 208. At this time, a data line (not shown) extends from the source electrode 213a, and the data line (not shown) is formed in the other direction crossing the gate line (not shown).

The gate electrode 203, the semiconductor layer 207, the source electrode 213a and the drain electrode 213b form a thin film transistor T.

In addition, a protective layer 215 is formed on the entire surface of the lower substrate 201 including the source electrode 213a and the drain electrode 213b.

On the lower substrate 201 corresponding to the pixel area (not shown) of the image display unit AA, red, green, and blue color filters 217R, 217G, not shown. A color filter 217 is formed. At this time, a black matrix (not shown) is formed on the lower substrate 201 corresponding to the boundary area of the red, green, and blue color filters 217R, 217G, not shown, or A portion overlapping between the red, green, and blue color filters 217R, 217G (not shown) may serve as a black matrix function, that is, to block light.

In addition, a planarization layer 221 is formed on the entire surface of the passivation layer 215 including the color filter 217. In this case, the planarization layer 221 serves to planarize the surface of the lower substrate 201.

Further, a drain contact hole (not shown) exposing a portion of the drain electrode 213b of the thin film transistor T is formed in the planarization layer 221, the color filter 217, and the passivation layer 215.

Further, a pixel electrode 225 in electrical contact with the drain electrode 215 is formed on the planarization layer 221 including the drain contact hole (not shown). In this case, the pixel electrode 225 is formed for each pixel area (not shown) of the image display unit AA.

On the planarization layer 221 of the lower substrate 201 corresponding to the bezel part BA, as shown in FIG. 4, driving circuit patterns (not shown) are formed to be spaced apart from each other. Further, a dummy pattern (not shown, see FIG. 4 129) as in FIG. 4 is formed on the planarization layer 221 between the driving circuit patterns (not shown), but the GIP driving circuit patterns (not shown) A dummy pattern 229 is formed in another area of the bezel part BA in which) is not formed at all. That is, as shown in FIG. 8, the front surface of the planarization layer 121 of the lower substrate 201 corresponding to a different region of the bezel part BA in which the GIP driving circuit patterns (not shown) are not formed at all. In the dummy pattern 229 is formed. In this case, the dummy pattern 229 is formed of the same material layer as the pixel electrode 225.

Column spacers 231 are formed on the planarization layer 221 so that the lower substrate 201 and the upper substrate 241 maintain a constant cell gap. In this case, the column spacer 231 may be formed at a position overlapping with a thin film transistor T, a gate line (not shown), or a data line (not shown) in the image display unit AA, and the column spacer ( The 231 may be formed on the planarization layer 221 positioned on the bezel part BA.

In addition, a lower alignment layer (not shown) may be formed on the exposed surface of the lower substrate 201 including the column spacer 231 and the pixel electrode 225.

On the other hand, the upper substrate 241 is disposed on the lower substrate 201 with a certain cell gap, and a seal pattern 251 is formed along the outer rims of the substrates 201 and 241, so that the lower substrate 201 and The upper substrate 241 is bonded together. In this case, a common electrode (not shown) and an upper alignment layer (not shown) may be formed on the entire surface of the upper substrate 241. In addition, the common electrode (not shown) may be selectively formed on the upper substrate 241 or the lower substrate 201 according to the liquid crystal driving mode.

In addition, a liquid crystal layer (not shown) is formed between the lower substrate 201 and the upper substrate 241 in which a constant cell gap is maintained by the column spacers 231.

As described above, in the liquid crystal display device according to another embodiment of the present invention, a dummy pattern is additionally added to the front of the lower substrate corresponding to a region in which no driving circuit patterns are formed among the bezel portions outside the panel without a black matrix and a black column spacer. By forming it, it is possible to improve the visibility from the bezel part outside the panel.

The embodiments have been described above with reference to the drawings, but the present invention is not limited thereto.

Terms such as "comprise", "comprise", or "have" described above mean that the corresponding component may be embedded, unless otherwise stated, and therefore, other components are not excluded. It should be interpreted as being able to further include other components. All terms, including technical or scientific terms, unless otherwise defined, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms generally used, such as terms defined in the dictionary, should be interpreted as being consistent with the meaning of the context of the related technology, and are not interpreted as ideal or excessively formal meanings unless explicitly defined in the present invention.

The above description is merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains will be able to make various modifications and variations without departing from the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain the technical idea, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

117: color filter 125: pixel electrode
127: circuit pattern 129: dummy pattern
131: column spacer 151: seal pattern

Claims (8)

A lower substrate and an upper substrate facing each other, defining an image display portion and a bezel portion, and bonded together by a seal pattern disposed on the bezel portion;
A thin film transistor and a color filter provided on the lower substrate;
A pixel electrode provided on the color filter and in contact with the thin film transistor;
A plurality of circuit patterns provided on the bezel portion of the lower substrate; And
Including a dummy pattern provided between the circuit patterns of the bezel part,
The dummy pattern is located on the front surface of a region in which the circuit patterns are not located among the bezel parts including the outermost part of the lower substrate,
The seal pattern is located at the outermost side of the lower substrate,
The dummy pattern includes a region overlapping the seal pattern. The liquid crystal display device of claim 1, wherein the dummy pattern is formed of the same material layer as the pixel electrode. delete The liquid crystal display device of claim 1, wherein the dummy pattern is independently separated from circuit patterns of a lower substrate. Providing a lower substrate and an upper substrate in which an image display portion and a bezel portion are defined;
Forming a thin film transistor and a color filter on the lower substrate;
Forming a planarization layer on the color filter;
Forming a pixel electrode on the planarization layer in contact with the thin film transistor;
Forming a plurality of circuit patterns on the planarization layer corresponding to the bezel portion and forming a dummy pattern on the planarization layer between the circuit patterns; And
Including the step of bonding the lower substrate and the upper substrate using a seal pattern located on the bezel,
The dummy pattern is formed on the entire surface of a region of the bezel part in which the circuit patterns are not formed, including the outermost part of the lower substrate,
The seal pattern is located at the outermost side of the lower substrate,
The method of manufacturing a liquid crystal display device, wherein the dummy pattern includes a region overlapping the seal pattern. 6. The method of claim 5, wherein the dummy pattern is formed of the same material layer as the pixel electrode. delete The method of claim 5, wherein the dummy pattern is independently separated from circuit patterns of a lower substrate.

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