KR102245005B1 - Testing method of mother substrate for display device - Google Patents

Abstract

The present invention is to provide a mother substrate for a display device capable of inspecting defective pixels by arranging an inspection gate driver on a dummy portion of the mother substrate, and an inspection method thereof, wherein the inspection gate driver includes first to n-th gates A circuit, wherein the first to n-th gate embedded circuits sequentially output first to n-th gate signals to the first to n-th gate wirings to perform inspection, and then remove the dummy part.

Description

Testing method of mother substrate for display device

The present invention relates to a mother substrate for a display device, and more particularly, to a method for inspecting a mother substrate for a display device capable of inspecting defective pixels by arranging an inspection gate driver on a dummy portion of the mother substrate.

In the display device, a plurality of first substrates are formed on a first mother substrate of a large area, a plurality of second substrates are formed on a separate second mother substrate, and then the two first and second mother substrates are bonded together. A plurality of display panels are simultaneously formed to improve yield.

Accordingly, a process of cutting the bonded first and second mother substrates into a plurality of unit display panels is required.

In this case, the gate wiring and the data wiring are cross-arranged on the display panel, and pixels are positioned at the intersection of the gate wiring and the data wiring.

In addition, each display device includes a gate driver for driving the gate wiring, a data driver for driving the data wiring, a timing controller for controlling the gate driver and the data driver, and a power supply for supplying a driving voltage.

The timing controller controls the driving timing of the gate driver and the data driver and supplies a data signal to the data driver.

The power supply generates driving voltages such as a common voltage Vcom, a gate high voltage Vgh, and a gate low voltage Vgl by using the input power.

The gate driver sequentially supplies a gate signal to the gate wiring, and the data driver supplies a data signal to each data line whenever the gate signal is supplied to the gate wiring.

In this case, the data driver and the gate driver are integrated into several ICs (Integrated Circuits).

The integrated data driving IC is mounted on the TCP (Tape Carrier Package) and connected to the liquid crystal panel by TAB (Tape Automated Bonding) method, and the integrated gate driving IC is mounted on the display panel by COG (Chip On Glass) method. .

Here, the data driving IC receives a control signal and a driving voltage from a printed circuit board (PCB) (that is, a timing control unit and a power supply unit) connected to the TCP.

The gate driving IC receives control signals and driving voltages from the timing control unit and the power supply unit through signal wiring mounted in a line on glass method.

Meanwhile, before connecting the TCP to the display panel, a defective pixel of the display panel is inspected using a display panel inspection device (Auto Probe).

That is, after the display panel is completed, defective pixels are checked and the checked defective pixels are repaired to secure a reliable display panel.

After securing the reliability of the display panel in this way, the TCP is connected to the display panel.

1 is a view schematically showing a part of a conventional mother substrate.

As shown in the drawing, the mother substrate 10 includes a plurality of first substrates 1 divided into a display area AA in which an image is displayed and a non-display area NAA disposed outside the display area AA, It includes a dummy part DMY disposed outside the non-display area NAA of the first substrate 1.

In this case, first to n-th gate wirings GL1 to GLn are disposed in the display area AA of the first substrate 1, and the first to n-th gate wirings GL1 to GLn are disposed in the non-display area NAA. A gate pad part 5 connected to) is disposed.

In addition, each of the first to nth gate wirings GL1 to GLn is connected to the gate pad portion 5 through first to nth gate link lines GLL1 to GLLn disposed in the non-display area NAA.

In addition, a plurality of data lines DL crosses the first through n-th gate lines GL1 through GLn and are disposed in the display area AA, and the first through n-th gate lines GL1 through GLn and a plurality of data are A thin film transistor (not shown) is disposed at the intersection point of the wiring DL.

On the other hand, the dummy part DMY is an area removed during the cutting process of cutting along the predetermined cutting line SL formed on the mother substrate 10.

In order to inspect the defective pixels of the first substrate 1 configured on the mother substrate 10, gate signals must be sequentially output to the first to nth gate wirings GL1 to GLn.

To this end, a gate driver (not shown) for inspection is directly contacted with the gate pad unit 5 to sequentially apply a gate signal to each of the gate wirings GL1 to GLn.

On the other hand, the gate pad part 5 is made of a plurality of gate pads (not shown) that apply a gate signal to each of the gate lines GL1 to GLn, and these gate pads (not shown) are the gate lines GL1 to GLn. It is placed in the same number as the number.

In addition, the inspection gate driver (not shown) has a plurality of pins in contact with each gate pad (not shown), and these pins are arranged in the same number as the number of gate pads (not shown). do.

In particular, in the case of a high-resolution display device, the gap between the gate lines GL1 to GLn and the gap between each gate pad (not shown) are formed to be narrow, and accordingly, the gate driver for inspection (not shown) in contact with the gate pad (not shown) The spacing between the pins of the city) is also formed narrow.

Due to such a narrow gap, when the inspection gate driver (not shown) is in contact with the gate pad portion 5 to perform inspection, the gate pad (not shown) and the pin of the inspection gate driver (not shown) are Miss alignment occurs frequently, and when such misalignment is adjusted, the data pad portion 5 is damaged, and the time required for inspection is increased.

The present invention was conceived to solve the above-described conventional problem, and by placing an inspection gate driver on a dummy portion of the mother substrate to conduct inspection, a display capable of preventing damage to the gate pad portion and shortening the inspection time required. Its purpose is to provide an inspection method for a device mosquito board.

In order to achieve the above object, the present invention provides a plurality of first substrates divided into a display area in which an image is displayed, a non-display area disposed outside the display area, and a dummy part disposed outside the non-display area and a display. First to n-th gate wiring disposed in the area and a gate pad portion disposed in the non-display area and connected to the first to n-th gate wiring, and an inspection gate driver disposed on the dummy portion and connected to the gate pad portion. Provide mosquito boards for display devices.

In addition, the inspection gate driver includes first to n-th gate built-in circuits, and the first to n-th gate built-in circuits sequentially output first to n-th gate signals to the first to n-th gate wirings.

In addition, the inspection gate driver is connected to at least one start signal wiring and a clock signal wiring disposed on the dummy portion.

In addition, the dummy portion further includes a test pad portion for applying a start signal and a clock signal to each of the start signal wiring and the clock signal wiring.

Further, it further includes first to n-th gate link wirings connecting the first to n-th gate wirings and the gate pad portion, and first to n-th test link wirings connecting the gate pad portion and the inspection gate driver.

In addition, a thin film transistor disposed in the display area and disposed at an intersection of a plurality of data lines crossing the first through n-th gate lines and the first through n-th gate lines and the plurality of data lines is further included.

In addition, in the inspection method of a mother substrate for a display device, the steps of inspecting the mother substrate by an inspection gate driver disposed on the dummy portion, and cutting the mother substrate to form a plurality of first substrates, and removing the dummy portion It provides a method of testing the mosquito plate comprising a.

In addition, in the inspection method of a mother substrate for a display device, the step of cutting the mother substrate into a plurality of first substrates with a dummy portion and inspecting the plurality of first substrates respectively by an inspection gate driver disposed on the dummy portion. It provides a method for inspecting a mother substrate including the step of cutting the dummy parts attached to the plurality of first substrates.

In addition, the step of inspecting the mother substrate or the first substrate includes a step of outputting a first gate signal through the first gate wiring by receiving the start signal and the first clock signal by the first gate built-in circuit and the second built-in gate circuit. The step of receiving the first gate signal and the second clock signal and outputting a second gate signal to the second gate wire, and the third gate built-in circuit receiving the second gate signal and the third clock signal to receive the second gate signal and the third clock signal to the third gate wire. Outputting a third gate signal and outputting a fourth gate signal to the fourth gate wire by receiving the third gate signal and the fourth clock signal by the fourth gate built-in circuit, and the n-th gate built-in circuit being applied to the n-th gate wire. And outputting an n-th gate signal to.

According to the present invention, by disposing the inspection gate driver on the dummy portion of the mother substrate to perform inspection, the inspection can be performed without directly contacting the inspection gate driver to the gate pad portion, thereby preventing damage to the gate pad portion.

In addition, it is possible to shorten the time required for inspection by preventing misalignment that occurs when the inspection gate driver directly contacts the gate pad portion.

1 is a view schematically showing a part of a conventional mother substrate.
2 is a view schematically showing a part of a mother substrate according to an embodiment of the present invention.
FIG. 3 is a block diagram of a gate driver for inspection of FIG. 2, and is a diagram illustrating a method of inspecting a mother substrate according to an exemplary embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

2 is a view schematically showing a part of a mother substrate according to an exemplary embodiment of the present invention, and FIG. 3 is a block diagram of a gate driver for inspection of FIG. 2, illustrating a method of inspecting a mother substrate according to an embodiment of the present invention. It is a drawing to do.

As shown in the drawing, the mother substrate 100 according to the present invention comprises a plurality of first substrates divided into a display area AA in which an image is displayed and a non-display area NAA disposed outside the display area AA. (11) and a dummy portion DMY disposed outside the non-display area NAA.

At this time, the first to n-th gate wirings GL1 to GLn are disposed in the display area AA of the first substrate 11, and the first to n-th gate wirings GL1 to GLn are disposed in the non-display area NAA. A gate pad part 50 connected to) is disposed.

In addition, an inspection gate driving unit 70 connected to the gate pad unit 50 is disposed in the dummy unit DMY.

At this time, the first to n-th gate wirings GL1 to GLn are connected to the gate pad unit 50 through first to n-th gate link wirings GLL1 to GLLn disposed in the non-display area NAA, The gate pad part 50 is connected to the test gate driving part 70 through the first to nth test link wirings TTL1 to TTLn.

Further, the gate pad part 50 includes a plurality of gate pads sequentially applying gate signals to the first to n-th gate wirings GL1 to GLn.

In addition, a plurality of data lines DL crosses the first through n-th gate lines GL1 through GLn and are disposed in the display area AA, and the first through n-th gate lines GL1 through GLn and a plurality of data are A thin film transistor (not shown) is disposed at the intersection point of the wiring DL.

The inspection gate driver 70 includes first to n-th gate built-in circuits GIP1 to GIPn, and the first to n-th gate built-in circuits GIP1 to GIPn are first to n-th gate wirings GL1 to GLn. ) To sequentially output the first to nth gate signals Vout1 to Voutn.

At this time, each of the built-in gate circuits GIP1 to GIPn is formed together when the thin film transistor (not shown) disposed in the display area AA is formed, so that a separate inspection gate driver (not shown) is used as a gate pad unit ( No need to contact 50).

In addition, the inspection gate driver 70 is connected to at least one start signal line (VSL) and clock signal lines (CL1 to CL4), and starts to each of the start signal lines (VSL) and clock signal lines (CL1 to CL4). A test pad unit 90 for applying the signal VST and the clock signals CLK1 to CLK4 is provided.

At this time, the start signal wiring VSL, the clock signal wirings CL1 to CL4, and the test pad portion 90 are disposed in the dummy portion DMY.

That is, the mother substrate 100 according to the embodiment of the present invention includes a gate driver 70 for inspection, a start signal line VSL, a clock signal line CL1 to CL4, and a test pad unit 90 as a dummy part (DMY). ), and simultaneously inspects the defective pixels of the plurality of first substrates 11 disposed on the mother substrate 100 before cutting revolution, and then cuts along the predetermined cutting line SL formed on the mother substrate 100 During the cutting process, it is removed together with the dummy part DMY.

On the other hand, the mother substrate 100 is cut into a plurality of first substrates with the dummy part DMY attached, and the dummy part DMY after inspecting each of the first substrates with the dummy part DMY attached thereto. It can also be removed by cutting.

Accordingly, the mother substrate 100 according to the embodiment of the present invention arranges the gate built-in circuits GIP1 to GIPn in the dummy part DMY, so that a separate test gate driver (not shown) is directly provided to the gate pad part ( Since the inspection can be performed without contacting 50), damage to the gate pad unit 50 can be prevented.

In addition, it is possible to shorten the time required for inspection by preventing misalignment caused by direct contact of the gate driving unit for inspection (not shown) to the gate pad unit 50.

After the inspection process of the plurality of first substrates 11 configured on the mother substrate 100 described above is finished, a TCP (Tape Carrier Package) on which a gate driving IC (Integrated Circuit) is mounted is connected to the gate pad unit 50. , By performing the cutting process, the dummy portion DMY is removed and a plurality of first substrates 11 are formed.

Next, a method of inspecting the mother substrate 100 according to an embodiment of the present invention will be described.

The gate signals Vout1 to Voutn output from each of the built-in gate circuits GIP1 to GIPn are sequentially supplied to the gate wirings GL1 to GLn.

Specifically, the first built-in gate circuit GIP1 outputs the first gate signal Vout1 to the first gate wire GL1, and the second built-in gate circuit GIP2 serves as the second gate wire GL2. The gate signal Vout2 is output, the third gate built-in circuit GIP3 outputs the third gate signal Vout3 to the third gate wiring GL3, and the fourth gate built-in circuit GIP4 is the fourth gate wiring. The fourth gate signal Vout4 is output to GL4, and..., the n-th gate built-in circuit GIPn outputs the n-th gate signal Voutn to the n-th gate line GLn.

First, since the first built-in gate circuit (GIP1) does not have a built-in gate circuit in the previous step, the first built-in gate circuit (GIP1) cannot start by receiving the gate signal of the built-in gate circuit in the previous step as a trigger signal. It is initiated by (VST).

Accordingly, when the start signal VST is applied to the first built-in gate circuit GIP1, the first built-in gate circuit GIP1 outputs the first gate signal Vout1 using the first clock signal CLK1. , The first gate signal Vout1 output from the first built-in gate circuit GIP1 is supplied to the second built-in gate circuit GIP2 to start the second built-in gate circuit GIP2, thereby starting the second built-in gate circuit. GIP2 outputs the second gate signal Vout2 using the second clock signal CLK2.

Next, the second gate signal Vout2 output from the second gate built-in circuit GIP2 is supplied to the third built-in gate circuit GIP3 to start the third built-in gate circuit GIP3, thereby embedding the third gate. The circuit GIP3 outputs the third gate signal Vout3 using the third clock signal CLK3, and the third gate signal Vout3 output from the third gate built-in circuit GIP3 is a fourth gate built-in circuit. It is supplied to (GIP4) to start the fourth gate built-in circuit (GIP4), whereby the fourth built-in gate circuit (GIP4) outputs the fourth gate signal (Vout4) using the fourth clock signal (CLK4), ..., the n-th gate built-in circuit GIPn outputs the n-th gate signal Voutn.

In this inspection method, after inspecting the defective pixels of the mother substrate 100, the inspection gate driver 70 disposed in the dummy portion DMY, the start signal wiring VSL, and the clock signal wirings CL1 to CL4. And as the test pad part 90 is removed, it is possible to perform the test without directly contacting the gate pad part 50 with a separate test gate driver (not shown), thereby preventing damage to the gate pad part 50. can do.

In addition, it is possible to shorten the time required for inspection by preventing misalignment caused by direct contact of the gate driving unit for inspection (not shown) to the gate pad unit 50.

The present invention is not limited to the above-described embodiments, and various changes and modifications are possible without departing from the spirit of the present invention.

11: first substrate
100: mosquito board
GL1 to GLn: first to nth gate wiring
50: gate pad part
70: inspection gate driver
90: test pad part

Claims (7)

A plurality of first substrates divided into a display area in which an image is displayed and a non-display area disposed outside the display area, a dummy part disposed outside the non-display area, and first to first substrates disposed in the display area For a display device comprising an n-gate wire, a gate pad part disposed in the non-display area and connected to the first to n-th gate wires, and an inspection gate driver disposed in the dummy part and connected to the gate pad part In the inspection method of the mosquito plate,
Simultaneously inspecting the plurality of first substrates by the inspection gate driver disposed on the dummy portion; And
Cutting the mother substrate to form the plurality of first substrates, and removing the dummy part
Inspection method of a mosquito board for a display device comprising a.
The method of claim 1,
The inspection gate driver includes first to n-th gate built-in circuits, and the first to n-th gate built-in circuits sequentially output first to n-th gate signals to the first to n-th gate wirings. Inspection method of device mosquito board.
The method of claim 2,
The step of simultaneously inspecting the plurality of first substrates,
Receiving, by the first gate internal circuit, a start signal and a first clock signal, and outputting the first gate signal to the first gate wiring;
Receiving, by the second gate internal circuit, the first gate signal and the second clock signal and outputting the second gate signal to the second gate wire;
Receiving, by the third gate built-in circuit, the second gate signal and the third clock signal and outputting the third gate signal to the third gate wiring;
Receiving the third gate signal and the fourth clock signal by the fourth gate built-in circuit and outputting the fourth gate signal to the fourth gate wiring; And
Outputting, by the n-th gate built-in circuit, the n-th gate signal to the n-th gate wiring
Inspection method of a mosquito board for a display device comprising a.
A plurality of first substrates divided into a display area in which an image is displayed and a non-display area disposed outside the display area, a dummy part disposed outside the non-display area, and first to first substrates disposed in the display area For a display device comprising an n-gate wire, a gate pad part disposed in the non-display area and connected to the first to n-th gate wires, and an inspection gate driver disposed in the dummy part and connected to the gate pad part In the inspection method of the mosquito plate,
Cutting the mother substrate into the plurality of first substrates to which the dummy part is attached;
Inspecting each of the plurality of first substrates by the inspection gate driver disposed on the dummy portion; And
Cutting the dummy parts attached to the plurality of first substrates
Inspection method of a mosquito board for a display device comprising a.
The method of claim 4,
The inspection gate driver includes first to n-th gate built-in circuits, and the first to n-th gate built-in circuits sequentially output first to n-th gate signals to the first to n-th gate wirings. Inspection method of mosquito board for device.
The method of claim 5,
Inspecting each of the plurality of first substrates,
Receiving, by the first gate internal circuit, a start signal and a first clock signal, and outputting the first gate signal to the first gate wiring;
Receiving, by the second gate internal circuit, the first gate signal and the second clock signal and outputting the second gate signal to the second gate wire;
Receiving, by the third gate built-in circuit, the second gate signal and the third clock signal and outputting the third gate signal to the third gate wiring;
Receiving, by the fourth gate built-in circuit, the third gate signal and the fourth clock signal and outputting the fourth gate signal to the fourth gate wiring; And
Outputting, by the n-th gate built-in circuit, the n-th gate signal to the n-th gate wiring
Inspection method of a mosquito board for a display device comprising a.
The method of claim 1,
The inspection gate driver sequentially outputs first to n-th gate signals,
The first to nth gate signals are sequentially applied to the first to nth gate wirings through the gate pad part.

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