KR20040061424A - TFT array panel structure being possible log line short test - Google Patents

TFT array panel structure being possible log line short test Download PDF

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KR20040061424A
KR20040061424A KR1020020087688A KR20020087688A KR20040061424A KR 20040061424 A KR20040061424 A KR 20040061424A KR 1020020087688 A KR1020020087688 A KR 1020020087688A KR 20020087688 A KR20020087688 A KR 20020087688A KR 20040061424 A KR20040061424 A KR 20040061424A
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line
test
gate
log
array panel
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KR1020020087688A
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KR100930423B1 (en
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김재광
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비오이 하이디스 테크놀로지 주식회사
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2203/00—Function characteristic
    • G02F2203/69—Arrangements or methods for testing or calibrating a device

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Abstract

PURPOSE: A TFT array panel structure capable of conducting an LOG(Line On Glass) disconnection test is provided to detect a short of a GGS(Gate Gate Short) and an LOG signal line while performing a test by a 1G2D method, thereby enabling an LOG disconnection test. CONSTITUTION: In a 1G2D test circuit, a common line(300) is wired between gate lines of a fanout portion(200) to detect a GCS(Gate Common Short) when a short is generated. A 1G line(210) cannot detect a short in a part crossed with a signal line for testing the gate lines only. A portion of an LOG line(220) to which a signal is applied is contacted. An end of the LOG line(220) is shorted to detect a short with an adjacent line. The common line(300) uses metals different from gate metal lines used for a fanout.

Description

로그라인 단선시험이 가능한 ＴＦＴ 어레이 패널구조{TFT array panel structure being possible log line short test}TFT array panel structure being possible log line short test}

본 발명은 TFT 어레이 패널구조에 관한 것으로서, 보다 상세하게는 어레이패널 제작 완료후 신호배선의 PDI-O/S 테스트를 사용하고 있는 1G2D방식에서 2G2D방식으로 변경시에 어레이 테스트에서 로그(LOG : Line On Glass)라인의 단선테스트가 가능하도록 한 로그라인 단선시험이 가능한 TFT 어레이 패널구조에 관한 것이다.The present invention relates to a TFT array panel structure, and more specifically, to a log (LOG: Line) in an array test when changing from a 1G2D method to a 2G2D method using a PDI-O / S test of signal wiring after the fabrication of the array panel is completed. The present invention relates to a TFT array panel structure capable of a log line disconnection test that enables a disconnection test of an On Glass line.

일반적인 박막 트랜지스터 액정표시장치의 어레이 공정을 진행할 때 다양한 결함이 빈번하게 발생되는데, 이중 5-마스크 어레이 공정을 완료한 후 PDI 테스트 방식을 이용하여 어레이 테스트를 실시하는데, 그 PCI 테스트 방식에 따르면 2G2D 방식에 의해 게이트/데이터 신호배선을 이븐(Even)/오드(Odd)로 구분하고, 각각 신호를 인가하여 오픈(Open)/단락(Short) 여부를 검사하고 있다.Various defects frequently occur when the array process of a general thin film transistor liquid crystal display is performed. After completing the 5-mask array process, the array test is performed using the PDI test method. According to the PCI test method, the 2G2D method is used. The gate / data signal wiring is divided into Even / Odd and the signals are applied to each other to check whether they are open or short.

즉, 일반적인 2G2D방식을 도시하고 있는 도 1을 참조하여 설명하면, 게이트의 신호배선을 동일한 금속으로 사용하면 교차(Cross)되는 부분에서 단락이 발생되기 때문에, 서로 상이한 금속을 사용하여 게이트 신호배선(Even/Odd)을 구성하여 상기 단락 발생을 방지하고 있다.That is, referring to FIG. 1, which illustrates a general 2G2D method, when a gate signal wire is used as the same metal, a short circuit occurs at a cross section, so that gate signal wires using different metals ( Even / Odd) is configured to prevent the occurrence of the short circuit.

다시 말해 게이트 오드(Odd)(10)와 게이트 이븐(Even)(20)을 각각 구분하여 제공한 상태에서, 게이트 패드에서 연장되는 오드 패드(Odd Pad)(30)와 이븐 패드(Even Pad)(40)를 상기 오드(Odd)와 이븐(Even)으로 구분된 게이트 신호배선에 연결하고, 그 각각의 이븐(Even)과 오드(Odd) 배선에 신호를 인가하여 테스트를 실시하는 것이다.In other words, in the state in which the gate odd 10 and the gate even 20 are provided separately, the odd pad 30 and the even pad extending from the gate pad ( 40 is connected to the gate signal wiring divided into the odd and the odd, and a test is performed by applying a signal to each of the even and odd wirings.

그러나, 상기와 같은 종래 기술에 의하면, 상기 서로 상이한 메탈을 사용하여 게이트 신호배선을 구성할 때, 접촉홀(Contact Hole)(A)(도 1)이 형성되어 게이트 배선과 연결하는 구조로 이루어지기 때문에 접촉홀(A) 불량이나 정전기 등에 취약하여 게이트 배선이 손상을 받게 되면 엷은 선이 보이는 결함을 발생시키는 문제점이 있었다.However, according to the prior art as described above, when configuring the gate signal wiring using the different metals, a contact hole (A) (FIG. 1) is formed to be connected to the gate wiring. Therefore, when the gate wiring is damaged due to a poor contact hole (A) defect or static electricity, there is a problem of generating a thin line defect.

그와 같이 접촉홀(A) 불량 등의 결함 요소를 방지하기 위하여 도 2에 도시된 바와 같이 게이트 신호배선(50)을 동일한 금속을 사용하는 1G2D방식에 의해 테스트를 실시하고 있지만, 그 1G2D 방식은 게이트와 게이트 상호간의 단락 검출이 불가능하고, 패널 구동에 필요한 신호라인을 글래스(Glass)상에 직접 패터링(Patterning) 하는 방식을 적용할 경우 1G2D 방식에서는 로그 배선간의 단락이 어레이 테스트에서 검출이 안되어 셀 테스트(Cell Test)를 할 경우 상기와 같은 로그 배선간의 단락 미검출로 인하여 셀 테스트(Cell Test) 장비가 다운(Down)되거나 패널(Panel)이 파손되는 문제점이 발생된다.In order to prevent defective elements such as a defective contact hole A, the gate signal wiring 50 is tested by the 1G2D method using the same metal as shown in FIG. 2, but the 1G2D method is used. If short circuit between gate and gate cannot be detected, and the signal line required for driving the panel is directly patterned on the glass, the short circuit between the log wirings cannot be detected in the array test in the 1G2D method. In the case of a cell test, a problem occurs in that a cell test device is down or a panel is damaged due to the short circuit detection between the log wires as described above.

즉, 도 2의 B부분에서 동일한 신호가 인가되어 각각의 라인이 단락될 경우 라인간 단락을 검출할 수 없기 때문에 셀 테스트시에 각각의 개별 전압을 갖는 신호가 인가될 때 단락된 라인이 있을 경우 과부하가 걸려 셀 테스트 장비가 다운될 문제점이 있는 것이다.That is, when the same signal is applied in part B of FIG. 2 and each line is shorted, the short circuit between lines cannot be detected. There is a problem that the cell test equipment is down due to an overload.

이에 본 발명은 상기 종래 기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 어레이 패널 제작 완료후에 1G2D 방식에 의해 테스트 수행시 GGS(Gate Gate Short)및 로그 신호라인의 단락검출이 가능하도록 한 로그라인 단선시험이 가능한 TFT 어레이 패널구조를 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, the log line disconnection to enable the detection of the gate gate short (GGS) and the log signal line when performing the test by the 1G2D method after the completion of the array panel production The purpose is to provide a TFT array panel structure that can be tested.

도 1은 종래 기술에 따른 2G2D 테스트 방식에 의한 설계상태의 도면.1 is a view of a design state by the 2G2D test method according to the prior art.

도 2는 종래 기술에 따른 1G2D 테스트 방식에 의한 설계상태의 도면.Figure 2 is a view of the design state by the 1G2D test method according to the prior art.

도 3은 본 발명에 따른 로그라인 단선시험이 가능한 TFT 어레이 패널구조에 의해 1G2D 테스트방식에 따라 GGS상태를 검출하는 것을 보인 도면.3 is a view showing the detection of the GGS state according to the 1G2D test method by the TFT array panel structure capable of a log line disconnection test according to the present invention.

도 4는 본 발명에 따른 로그라인 단선시험이 가능한 TFT 어레이 패널구조에 의해 1G2D 테스트방식에 따라 GCS상태를 검출하는 것을 보인 도면.4 is a view showing detecting the GCS state according to the 1G2D test method by the TFT array panel structure capable of a log line disconnection test according to the present invention.

[도면부호의설명][Description of Drawing Reference]

100 : 게이트 테스트의 신호라인100: signal line of gate test

110 : 로그 오드 라인 테스트만을 위한 신호라인110: signal line for log order line test only

120 : GO 패드 130 : GE 패드120: GO pad 130: GE pad

200 : 팬 아웃부 300 : 공통라인(Common Line)200: fan out portion 300: common line

상기 목적을 달성하기 위한 본 발명에 따른 로그라인 단선시험이 가능한 TFT 어레이 패널구조는, 어레이 패널 제작완료후, 신호배선의 PDI-O/S 테스트를 사용하고 있는 2G2D 방식에서 1G2D 방식으로 변경시에 로그(Line On Glass)라인의 단락 테스트가 가능하도록 한 패널 구조에 있어서, GGS 검출과 셀 테스트 전에 로그 라인의 단락 테스트가 정전기 등에 의해 가능하도록 PDI 공통 패드의 신호배선의 연장선이 게이트 라인의 팬 아웃의 라인 사이사이에 공통라인이 형성되는 것을 특징으로 한다.In order to achieve the above object, a TFT array panel structure capable of a log line disconnection test according to the present invention may be changed from a 2G2D method using a PDI-O / S test of signal wiring to a 1G2D method after completion of array panel fabrication. In the panel structure which enables the short line test of the line on glass line, the extension line of the signal line of the PDI common pad is fan-out of the gate line so that the short line test of the log line is possible by electrostatic etc. before the GGS detection and the cell test. The common line is formed between the lines of.

(실시예)(Example)

이하, 본 발명에 따른 로그라인 단선시험이 가능한 TFT 어레이 패널구조를 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a TFT array panel structure capable of a log line disconnection test according to the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명에 따른 로그라인 단선시험이 가능한 TFT 어레이 패널구조에 의해 1G2D 테스트방식에 따라 GGS상태를 검출하는 것을 보인 도면이다.3 is a view showing the detection of the GGS state according to the 1G2D test method by the TFT array panel structure capable of a log line disconnection test according to the present invention.

도 4는 본 발명에 따른 로그라인 단선시험이 가능한 TFT 어레이 패널구조에 의해 1G2D 테스트방식에 따라 GCS상태를 검출하는 것을 보인 도면이다.4 is a view showing detecting the GCS state according to the 1G2D test method by the TFT array panel structure capable of a log line disconnection test according to the present invention.

본 발명의 일 실시예에 따른 로그라인 단선시험이 가능한 TFT 어레이 패널구조에 따르면, 도 3에 도시된 바와 같이 1G2D 방식에서 1-패드는 게이트라인을 테스트하도록 함과 아울러, 다른 1-패드는 로그라인의 테스트에 선택적으로 사용하도록 한다. 즉 도면부호 100은 게이트 테스트의 신호라인이고, 110은 로그 오드 라인 테스트만을 위한 신호라인이다.According to the TFT array panel structure capable of a log line disconnection test according to an embodiment of the present invention, as shown in FIG. 3, in the 1G2D method, the 1-pad allows the gate line to be tested, and the other 1-pad logs. Optionally used for testing lines. That is, reference numeral 100 denotes a signal line of a gate test, and 110 denotes a signal line only for a log order line test.

이와 같은 구조에 따르면, 로그 패턴간에 단락 발생시에, GE 패드(130)에 신호를 인가하고 GO 패드(120)에서 검출되면 GGS로 판단할 수 있어 로그 라인간에 단락이 발생되었음을 검출할 수 있게 된다.According to such a structure, when a short circuit occurs between the log patterns, a signal is applied to the GE pad 130 and detected by the GO pad 120, so that it can be determined as a GGS to detect that a short circuit has occurred between the log lines.

여기서, 다음단 패드의 시작단의 경우 아웃터 게이트 테스트(Outter Gate Test)라인과 연결되지 않아야 테스트가 가능하다.In this case, the start stage of the next stage pad may not be connected to the outer gate test line so that the test can be performed.

한편, 전술한 바와 같이 1G2D의 테스트 방식에서는 GGS검출이 불가능한바, 그러한 GGS는 대부분 팬아웃(Fanout) 부분에서 발생하고 있으므로 이를 해결하기 위하여 상기 팬아웃 라인 사이에 공통라인(Common Line)을 삽입 설치한다.On the other hand, as described above, in the test method of 1G2D, it is impossible to detect GGS. Since such GGS is mostly generated in the fanout part, a common line is inserted between the fanout lines to solve this problem. do.

예컨대 도 4에 도시된 바와 같이, 1G2D 테스트 회로에서 팬 아웃부(200)의 게이트 라인 사이에 공통라인(300)을 배선하여, 단락 발생시에 GCS(Gate Common Short)를 검출할 수 있도록 하는 것이다.For example, as shown in FIG. 4, the common line 300 is wired between the gate lines of the fan out part 200 in the 1G2D test circuit so that a gate common short (GCS) can be detected when a short circuit occurs.

그리고, 도면부호 210의 1G라인은 게이트 라인 테스트만을 위한 신호라인과 별도의 금속을 사용하여 교차되어 지는 부분에서의 단락 검출이 불가능하도록 되어 있으며, 로그라인(220)은 신호가 인가되는 부분은 접촉되고 끝부분의 경우 단선되어 있어 인접라인과의 단락이 검출 가능하게 된다.In addition, the 1G line of the reference numeral 210 is not possible to detect a short circuit in the intersection portion using a separate metal and a signal line for the gate line test only, the log line 220 is in contact with the portion to which the signal is applied In the case of the end part, it is disconnected and a short circuit with an adjacent line is detectable.

상기에서 설명한 바와 같이, 본 발명에 따른 로그라인 단선시험이 가능한 TFT 어레이 패널구조에 있어서는 다음과 같은 효과가 있다.As described above, the TFT array panel structure capable of the log line disconnection test according to the present invention has the following effects.

본 발명에 따른 TFT 어레이 패널구조는 기존 1G2D 방식에서 GGS 검출이 불가능하였던 것을 팬아웃 부분에 공통라인을 이용하여 GGS를 검출할 수 있음은 물론,로그 라인의 단락 테스트가 불가능하였던 구조를 개선하여 1G2D 어레이 테스트시에 GGSDML 테스트가 가능하여, 셀 테스트 및 GGS의 검출을 사전에 테스트 할 수 있어 TFT 어레이 패널의 수율 향상을 할 수 있다.The TFT array panel structure according to the present invention can detect the GGS using the common line in the fanout part, which is impossible to detect the GGS in the existing 1G2D method, and also improves the structure in which the short circuit test of the log line was not possible, thereby improving the 1G2D. The GGSDML test is possible at the time of array test, and the cell test and the detection of the GGS can be tested in advance to improve the yield of the TFT array panel.

또한, 셀 테스트시 로그 배선의 단락은 개별 신호라인에 과부하로 인하여 셀 테스트 장비가 다운되게 되어 셀 테스트 전에 로그 배선의 단락 테스트가 반드시 이루어져야 하는데, 어레이 테스트시 로그 배선간의 단락을 검출할 수 있어 셀 투입전에 패널의 수리 등을 통하여 어레이 패널의 수율을 향상시킬 수 있고, 로그 단락 생략으로 인한 셀 테스트시 패널 파손을 줄일 수 있어 셀 패널 수율을 향상시킬 수 있게 된다.In addition, the short circuit of the log wiring during the cell test requires the cell test equipment to be shut down due to the overload of the individual signal lines, so the short circuit test of the log wiring must be performed before the cell test. It is possible to improve the yield of the array panel through the repair of the panel before the input, and to reduce the panel breakage during the cell test due to the omission of the log short, thereby improving the cell panel yield.

한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. .

Claims (4)

어레이 패널 제작완료후, 신호배선의 PDI-O/S 테스트를 사용하고 있는 2G2D 방식에서 1G2D 방식으로 변경시에 로그(LOG : Line On Glass)라인의 단락(Short) 테스트가 가능하도록 한 패널 구조에 있어서,After the fabrication of the array panel, the panel structure is designed to enable short test of the LOG (Line On Glass) line when changing from 2G2D method to 1G2D method using PDI-O / S test of signal wiring. In GGS(Gate Gate Short) 검출과 셀 테스트(Cell Test) 전에 로그 라인(LOG Line)의 단락 테스트가 정전기 등에 의해 가능하도록 PDI 공통 패드의 신호배선의 연장선이 게이트 라인의 팬 아웃(Fan out)의 라인 사이사이에 공통라인(Common Line)이 형성되는 것을 특징으로 하는 로그라인 단선시험이 가능한 TFT 어레이 패널구조.An extension line of the signal wiring of the PDI common pad is a fan out line of the gate line so that a gate gate short (GGS) detection and a short circuit test of the log line before the cell test can be performed by static electricity or the like. A TFT array panel structure capable of a log line disconnection test, characterized in that a common line is formed between. 제 1항에 있어서, 상기 공통라인(Common Line)은 팬 아웃에 사용되는 게이트 금속라인(Metal Line)과 상이한 금속을 사용하는 것을 특징으로 하는 로그라인 단선시험이 가능한 TFT 어레이 패널구조.The TFT array panel structure of claim 1, wherein the common line uses a different metal from the gate metal line used for the fan out. 제 1항에 있어서, 상기 패널 구조는 정전기에 의해 단락이 검출되도록 PDI 공통패드의 신호배선의 연장선이 게이트 라인의 팬 아웃 라인의 사이에 형성되는 것을 특징으로 하는 로그라인 단선시험이 가능한 TFT 어레이 패널구조.The TFT array panel according to claim 1, wherein an extension line of a signal wiring of the PDI common pad is formed between the fan out lines of the gate line so that a short circuit is detected by static electricity. rescue. 제 3항에 있어서, 상기 게이트 라인은 게이트 라인의 테스트만을 위한 신호라인과 별도의 금속을 사용하여 교차되어지는 것을 특징으로 하는 로그라인 단선시험이 가능한 TFT 어레이 패널구조.4. The TFT array panel structure as claimed in claim 3, wherein the gate line is crossed by using a separate metal from a signal line for testing the gate line only.
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WO2020103252A1 (en) * 2018-11-22 2020-05-28 惠科股份有限公司 Substrate, display panel and display device
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WO2019174099A1 (en) * 2018-03-12 2019-09-19 武汉华星光电半导体显示技术有限公司 Array substrate and oled display panel
US10707288B2 (en) 2018-03-12 2020-07-07 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. TFT array substrate and OLED display panel
WO2020103252A1 (en) * 2018-11-22 2020-05-28 惠科股份有限公司 Substrate, display panel and display device

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