KR102229424B1 - Semiconductor device with negative differential transconductance and manufacturing method thereof - Google Patents

Abstract

Disclosed is a semiconductor device with a negative differential transfer conductance characteristic. The semiconductor device according to the present invention comprises: a substrate; a gate electrode formed on the substrate; a gate insulation film formed on the gate electrode; a first oxide semiconductor channel layer formed on the gate insulation film and having a predefined first conductivity; a second oxide semiconductor channel layer formed on the gate insulation film and formed to contact one side of the first oxide semiconductor channel layer while covering a partial upper surface of the first oxide semiconductor channel layer, and having a second conductivity lower than the first conductivity; and a source electrode formed to contact the gate insulating film and the first oxide semiconductor channel layer, and a drain electrode formed to contact the gate insulating film and the second oxide semiconductor channel layer. The first oxide semiconductor channel layer forms a threshold voltage lower than the second oxide semiconductor channel layer, and the first oxide semiconductor channel layer and the second oxide semiconductor channel layer are sequentially switched to an ON state according to a gate voltage applied from the gate electrode, such that the current in the drain electrode shows the negative differential transfer conductance (NDT) characteristic.

Description

A semiconductor device having a negative differential transfer conductance characteristic, and a manufacturing method thereof {SEMICONDUCTOR DEVICE WITH NEGATIVE DIFFERENTIAL TRANSCONDUCTANCE AND MANUFACTURING METHOD THEREOF}

The present invention relates to a semiconductor device having a negative differential transfer conductance characteristic, and in particular, the negative differential transfer conductance characteristic of a structure in which the manufacturing process is much simpler and the manufacturing cost is reduced compared to the prior art without being limited by the process design as a simplified structure. It relates to a semiconductor device having.

Further, the present invention relates to a method of manufacturing the semiconductor device.

In general, in a semiconductor device, the negative differential transfer conductance ("NDT") and the negative differential resistance ("NDR") refer to the vibration peak characteristics of the output current or voltage appearing at specific bias points.

In particular, the above NDT characteristic shows a number of current vibration peaks in which the current decreases even when the voltage increases at various specific bias points. As such, the vibration peak characteristics of the output current, such as diode characteristics having multiple threshold voltages, can be very promisingly used in next-generation computing devices such as multi-logic functions, multi-value logic processing, and probability data processing. For example, using these NDT characteristics, a device that uses the ternary system of 3 logic values 0, 1, and 2 operates at a much higher speed while consisting of only 60% of the components than a device using only the binary system of 0 and 10,000. Because of this, it is possible to achieve miniaturization, low power consumption, and ultra-high speed of the semiconductor chip.

These NDT characteristics are generally observed in existing Esaki diodes, resonant tunneling diodes, or single electron transistors, but the Esaki diodes have two or more current oscillation peaks due to the mechanism. It is difficult to obtain, and the resonance tunneling diode and the single-electron transistor are difficult to put into practical use due to difficult driving conditions such as a complicated manufacturing process or a cryogenic environment.

Recently, as shown in FIG. 1A, a metal-oxide-semiconductor field-effect transistor (MOSFET) having a structure having ^{a gate-type Si p +} -in ^{+ ultra-thin body (UTB) channel disposed on an SOI substrate.} ) Has been suggested. As shown in FIG. 1B, a Λ-shaped NDT peak characteristic is realized in such a transistor with a clear current I _{D at a specific gate voltage V G at room temperature.} 1A to 1B are related to a conventional semiconductor device having NDT characteristics, and FIG. 1A is a schematic structural diagram thereof, and FIG. 1B is a graph showing current I _{D characteristics according to its gate voltage V G.}

However, in the conventional structure as described above, since both the p-type semiconductor layer and the n-type semiconductor layer must be formed in one device, as shown in FIG. 1A, the p-type semiconductor material and the n-type semiconductor material If the process conditions of are different, there is a problem that several conditions must be considered during the manufacturing process and the process design is limited.

1. Unexamined Patent Publication No. 10-2017-0109457 (2017. 9. 29)

2. Unexamined Patent Publication No. 10-2018-0135350 (2018. 12. 20)

3.Sejoon Lee et al., Scientific Reports volume 7, Article number: 11065 (2017)

An object of the present invention is to provide a semiconductor device having a negative differential transfer conductance characteristic of a structure in which the manufacturing process is much simpler and the manufacturing cost is reduced than the conventional one without being restricted by the process design as a simplified structure than the prior art, and a method of manufacturing the same. .

A semiconductor device according to an aspect of the present invention for solving the above problem includes a substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, and a predefined agent formed on the gate insulating film. A first oxide semiconductor channel layer having 1 conductivity, and formed on the gate insulating layer and formed to contact one side of the first oxide semiconductor channel layer while covering a portion of the upper surface of the first oxide semiconductor channel layer. A second oxide semiconductor channel layer having a second conductivity lower than the conductivity, a source electrode formed to contact the gate insulating film and the first oxide semiconductor channel layer, respectively, and the gate insulating film and the second oxide semiconductor channel layer, respectively. And a drain electrode formed so that the first oxide semiconductor channel layer has a lower threshold voltage than the second oxide semiconductor channel layer, and the first oxide semiconductor channel layer and the second oxide semiconductor channel layer are the gate electrode Each of the currents at the drain electrode exhibits a negative differential transconductance (NDT) characteristic by switching to the ON state in turn according to the gate voltage applied at.

In addition, optionally, the composition of the first oxide semiconductor channel layer and the second oxide semiconductor channel layer may include at least one of silicon indium zinc oxide (SiInZnO) and silicon tin oxide (SiZnSnO).

In addition, optionally, the first oxide semiconductor channel layer and the second oxide semiconductor channel layer may have a silicon content in the range of 0.001 to 30 wt%.

Also, optionally, the first oxide semiconductor channel layer may have a lower silicon content than the second oxide semiconductor channel layer.

In addition, optionally, the second oxide semiconductor channel layer may have a silicon content in the range of 0.01 to 30 wt%.

In addition, optionally, the composition of the first oxide semiconductor channel layer and the second oxide semiconductor channel layer is aluminum (Al), gallium (Ga), hafnium (Hf), zirconium (Zr), lithium (Li), potassium (K). ), titanium (Ti), germanium (Ge), and niobium (Nb), but the composition of the first oxide semiconductor channel layer is relatively lower than that of the second oxide semiconductor channel layer It may contain the dopant.

Also, optionally, each thickness of the first oxide semiconductor channel layer and the second oxide semiconductor channel layer may range from 10 to 200 nm.

Also, optionally, the first oxide semiconductor channel layer may have a greater thickness than the second oxide semiconductor channel layer.

In addition, optionally, the composition of the gate electrode may include a highly doped silicon substrate, indium tin oxide (ITO), gallium zinc oxide (GZO), and indium gallium zinc oxide; IGZO), Indium Gallium Oxide (IGO), Indium Zinc Oxide (IZO), Indium Oxide (In ₂ O ₃ ), Si, Mo, Al, Ag, Au, Cu, and Ta It may include one or more selected from the group.

In addition, optionally, the composition of the gate insulating layer is silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), and tantalum oxide (Ta ₂ O ₅ ), at least one selected from the group consisting of barium-strontium-titanium-oxygen compounds (Ba-Sr-Ti-O), and bismuth-zinc-niobium-oxygen compounds (Bi-Zn-Nb-O) Can include.

In addition, optionally, the composition of the substrate is a silicon substrate doped with a high concentration, polyimide (PI), polyamide (PA), polyamide-imide, polyurethane (polyurethane, PU). ), polyurethane acrylate (PUA), polyacrylamide (PA), polyethylene terephthalate (PET), polyether sulfone (PES), polyethylene naphthalate (PEN), Polycarbonate (PC), polymethylmethacrylate (PMMA), polyetherimide (PEI), polydimethylsiloxane (PDMS), polyethylene (PE), polyvinyl alcohol ( At least one selected from the group consisting of polyvinyl alcohol, PVA), polystyrene (PS), biaxially oriented PS (BOPS), acrylic resin, silicone resin, fluorine resin, modified epoxy resin, silicone, glass and tempered glass It may include.

In addition, optionally, the substrate, the gate electrode, and the gate insulating layer may be ^{a p ++} -Si substrate or an N ⁺⁺ -Si substrate _{having a silicon oxide (SiO 2} ) layer formed thereon.

In addition, optionally, the composition of the source electrode and the drain electrode is gold (Au), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), tungsten (W), molybdenum (Mo), ITO It may include at least one selected from the group consisting of (Indium Tin Oxide) and ISO (Indium Silicon Oxide).

In addition, a method of manufacturing a semiconductor device according to another aspect of the present invention includes the steps of sequentially forming a gate electrode and a gate insulating film on a substrate, and a first oxide semiconductor having a predefined first conductivity on the gate insulating film. Forming a channel layer, and a second oxide semiconductor channel layer having a second conductivity lower than the first conductivity and covering a portion of the top surface of the first oxide semiconductor channel layer, and one side of the first oxide semiconductor channel layer Forming a source electrode on the gate insulating layer to contact the gate insulating layer, forming a source electrode to contact the gate insulating layer and the first oxide semiconductor channel layer, respectively, and contacting the drain electrode to the gate insulating layer and the second oxide semiconductor channel layer, respectively And forming to be formed.

Also, optionally, the first oxide semiconductor channel layer may be formed by depositing under an oxygen flow rate lower than that of the second oxide semiconductor channel layer.

In addition, optionally, the first oxide semiconductor channel layer may be formed by depositing in an atmosphere containing at least one _{of argon (Ar) and nitrogen (N 2 ).}

Also, optionally, the second oxide semiconductor channel layer may be formed by depositing in an atmosphere containing _{oxygen (O 2 ).}

In addition, optionally, the first oxide semiconductor channel layer and the second oxide semiconductor channel layer are formed by depositing in an atmosphere containing _{at least one of argon (Ar) and nitrogen (N 2} ) and oxygen (O _{2 ), the} The first oxide semiconductor channel layer may be formed by depositing at a lower oxygen partial pressure than the second oxide semiconductor channel layer.

In addition, optionally, when the first oxide semiconductor channel layer is deposited, the partial pressure of the oxygen is adjusted to a range of 40% or less, and when the second oxide semiconductor channel layer is deposited, the partial pressure of the oxygen is in the range of 1 to 50%. Can be adjusted to

Also, optionally, the first oxide semiconductor channel layer may be deposited and formed by applying a higher source power than the second oxide semiconductor channel layer.

In addition, optionally, when the first oxide semiconductor channel layer is deposited, the source power is adjusted to a range of 20 to 300 W, and when the second oxide semiconductor channel layer is deposited, the source power is adjusted to a range of 10 to 200 W. I can...

The semiconductor device of the present invention is composed of a single-type oxide semiconductor material in one semiconductor device without the need to form both p-type and n-type semiconductor layers on one semiconductor device as in the prior art, but the composition is adjusted to have a difference in conductivity between them. Since it is composed of a simple structure in which the two oxide semiconductor channel layers are formed to contact each other and realizes the negative differential transfer conductance characteristic, the manufacturing process is much simpler than the conventional one without being restricted in the process design, and the manufacturing cost is greatly reduced. The semiconductor device of the present invention having negative differential transfer conductance characteristics can be very promisingly applied to next-generation computing devices such as multiple logic functions, multiple value logic processing, and probability data processing.

1A to 1B are related to a conventional semiconductor device having NDT characteristics, and FIG. 1A is a schematic structural diagram thereof, and FIG. 1B is a graph showing current I _{D characteristics according to its gate voltage V G.}
2 is a schematic cross-sectional view of a semiconductor device having NDT characteristics according to an embodiment of the present invention.
3 is a flowchart illustrating a method of manufacturing a semiconductor device having NDT characteristics according to an embodiment of the present invention.
4A to 4D are schematic views sequentially illustrating detailed processes in the method of manufacturing a semiconductor device having NDT characteristics according to an embodiment of the present invention shown in FIG. 3.
5 is a graph showing a change in drain current according to a change in a gate voltage in a semiconductor device having NDT characteristics manufactured according to an exemplary embodiment of the present invention.

Unlike the prior art, the present invention is composed of only a single layer of semiconductor material in one thin film semiconductor device without forming both p-type and n-type semiconductor material layers on one thin film semiconductor device, but the composition is adjusted to have a difference in conductivity between them. It consists of a simple structure in which the two semiconductor channel layers are formed so as to contact each other.

In the structure of the present invention, the conduction state is sequentially changed according to the voltage input thereto by different threshold voltages formed according to different conductivities between the two semiconductor channel layers. NDT") is effectively implemented. In addition, the structure of the two semiconductor channel layers having a difference in conductivity between each other according to the present invention can be easily formed through, for example, controlling the content of doping elements or oxygen partial pressure ratio or controlling process conditions.

As described above, since the present invention does not have a structure including both p-type and n-type semiconductor materials, unlike the prior art, the manufacturing process is much simpler than the prior art, and the process design is not restricted.

Hereinafter, the present invention will be described in detail with reference to the drawings.

2 is a schematic cross-sectional view of a semiconductor device having NDT characteristics according to an embodiment of the present invention.

Referring to FIG. 2, the semiconductor device 100 of the present invention is formed on a gate electrode 110, a gate insulating layer 114 formed on the gate electrode 110, and the gate insulating layer 114. The first oxide semiconductor channel layer 130 having one conductivity and formed on the gate insulating layer 114 and covering a portion of the top surface of the first oxide semiconductor channel layer 130 and the first oxide semiconductor channel layer 130 A second oxide semiconductor channel layer 140 formed to contact a side surface of the first oxide semiconductor channel layer 130 and having a second conductivity lower than the first conductivity of the first oxide semiconductor channel layer 130, and the gate insulating layer 114 and the first A source electrode 170 formed to contact the oxide semiconductor channel layer 130, and a drain electrode 180 formed to contact the gate insulating layer 114 and the second oxide semiconductor channel layer 140.

In addition, the gate electrode 110 may be positioned on a predetermined substrate (not shown), and the substrate may be a silicon substrate doped with a high concentration, polyimide (PI), polyamide (PA), Polyamide-imide, polyurethane (polyurethane, PU), polyurethane acrylate (PUA), polyacrylamide (PA), polyethylene terephthalate (PET), polyether sulfone (Polyether sulfone, PES), polyethylene naphthalate (PEN), polycarbonate (PC), polymethylmethacrylate (PMMA), polyetherimide (PEI), polydimethylsiloxane (polydimethylsiloxane, PDMS), polyethylene (PE), polyvinyl alcohol (PVA), polystyrene (PS), biaxially oriented PS (BOPS), acrylic resin, silicone resin, fluorine resin, It may be one or more selected from the group consisting of modified epoxy resin, silicon, glass and tempered glass.

In addition, the gate electrode 110 is a silicon substrate doped with a high concentration, transparent conductive oxides of indium tin oxide (ITO), gallium zinc oxide (GZO), and indium gallium zinc oxide. Oxide; IGZO), Indium Gallium Oxide (IGO), Indium Zinc Oxide (IZO), Indium Oxide (In ₂ O ₃ ), Si, Mo, Al, Ag, Au, Cu, and Ta It may be one or more selected from the group consisting of.

In addition, the gate insulating layer 114 includes silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), and tantalum oxide (Ta ₂ O). ₅ ), barium-strontium-titanium-oxygen compounds (Ba-Sr-Ti-O), and bismuth-zinc-niobium-oxygen compounds (Bi-Zn-Nb-O). have. In a preferred embodiment of the present invention, silicon oxide (SiO ₂ ^{) is used as the gate insulating film 114 and the p ++} -Si substrate or N ⁺⁺ -Si substrate on which it is deposited is an integral substrate (not shown). -Gate electrode 110-Can be used as the gate insulating film 114.

In particular, in the present invention, the first oxide semiconductor channel layer 130 and the second oxide semiconductor channel layer 140 are designed to have a difference in conductivity between each other in order to realize the NDT characteristic of the drain current against the gate voltage as described above. do. To this end, the first conductivity of the first oxide semiconductor channel layer 130 is configured to be relatively higher than the second conductivity of the second oxide semiconductor channel layer 140, whereby the first oxide semiconductor channel layer ( 130) has a lower threshold voltage at which a channel is formed than the second oxide semiconductor channel layer 140. Therefore, the first oxide semiconductor channel layer 130 is first turned on at a low gate voltage, and when the gate voltage is increased later and reaches a higher threshold voltage of the second oxide semiconductor channel layer 140 When it is turned on, a vibration peak of the drain current is formed, and the NDT characteristic is realized.

In the present invention, the first oxide semiconductor channel layer 130 and the second oxide semiconductor channel layer 140 are amorphous oxide films, and in one embodiment, such as silicon indium zinc oxide (SiInZnO) and silicon tin oxide (SiZnSnO). In the case of one or more oxide semiconductors, the silicon indium zinc oxide (SiInZnO) and silicon tin oxide zinc (SiZnSnO), the preferred silicon content is in the range of about 0.001 to 30 wt%, preferably 0.01 to 20 wt. It can be in the range of %. The thickness of the first oxide semiconductor channel layer 130 and the second oxide semiconductor channel layer 140 is preferably in the range of approximately 10 to 200 nm.

In addition, in order to increase the first conductivity of the first oxide semiconductor channel layer 130 relatively higher than the second conductivity of the second oxide semiconductor channel layer 140, the following Examples (i) to (vi) It may contain one or more of:

(i) In one embodiment, the first oxide semiconductor channel layer 130 and the second oxide semiconductor channel layer 140 have a strong binding force with oxygen compared to In or Zn, and thus serve as carriers in the amorphous oxide semiconductor. As a dopant that suppresses oxygen vacancy that increases conductivity, for example, aluminum (Al), gallium (Ga), hafnium (Hf), zirconium (Zr), lithium (Li), potassium (K), titanium (Ti), Conductivity of each of the first and second oxide semiconductor channel layers 130 and 140 may be adjusted by including at least one element of germanium (Ge) and niobium (Nb), and at this time, the first oxide semiconductor channel layer 130 May be controlled to have a relatively lower content of the dopant than the second oxide semiconductor channel layer 140; And/or

(ii) In one embodiment, the first oxide semiconductor channel layer 130 may contain a lower silicon content than the second oxide semiconductor channel layer 140, and accordingly, the second oxide semiconductor channel layer ( 140) may preferably contain a silicon content in the range of 0.01 to 30 wt% relative to the total amount; And/or

(iii) In one embodiment, the thickness of the first oxide semiconductor channel layer 130 may be greater than the thickness of the second oxide semiconductor channel layer 140; And/or

(iv) In one embodiment, the first oxide semiconductor channel layer 130 may be formed with a lower oxygen partial pressure than the second oxide semiconductor channel layer 140 when deposited, preferably the first oxide The semiconductor channel layer 130 may be adjusted to a partial pressure of oxygen of about 40% or less, and the second oxide semiconductor channel layer 140 may be adjusted to a partial pressure of oxygen of about 1 to 50%; And/or

(v) In one embodiment, the first oxide semiconductor channel layer 130 is _{deposited in an atmosphere containing at least one of argon (Ar) and nitrogen (N 2} ), and the second oxide semiconductor channel layer 140 is It may be deposited in an atmosphere containing oxygen (O _{2 );} And/or

(vi) In one embodiment, the first oxide semiconductor channel layer 130 may be deposited by applying a higher source power than the second oxide semiconductor channel layer 140 during formation, and preferably, the The first oxide semiconductor channel layer 130 may be applied with a source power in the range of about 20 to 300 W, and the second oxide semiconductor channel layer 140 is in the range of about 10 to 200 W. 130), a lower source power may be applied.

In addition, in the present invention, the source electrode 170 and the drain electrode 180 are gold (Au), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), tungsten (W), molybdenum It may be configured to include at least one selected from the group consisting of (Mo), ITO (Indium Tin Oxide) and ISO (Indium Silicon Oxide).

3 and 4A to 4D are for explaining a method of manufacturing a semiconductor device having NDT characteristics according to an embodiment of the present invention, and FIG. 3 is a flow chart thereof and FIGS. 4A to 4D schematically show detailed processes. to be.

3 and 4A to 4D, the method of manufacturing a semiconductor device having NDT characteristics of the present invention includes the following steps (i) to (iv):

(i) sequentially forming a gate electrode 110 and a gate insulating layer 114 on a substrate (not shown) (S310 to S320, FIG. 4A);

(ii) forming a first oxide semiconductor channel layer 130 on the gate insulating layer 114 (S330, FIG. 4B);

(iii) a second oxide semiconductor channel layer formed on the gate insulating layer 114 and covering a portion of the upper surface of the first oxide semiconductor channel layer 130 and in contact with the side surface of the first oxide semiconductor channel layer 130 Forming 140 (S340, FIG. 4C); And

(iv) forming the source electrode 170 and the drain electrode 180 to contact the gate insulating layer 114 and the first oxide semiconductor channel layer 130 or the second oxide semiconductor channel layer 140, respectively ( S350, Fig. 4d).

In the present invention, the first and second oxide semiconductor channel layers 130 and 140 are formed on the gate insulating layer 114 by Atmospheric Pressure Chemical Vapor Deposition (APCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced (PECVD). Chemical Vapor Deposition (CVD) deposition method such as Chemical Vapor Deposition), PVD (Physical Vapor Deposition) deposition method such as PLD (Pulsed Laser Deposition), thermal deposition, electron beam deposition, sputtering process, printing process , May be formed by any known manufacturing method including a wet solution process, and in one embodiment, patterned using a shadow mask during deposition, or in another embodiment, patterned by a mask pattern and an etching process. have.

In addition, in the present invention, the source electrode 170 and the drain electrode 180 are any known manufacturing method including sputtering method, thermal evaporation method, electron beam evaporation method, CVD evaporation method, sol-gel method, ion plating method, etc. Can be formed.

Hereinafter, preferred embodiments of the present invention will be described in detail below. However, these examples are provided to aid in the overall understanding of the present invention and do not limit the present invention.

Example

In this embodiment, ^{a p ++} _{-Si substrate on which silicon oxide (SiO 2} ) is deposited was used as the integral gate electrode 110 -gate insulating film 114. At this time, the gate electrode 110 becomes a p ⁺⁺ -Si substrate itself.

The first oxide semiconductor channel layer 130 made of SiZnSnO was formed on the substrate by RF sputtering, but was deposited only in a pure argon (Ar) atmosphere in order to increase the conductivity of SiZnSnO during deposition. In this case, the substrate may be rotated so that the deposited thin film has a uniform thickness. Thereafter, the remaining portions except for the region of the first oxide semiconductor channel layer 130 were removed by wet etching by photo etching.

In addition, a second oxide semiconductor channel layer 140 having a lower conductivity is formed so as to be adjacent to the first oxide semiconductor channel layer 130, and argon (Ar) and oxygen (O2) are used to lower the conductivity of SiZnSnO during deposition. Combined and deposited. In this case, the substrate may be rotated so that the deposited thin film has a uniform thickness. Thereafter, the remaining portions of the first oxide semiconductor channel layer 130 and the second oxide semiconductor channel layer 140 except for each region are removed by wet etching by photo etching, and the two channel layers 130 and 140 are joined. The part was left behind and etched. Thereafter, a heat treatment process was performed to improve the density and stability of the produced channel layer.

Thereafter, in order to define a portion to be used as the source electrode 170/drain electrode 180, it was exposed using an etching and lift-off method, and titanium (Ti) and aluminum (Al) were each used by using an electron beam evaporation method and a thermal evaporation method. After forming the stack, the photoresist was removed to form the electrodes 170 and 180.

5 is a graph showing a change in drain current according to a change in a gate voltage in a semiconductor device having NDT characteristics manufactured according to an exemplary embodiment of the present invention.

Referring to FIG. 5, it is observed that a vibration peak of the drain current occurs at a gate voltage in the range of approximately 4 to 6 V. That is, in the semiconductor device of the present invention, since the first oxide semiconductor channel layer 130 having a relatively high conductivity has a lower threshold voltage at which a channel is formed than the second oxide semiconductor channel layer 140, the gate voltage is As it gradually increases, the first oxide semiconductor channel layer 130 is first turned on at a low gate voltage, but the second oxide semiconductor channel layer 140 is turned off. When the size of the oxide semiconductor channel layer 140 reaches a higher threshold voltage, the second oxide semiconductor channel layer 140 is also turned on, thereby forming a vibration peak of the drain current, thereby implementing the NDT characteristic.

As described above, the present invention is composed of a single-type (eg, n-type) oxide semiconductor material in one semiconductor device without the need to form both p-type and n-type semiconductor layers in one semiconductor device as in the prior art, but the conductivity difference between each other It consists of a simple structure in which the two oxide semiconductor channel layers 130 and 140 whose composition is adjusted to have a contact with each other.

In the structure of the present invention, the first oxide semiconductor channel layer 130 of higher conductivity has a lower threshold voltage at which a channel is formed than the second oxide semiconductor channel layer 140 of lower conductivity. According to the voltage, only the first oxide semiconductor channel layer 130 was turned on, but as the input voltage further increased, the second oxide semiconductor channel layer 140 also changed to the ON state, resulting in a vibration peak of current, resulting in a negative differential transfer conductance. (NDT) characteristics are effectively implemented.

In the present invention, the two oxide semiconductor channel layers 130 and 140 having a conductivity difference between each other as described above are easily formed through the aforementioned various means such as, for example, controlling the content of doping elements or oxygen partial pressure ratio or controlling process conditions. As a result, the manufacturing process is much simpler and manufacturing cost is reduced than before without being restricted in the process design.

Above, the above-described preferred embodiments and examples of the present invention are disclosed for the purpose of illustration, and anyone of ordinary skill in the relevant field can make various modifications, changes, additions, etc. within the spirit and scope of the present invention. And such modifications, changes, additions, etc. should be regarded as belonging to the scope of the claims.

100: semiconductor device having NDT characteristics
110: gate electrode
114: gate insulating film
130: first oxide semiconductor channel layer
140: second oxide semiconductor channel layer
170: source electrode
180: drain electrode

Claims (21)

A substrate;
A gate electrode formed on the substrate;
A gate insulating film formed on the gate electrode;
A first oxide semiconductor channel layer formed on the gate insulating layer and having a predefined first conductivity;
A second oxide formed on the gate insulating layer and formed to contact a side surface of the first oxide semiconductor channel layer while covering a partial upper surface of the first oxide semiconductor channel layer, and having a second conductivity lower than the first conductivity A semiconductor channel layer;
A source electrode formed to contact the gate insulating layer and the first oxide semiconductor channel layer, respectively, and a drain electrode formed to contact the gate insulating layer and the second oxide semiconductor channel layer, respectively,
The first oxide semiconductor channel layer has a lower threshold voltage than the second oxide semiconductor channel layer, and the first oxide semiconductor channel layer and the second oxide semiconductor channel layer are sequentially applied according to a gate voltage applied from the gate electrode. A semiconductor device, characterized in that the current at the drain electrode exhibits a negative differential transfer conductance (NDT) characteristic by switching to each ON state. The method of claim 1,
The composition of the first oxide semiconductor channel layer and the second oxide semiconductor channel layer comprises at least one of silicon indium zinc oxide (SiInZnO) and silicon tin oxide (SiZnSnO). The method of claim 2,
The semiconductor device, wherein the first oxide semiconductor channel layer and the second oxide semiconductor channel layer have a silicon content in the range of 0.001 to 30 wt%. The method according to claim 2 or 3,
The semiconductor device, wherein the first oxide semiconductor channel layer has a lower silicon content than the second oxide semiconductor channel layer. The method of claim 4,
The semiconductor device, characterized in that the second oxide semiconductor channel layer has a silicon content in the range of 0.01 to 30 wt%. The method according to claim 1 or 2,
The composition of the first oxide semiconductor channel layer and the second oxide semiconductor channel layer is aluminum (Al), gallium (Ga), hafnium (Hf), zirconium (Zr), lithium (Li), potassium (K), titanium (Ti ), germanium (Ge) and niobium (Nb), but the composition of the first oxide semiconductor channel layer contains the dopant in a relatively lower content than the composition of the second oxide semiconductor channel layer A semiconductor device, characterized in that. The method according to claim 1 or 2,
Each thickness of the first oxide semiconductor channel layer and the second oxide semiconductor channel layer is in a range of 10 to 200 nm. The method according to claim 1 or 2,
The semiconductor device, wherein the first oxide semiconductor channel layer has a larger thickness than the second oxide semiconductor channel layer. The method according to claim 1 or 2,
The composition of the gate electrode is a silicon substrate doped with a high concentration, indium tin oxide (ITO), gallium zinc oxide (GZO), indium gallium zinc oxide (IGZO), and indium oxide. Gallium (Indium Gallium Oxide; IGO), indium zinc oxide (Indium Zinc Oxide; IZO), indium oxide (In ₂ O ₃ ), Si, Mo, Al, Ag, Au, one or more selected from the group consisting of Cu and Ta A semiconductor device comprising a. The method according to claim 1 or 2,
The composition of the gate insulating layer is silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), Characterized in that it comprises at least one selected from the group consisting of barium-strontium-titanium-oxygen compounds (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compounds (Bi-Zn-Nb-O) Semiconductor device. The method according to claim 1 or 2,
The composition of the substrate is a highly doped silicon substrate, polyimide (PI), polyamide (PA), polyamide-imide, polyurethane (polyurethane, PU), polyurethane acrylic Polyurethaneacrylate (PUA), polyacrylamide (PA), polyethylene terephthalate (PET), polyether sulfone (PES), polyethylene naphthalate (PEN), polycarbonate, PC), polymethylmethacrylate (PMMA), polyetherimide (PEI), polydimethylsiloxane (PDMS), polyethylene (PE), polyvinyl alcohol (PVA) , Polystyrene (PS), biaxially oriented polystyrene (biaxially oriented PS, BOPS), acrylic resin, silicone resin, fluorine resin, modified epoxy resin, silicon, glass, and tempered glass. Semiconductor device. The method according to claim 1 or 2,
The substrate, the gate electrode, and the gate insulating layer form a p ⁺⁺ -Si substrate or an N ⁺⁺ -Si substrate in which a _{silicon oxide (SiO 2) layer is formed on an upper surface thereof.} The method according to claim 1 or 2,
The composition of the source electrode and the drain electrode is gold (Au), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), tungsten (W), molybdenum (Mo), and ITO (Indium Tin Oxide). And at least one selected from the group consisting of ISO (Indium Silicon Oxide). Sequentially forming a gate electrode and a gate insulating film on the substrate;
Forming a first oxide semiconductor channel layer having a first predefined conductivity on the gate insulating layer;
A second oxide semiconductor channel layer having a second conductivity lower than the first conductivity is disposed on the gate insulating layer to contact one side of the first oxide semiconductor channel layer while covering a portion of the top surface of the first oxide semiconductor channel layer. Forming;
And forming a source electrode to contact the gate insulating layer and the first oxide semiconductor channel layer, respectively, and forming a drain electrode to contact the gate insulating layer and the second oxide semiconductor channel layer, respectively. A method of manufacturing a semiconductor device, characterized in that. The method of claim 14,
The method of manufacturing a semiconductor device, wherein the first oxide semiconductor channel layer is formed by depositing under an oxygen flow rate lower than that of the second oxide semiconductor channel layer. The method of claim 14,
The first oxide semiconductor channel layer is a method of manufacturing a semiconductor device, characterized in that formed by depositing in an atmosphere containing at least one of argon (Ar) and nitrogen (N _{2 ).} The method of claim 14,
The second oxide semiconductor channel layer is a method of manufacturing a semiconductor device, characterized in that formed by depositing in an atmosphere containing _{oxygen (O 2 ).} The method of claim 14,
The first oxide semiconductor channel layer and the second oxide semiconductor channel layer are formed by depositing in an atmosphere containing _{at least one of argon (Ar) and nitrogen (N 2} ) and oxygen (O _{2 ), the first oxide semiconductor channel} A method of manufacturing a semiconductor device, characterized in that the layer is formed by depositing at a lower oxygen partial pressure than the second oxide semiconductor channel layer. The method of claim 18,
When the first oxide semiconductor channel layer is deposited, the partial pressure of oxygen is adjusted to a range of 40% or less, and when the second oxide semiconductor channel layer is deposited, the partial pressure of oxygen is adjusted to a range of 1 to 50%. Method of manufacturing a semiconductor device as described above. The method of claim 14,
The method of manufacturing a semiconductor device, wherein the first oxide semiconductor channel layer is deposited and formed by applying a higher source power than the second oxide semiconductor channel layer. The method of claim 20,
When the first oxide semiconductor channel layer is deposited, the source power is adjusted to a range of 20 to 300 W, and when the second oxide semiconductor channel layer is deposited, the source power is controlled to a range of 10 to 200 W. Device manufacturing method.

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