CN111129150B - Ferroelectric thin film transistor and manufacturing method thereof - Google Patents
Ferroelectric thin film transistor and manufacturing method thereof Download PDFInfo
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- CN111129150B CN111129150B CN201911149614.5A CN201911149614A CN111129150B CN 111129150 B CN111129150 B CN 111129150B CN 201911149614 A CN201911149614 A CN 201911149614A CN 111129150 B CN111129150 B CN 111129150B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
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Abstract
The invention discloses a ferroelectric thin film transistor and a manufacturing method thereof, wherein the ferroelectric thin film transistor comprises a substrate, a grid electrode, a semiconductor layer, a source electrode and a drain electrode which are sequentially arranged on the substrate, and a three-layer structure ferroelectric dielectric layer positioned between the grid electrode and the semiconductor layer, wherein the three-layer structure ferroelectric dielectric layer comprises a first insulating layer arranged on the grid electrode, a dielectric layer arranged on the first insulating layer and a second insulating layer arranged on the dielectric layer. The ferroelectric thin film transistor has the advantages that the problem that the conventional ferroelectric thin film transistor is likely to be broken down and have leakage current is solved by arranging the first insulating layer and the second insulating layer.
Description
Technical Field
The invention relates to the technical field of thin film transistors, in particular to a ferroelectric thin film transistor and a manufacturing method thereof.
Background
The thin film transistor is one of field effect transistors, is widely used in novel display technologies such as TFT-LCD, AM-OLED, AM-QLED, Mini/Micro LED and the like, and is used as 'ON/OFF' of a display pixel of a control panel. A dielectric layer is arranged between the semiconductor layer and the grid electrode, plays a role in isolating conduction of an upper layer and a lower layer, and is an important part in a transistor structure. Generally, organic TFT, metal oxide TFT, and silicon-based TFT are made of low-cost and high-dielectric-property polymer material such as PMMA, and high-dielectric-constant SiO2And the like. They have higher dielectric properties and lower price, and meet the requirements of various types of TFTs on the market at present. But does not contribute to the improvement of the carrier concentration and mobility in the channel of the "semiconductor layer". One of the most important electrical performance indexes of a TFT is "electron mobility and concentration" in a channel, and high electron mobility is an important index for evaluating a high-performance TFT. Thus, scientists and engineers have introduced "ferroelectric materials" as dielectric layers of TFTs for changing and regulating the mobility, concentration and transport direction of carriers (electrons or holes) in the channel, i.e. changing and regulating the resistance characteristics of the channel. However, the thin film transistor using the "ferroelectric material" may cause an unstable output current, and thus has a certain defect.
Disclosure of Invention
In order to overcome the disadvantages of the prior art, an object of the present invention is to provide a ferroelectric thin film transistor, which solves the problems of "breakdown" and leakage current of the conventional ferroelectric thin film transistor.
The second objective of the present invention is to provide a method for manufacturing a ferroelectric thin film transistor, which is used for manufacturing the ferroelectric thin film transistor.
The invention also aims to provide another preparation method of the ferroelectric thin film transistor, which is used for preparing the ferroelectric thin film transistor.
One of the purposes of the invention is realized by adopting the following technical scheme:
a ferroelectric thin film transistor comprising:
a substrate;
the grid is arranged on the substrate;
a first insulating layer disposed on the gate electrode;
the dielectric layer is made of ferroelectric materials and arranged on the first insulating layer;
a second insulating layer disposed on the dielectric layer;
a semiconductor layer disposed on the second insulating layer; and the number of the first and second groups,
and the source electrode and the drain electrode are arranged at intervals, are electrically connected with the semiconductor layer and are used for forming a transmission channel in the semiconductor layer.
Preferably, the source electrode and the drain electrode are both arranged on the upper surface of the semiconductor layer.
The ferroelectric thin film transistor further includes a source conductive layer disposed between the second insulating layer and the semiconductor layer, the drain electrode disposed on the semiconductor layer and the source electrode disposed on the source conductive layer.
Preferably, the thickness of the first insulating layer and the second insulating layer is smaller than the thickness of the dielectric layer.
Preferably, the first insulating layer and the second insulating layer are made of metal oxide.
Preferably, the metal oxide is Al2O3、MgO、HfO2、Y2O3、ZrO2One or more ofAnd (4) seed preparation.
Preferably, the first insulating layer and the second insulating layer are one or more of silicon oxide, silicon nitride, and silicon oxynitride.
Preferably, the ferroelectric material used for making the dielectric layer is BiFeO3、BaTiO3、CaTiO3、PbTiO3And lead zirconate titanate piezoelectric ceramics; the substrate is a rigid substrate made of glass or plastic or sapphire or quartz; or the substrate is a flexible substrate made of PET or PI; the grid is made of one or more of chromium, aluminum, gold and alloy thereof; the semiconductor layer is made of organic polymer materials, metal oxides or silicon-based materials.
The second purpose of the invention is realized by adopting the following technical scheme:
a preparation method of the ferroelectric thin film transistor comprises the following steps:
arranging a substrate;
forming a gate on the substrate;
forming a first insulating layer on the gate electrode;
forming a dielectric layer made of a ferroelectric material on the first insulating layer;
forming a second insulating layer on the dielectric layer;
forming a semiconductor layer corresponding to the gate electrode on the second insulating layer; and
and forming a source electrode and a drain electrode on the semiconductor layer, and arranging the source electrode and the drain electrode at a certain distance to form a channel.
Preferably, the first insulating layer and the second insulating layer are each provided with a thickness smaller than that of the dielectric layer.
The third purpose of the invention is realized by adopting the following technical scheme:
a preparation method of the ferroelectric thin film transistor comprises the following steps:
arranging a substrate;
forming a gate on the substrate;
forming a first insulating layer on the gate electrode;
forming a dielectric layer made of a ferroelectric material on the first insulating layer;
forming a second insulating layer on the dielectric layer;
forming a source conductive layer on the second insulating layer;
forming a semiconductor layer corresponding to the gate electrode on the source conductive layer;
and forming a drain electrode on the semiconductor layer and a source electrode on the source electrode conducting layer, and enabling the source electrode and the drain electrode to be separated by a certain distance to form a channel.
Preferably, the first insulating layer and the second insulating layer are each provided with a thickness smaller than that of the dielectric layer.
Additional features of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
Drawings
Fig. 1A is a schematic structural diagram of a ferroelectric thin film transistor in the prior art, fig. 1B and 1C are schematic operation diagrams of the ferroelectric thin film transistor in the prior art, and fig. 1D is a schematic diagram of a dielectric conduction/leakage current of the ferroelectric thin film transistor in the prior art;
FIG. 2 is a schematic structural diagram of a ferroelectric thin film transistor according to an embodiment of the present invention;
fig. 3A is a schematic cross-sectional structure diagram of a ferroelectric thin film transistor according to an embodiment of the present invention, and fig. 3B and 3C are schematic diagrams of the operation of the ferroelectric thin film transistor according to the embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a ferroelectric thin film transistor according to another embodiment of the present invention;
FIG. 5 is an I-V characteristic curve of each example and comparative example.
In the figure: 1. a substrate; 2. a gate electrode; 3. a first insulating layer; 4. a ferroelectric layer; 5. a second insulating layer; 6. a semiconductor layer; 7. a source electrode conductive layer; 8. a source electrode; 9. and a drain electrode.
Detailed Description
The present invention will now be described in more detail with reference to the accompanying drawings, in which the description of the invention is given by way of illustration and not of limitation. The various embodiments may be combined with each other to form other embodiments not shown in the following description.
In the description of the present invention, it should be noted that, for the terms of orientation, such as "central", "lateral", "longitudinal", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., it indicates that the orientation and positional relationship shown in the drawings are based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, but does not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated without limiting the specific scope of protection of the present invention.
Fig. 1A is a schematic view showing a structure of a ferroelectric thin film transistor in the related art. The conventional ferroelectric thin film transistor includes a semiconductor layer, a gate electrode and a dielectric layer disposed therebetween, the dielectric layer is made of a ferroelectric material, and fig. 1B and 1C are schematic diagrams illustrating a change of carriers in a channel of the thin film transistor when the dielectric layer of the ferroelectric material is in "up-polarized" and "down-polarized" states. A ferroelectric material is applied to a thin film transistor as a material with a high dielectric constant, but when the ferroelectric material is in a thin film form (thin film), a certain carrier migration activity still exists in the crystal, as shown in fig. 1D, electrons in a semiconductor layer and electrons in the ferroelectric layer are both likely to migrate to opposite positions, so that a semiconductor layer and a gate are in a conducting state at a certain moment, the thin film transistor is "broken down", and meanwhile, leakage current is generated, and the electron concentration in a channel is reduced; for electronic devices with low precision, the influence of low leakage current of the dielectric layer of the thin film transistor is not large, and for electronic devices with high precision and high requirements, even small leakage current has an influence on the performance of the device.
In order to solve the above problems, the present invention provides a ferroelectric thin film transistor, which can completely eliminate the phenomenon (conduction and leakage) that electrons (holes) in a channel of a semiconductor layer and electrons (holes) in a ferroelectric layer migrate to each other, but still retain negative shielding charges generated by electrons concentrated at an upper interface when in an up-polarization state, and a shielding electric field can penetrate through a first insulating layer and a second insulating layer to provide a driving force for the migration of electrons in the channel, thereby improving the migration rate, improving the transmission characteristics of a TFT, and finally improving the response speed and sensitivity of the thin film transistor.
As shown in fig. 2, 3A, 3B and 3C, the ferroelectric thin film transistor includes a substrate 1, a gate electrode 2, a semiconductor layer 6, a source electrode 8 and a drain electrode 9 sequentially disposed on the substrate 1, and further includes a three-layer structure ferroelectric dielectric layer between the gate electrode 2 and the semiconductor layer 6, the three-layer structure ferroelectric dielectric layer including a first insulating layer 3 disposed on the gate electrode 2, a dielectric layer disposed on the first insulating layer 3 and a second insulating layer 5 disposed on the dielectric layer. Hereinafter, for convenience of description, the dielectric layer made of a ferroelectric material is named as a ferroelectric layer 4.
The first insulating layer 3 disposed between the gate 2 and the ferroelectric layer 4 can prevent electrons in the gate 2 and electrons in the ferroelectric layer 4 from migrating to the opposite position when the ferroelectric layer 4 is in a lower polarization; the second insulating layer 5 disposed between the semiconductor layer 6 and the ferroelectric layer 4 can prevent electrons in the semiconductor layer 6 and electrons in the ferroelectric layer 4 from migrating to each other when the ferroelectric layer 4 is in the upper polarization, thereby preventing the thin film transistor from being 'broken down' and generating a leakage current. The first insulating layer 3 and the second insulating layer 5 are respectively arranged on the upper side and the lower side of the ferroelectric layer 4, so that the phenomenon of leakage current can be completely eliminated, and the requirements of high-precision and high-requirement electronic devices can be met.
The present invention provides the above ferroelectric thin film transistor of a horizontal channel and the above ferroelectric thin film transistor of a vertical channel based on thin film transistors of different types of channels, the specific structures of which will be described below.
In some embodiments, a horizontal channel ferroelectric thin film transistor has a structure including a substrate 1, a gate electrode 2 disposed on the substrate 1, a first insulating layer 3 disposed on the gate electrode 2, a ferroelectric layer 4 disposed on the first insulating layer 3, a second insulating layer 5 disposed on a dielectric layer, a semiconductor layer 6 disposed on the second insulating layer 5, and a source electrode 8 and a drain electrode 9 disposed on the semiconductor layer 6, wherein the semiconductor layer 6 corresponds to the gate electrode 2; the source electrode 8 and the drain electrode 9 are spaced apart by a distance, and a channel is formed between the source electrode 8 and the drain electrode 9.
In other embodiments, a vertical channel ferroelectric thin film transistor has a structure including a substrate 1, a gate electrode 2 disposed on the substrate 1, a first insulating layer 3 disposed on the gate electrode 2, a ferroelectric layer 4 disposed on the first insulating layer 3, a second insulating layer 5 disposed on the dielectric layer, a semiconductor layer 6 disposed on the second insulating layer 5, the semiconductor layer 6 being disposed corresponding to the gate electrode 2, and a source electrode 8 and a drain electrode 9, and further includes a source conductive layer 7, the source conductive layer 7 being disposed between the second insulating layer 5 and the semiconductor layer 6, the drain electrode 9 being disposed on the semiconductor layer 6 and the source electrode 8 being disposed on the source conductive layer 7, the source electrode 8 and the drain electrode 9 being spaced apart from each other, and a channel being formed between the source electrode 8 and the drain electrode 9.
Since the first insulating layer 3 and the second insulating layer 5 are respectively disposed on the upper and lower sides of the ferroelectric layer 4, in order to prevent the electric field in the ferroelectric layer 4 from being shielded and the control of the channel from being lost, the thicknesses of the first insulating layer 3 and the second insulating layer 5 need to be limited, the ferroelectric dielectric layer (ferroelectric material) plays a dielectric effect (blocking and storing charges), the insulating semiconductor layer 6 and the gate electrode 2 need to have a relatively large thickness, generally between 100 and 200nm, while the thicknesses of the first insulating layer 3 and the second insulating layer 5 vary with the thickness of the ferroelectric layer 4, preferably 1/10 of the ferroelectric layer 4 is optimal, i.e. 10nm to 20 nm. When the thicknesses of the first insulating layer 3 and the second insulating layer 5 are less than 8nm, electrons have quantum tunneling effect, a small amount of leakage current still occurs, and the blocking effect is poor; when the thicknesses of the first insulating layer 3 and the second insulating layer 5 are greater than 20nm, the first insulating layer 3 and the second insulating layer 5 weaken the electric field in the ferroelectric layer 4, and thus the control of the channel cannot be performed. Experiments prove that the first insulating layer 3 and the second insulating layer 5 have the preferable thickness of 10nm to 20nm, the processing cost is relatively lower, and the anti-leakage effect is good.
The thicknesses of the first insulating layer 3 and the second insulating layer 5 may be the same or different, and may be between 10nm (inclusive) and 20nm (inclusive), and for convenience of processing, the thicknesses of the first insulating layer 3 and the second insulating layer 5 may be generally set to be the same.
The first insulating layer 3 and the second insulating layer 5 may be made of metal oxide including, but not limited to, aluminum oxide (Al)2O3) Magnesium oxide (MgO), hafnium oxide (HfO)2) Yttrium oxide (Y)2O3) Zirconium oxide (ZrO)2) One or more of tantalum oxide, titanium oxide and zinc oxide; the first insulating layer 3 and the second insulating layer 5 further include, but are not limited to, one or more of silicon oxide, silicon nitride, and silicon oxynitride.
In addition, the ferroelectric material used to make the dielectric layer may be a ferroelectric oxide with high dielectric constant and high ferroelectric polarization remnant value, including but not limited to BiFeO3、BaTiO3、CaTiO3、PbTiO3And lead zirconate titanate piezoelectric ceramics; the substrate 1 may be a rigid substrate, the material of which includes but is not limited to glass or plastic or sapphire or quartz; the substrate may also be a flexible substrate, the material of which includes but is not limited to PET or PI; the material of the grid 2 is one or more of chromium, aluminum, gold and alloy thereof; the material of the semiconductor layer 6 is an organic polymer material, a metal oxide or a silicon-based material. The material of the source electrode 8 and the drain electrode 9 includes, but is not limited to, Au, Ag, Cr, Al, conductive glass (ITO), and the like.
The invention also provides a preparation method of the ferroelectric thin film transistor, which comprises the following steps:
providing a substrate 1; the substrate 1 can be made of glass, plastic, sapphire, quartz, PET, PI or the like;
forming a gate 2 on a substrate 1; the grid 2 can be made of one or more of chromium, aluminum, gold and alloy thereof, is prepared on the substrate 1 by a thermal evaporation method, and then is subjected to vacuum drying treatment;
forming a first insulating layer 3 on the gate electrode 2; material of the first insulating layer 3Can be a metal oxide including, but not limited to, alumina (Al)2O3) Magnesium oxide (MgO), hafnium oxide (HfO)2) Yttrium oxide (Y)2O3) Zirconium oxide (ZrO)2) One or more of tantalum oxide, titanium oxide and zinc oxide, and also one or more of silicon oxide, silicon nitride and silicon oxynitride, and when the material of the first insulating layer 3 is an oxide of the material of the gate 2, the first insulating layer can be prepared by oxidizing the gate 2, and when the first insulating layer 3 is another material, the first insulating layer can be formed by chemical vapor deposition or physical vapor deposition;
forming a dielectric layer made of a ferroelectric material on the first insulating layer 3; ferroelectric materials include, but are not limited to, BiFeO3、BaTiO3、CaTiO3、PbTiO3One or more of lead zirconate titanate piezoelectric ceramics are formed on the first insulating layer 3 by chemical vapor deposition;
forming a second insulating layer 5 on the dielectric layer; the material of the second insulating layer 5 may be a metal oxide including, but not limited to, aluminum oxide (Al)2O3) Magnesium oxide (MgO), hafnium oxide (HfO)2) Yttrium oxide (Y)2O3) Zirconium oxide (ZrO)2) One or more of tantalum oxide, titanium oxide and zinc oxide, and also one or more of silicon oxide, silicon nitride and silicon oxynitride, and can be formed by chemical vapor deposition or physical vapor deposition;
forming a semiconductor layer 6 corresponding to the gate electrode 2 on the second insulating layer 5; the material of the semiconductor layer 6 may be an organic polymer material, a metal oxide or a silicon-based material, and is formed on the second insulating layer 5 by dip coating or spray coating or a printing method; and
forming a source electrode 8 and a drain electrode 9 on the semiconductor layer 6, and arranging the source electrode 8 and the drain electrode 9 at a certain distance to form a channel; the source electrode 8 and the drain electrode 9 may be made of Au, Ag, Cr, Al, conductive glass (ITO), or the like, and are formed on the upper surface of the semiconductor layer 6 by a thermal evaporation method or a coating method. The ferroelectric thin film transistor is a horizontal channel thin film transistor.
Example 1
(1) Preparing a grid: preparing an aluminum (Al) metal grid with the thickness of 0.15 mu m on a glass substrate by a thermal evaporation method, and carrying out vacuum drying treatment;
(2) preparing a first insulating layer: controlling oxygen amount and temperature rise speed in the vacuum heating cavity to form compact Al on the surface of the aluminum gate2O3An insulating layer with a thickness of 10nm, drying;
(3) preparation of a ferroelectric layer: selecting a ferroelectric material BiFeO3Preparing a dielectric layer with the thickness of 100nm by adopting a Metal Oxide Chemical Vapor Deposition (MOCVD) method as a dielectric layer material, and drying;
(4) preparing a second insulating layer: in BiFeO3Preparation of Al with a thickness of-10 nm on a ferroelectric layer by thermal evaporation2O3Drying the second insulating layer;
(5) preparing a semiconductor layer: ZnO is selected as an N-type semiconductor layer channel material, a semiconductor layer with the thickness of 10nm is prepared by a thermal evaporation method, and drying treatment is carried out;
(6) preparing an electrode: the source electrode and the drain electrode are prepared by a patterned metal masking plate through evaporation, metal silver (Ag) is selected, the thickness of the metal silver (Ag) is 0.15 mu m, the channel length (the distance between the two electrodes) is 5 mu m, and the channel width is 300 mu m.
The grid electrode, the source electrode and the drain electrode are respectively connected with a control power supply, a device circuit and the like, and finally the thin film transistor TFT-S1 which can be used for controlling an electronic device is obtained.
Example 2
(1) Preparing a grid: preparing an aluminum (Al) metal grid with the thickness of 0.15 mu m on a glass substrate by a thermal evaporation method, and carrying out vacuum drying treatment;
(2) preparing a first insulating layer: controlling oxygen amount and temperature rise speed in the vacuum heating cavity to form compact Al on the surface of the aluminum gate2O3An insulating layer with a thickness of 20nm, and drying;
(3) preparation of a ferroelectric layer: selecting a ferroelectric material BiFeO3As a dielectric layer material, preparing a dielectric layer with the thickness of 200nm by adopting a metal oxide chemical vapor deposition method, and drying;
(4) preparing a second insulating layer: in BiFeO3Preparing Al with thickness of 20nm on the ferroelectric layer by thermal evaporation method2O3Drying the second insulating layer;
(5) preparing a semiconductor layer: ZnO is selected as an N-type semiconductor layer channel material, a semiconductor layer with the thickness of 10nm is prepared by a thermal evaporation method, and drying treatment is carried out;
(6) preparing an electrode: the source electrode and the drain electrode are prepared by a patterned metal masking plate through evaporation, metal silver (Ag) is selected, the thickness of the metal silver (Ag) is 0.15 mu m, the channel length (the distance between the two electrodes) is 5 mu m, and the channel width is 300 mu m.
The grid electrode, the source electrode and the drain electrode are respectively connected with a control power supply, a device and the like, and finally the thin film transistor TFT-S2 which can be used for controlling an electronic device is obtained.
Example 3
(1) Preparing a grid: preparing an aluminum (Al) metal grid with the thickness of 0.15 mu m on a glass substrate by a thermal evaporation method, and carrying out vacuum drying treatment;
(2) preparing a first insulating layer: controlling oxygen amount and temperature rise speed in the vacuum heating cavity to form compact Al on the surface of the aluminum gate2O3An insulating layer with a thickness of 15nm, and drying;
(3) preparation of a ferroelectric layer: selecting a ferroelectric material BiFeO3As a dielectric layer material, preparing a dielectric layer with the thickness of 150nm by adopting a metal oxide chemical vapor deposition method, and drying;
(4) preparing a second insulating layer: in BiFeO3Preparing Al with thickness of 15nm on the ferroelectric layer by thermal evaporation method2O3Drying the second insulating layer;
(5) preparing a semiconductor layer: ZnO is selected as an N-type semiconductor layer channel material, a semiconductor layer with the thickness of 10nm is prepared by a thermal evaporation method, and drying treatment is carried out;
(6) preparing an electrode: the source electrode and the drain electrode are prepared by a patterned metal masking plate through evaporation, metal silver (Ag) is selected, the thickness of the metal silver (Ag) is 0.15 mu m, the channel length (the distance between the two electrodes) is 5 mu m, and the channel width is 300 mu m.
The grid electrode, the source electrode and the drain electrode are respectively connected with a control power supply, a device and the like, and finally the thin film transistor TFT-S3 which can be used for controlling an electronic device is obtained.
The invention also provides another preparation method of the ferroelectric thin film transistor, which comprises the following steps:
providing a substrate 1; the substrate 1 can be made of glass, plastic, sapphire, quartz, PET, PI or the like;
forming a gate 2 on a substrate 1; the grid 2 can be made of one or more of chromium, aluminum, gold and alloy thereof, is prepared on the substrate 1 by a thermal evaporation method, and then is subjected to vacuum drying treatment;
forming a first insulating layer 3 on the gate electrode 2; the material of the first insulating layer 3 may be a metal oxide including, but not limited to, aluminum oxide (Al)2O3) Magnesium oxide (MgO), hafnium oxide (HfO)2) Yttrium oxide (Y)2O3) Zirconium oxide (ZrO)2) One or more of tantalum oxide, titanium oxide and zinc oxide, and also one or more of silicon oxide, silicon nitride and silicon oxynitride, and when the material of the first insulating layer 3 is an oxide of the material of the gate 2, the first insulating layer can be prepared by oxidizing the gate 2, and when the first insulating layer 3 is another material, the first insulating layer can be formed by chemical vapor deposition or physical vapor deposition;
forming a dielectric layer made of a ferroelectric material on the first insulating layer 3; ferroelectric materials include, but are not limited to, BiFeO3、BaTiO3、CaTiO3、PbTiO3One or more of lead zirconate titanate piezoelectric ceramics are formed on the first insulating layer 3 by chemical vapor deposition;
forming a second insulating layer 5 on the ferroelectric layer 4; the material of the second insulating layer 5 may be a metal oxide including, but not limited to, aluminum oxide (Al)2O3) Magnesium oxide (MgO), hafnium oxide (HfO)2) Yttrium oxide (Y)2O3) Zirconium oxide (ZrO)2) One or more of tantalum oxide, titanium oxide and zinc oxide, and also one or more of silicon oxide, silicon nitride and silicon oxynitride, and can be formed by chemical vapor deposition or physical vapor deposition;
forming a source conductive layer 7 on the second insulating layer 5, wherein the source conductive layer 7 may be a nano silver wire (Ag-NWs) conductive layer and may be prepared on the second insulating layer 5 by a spin coating method;
forming a semiconductor layer 6 corresponding to the gate electrode 2 on the source conductive layer 7; the material of the semiconductor layer 6 may be an organic polymer material, a metal oxide or a silicon-based material, and is formed on the source conductive layer 7 by dip coating or spray coating or printing; and
a drain electrode 9 is formed on the semiconductor layer 6 and a source electrode 8 is formed on the source conductive layer 7, and the channel is formed such that the source electrode 8 and the drain electrode 9 are spaced apart.
The ferroelectric thin film transistor is a vertical channel thin film transistor, and has the advantages of shorter transmission path, higher transmission speed, ultrahigh current density, ultrahigh switching characteristic and the like compared with the traditional horizontal channel thin film transistor.
The method for manufacturing the ferroelectric thin film transistor further includes a step of manufacturing the semiconductor layer 6, including:
forming a complete semiconductor layer 6 on the second insulating layer 5, and performing drying treatment; the completed semiconductor layer 6 is then processed to remove a portion of the semiconductor layer 6 to expose a portion of the silver nanowire layer as a source conductive layer 7 for deposition of a source electrode 8.
Example 4
(1) Preparing a grid: preparing an aluminum (Al) metal grid with the thickness of 0.15 mu m on a glass substrate by a thermal evaporation method, and carrying out vacuum drying treatment;
(2) preparing a first insulating layer: controlling oxygen amount and temperature rise speed in the vacuum heating cavity to form compact Al on the surface of the aluminum gate2O3An insulating layer with a thickness of 15nm, and drying;
(3) preparation of a ferroelectric layer: selecting a ferroelectric material BiFeO3Preparing a dielectric layer with the thickness of 150nm by adopting a metal oxide chemical vapor deposition method as a dielectric layer material, and drying;
(4) preparing a second insulating layer: in BiFeO3Preparing Al with thickness of 15nm on the ferroelectric layer by thermal evaporation method2O3Drying the second insulating layer;
(5) preparing a source electrode conducting layer: preparing a nano silver wire (Ag-NWs) conducting layer with the thickness of 20nm on the second insulating layer by a spin coating method, and drying;
(6) preparing a semiconductor layer: DNTT is selected as a semiconductor layer channel material, a semiconductor layer with the thickness of 30nm is prepared by a spin-coating method, and drying treatment is carried out; removing part of the DNTT semiconductor layer by an ion beam etching method to expose part of the source electrode conducting layer (namely the nano silver wire layer) for depositing a source electrode;
(7) preparing an electrode: the source electrode and the drain electrode are prepared by a patterned metal masking plate evaporation method, metal silver (Ag) is selected, the thickness of the metal silver (Ag) is 0.15 mu m, the channel length (the distance between the two electrodes) is 5 mu m, and the channel width is 300 mu m.
The grid electrode, the source electrode and the drain electrode are respectively connected with a control power supply, a device and the like, and finally the thin film transistor V-TFT-S4 which can be used for controlling an electronic device is obtained.
COMPARATIVE EXAMPLE 1 (horizontal channel, no insulating layer)
(1) Preparing a grid: preparing an aluminum (Al) metal grid with the thickness of 0.15 mu m on a glass substrate by a thermal evaporation method, and carrying out vacuum drying treatment;
(2) preparation of a ferroelectric layer: selecting a ferroelectric material BiFeO3Preparing a dielectric layer with the thickness of 150nm on the grid electrode by adopting a metal oxide chemical vapor deposition method as a dielectric layer material, and drying;
(3) preparing a semiconductor layer: ZnO is selected as an N-type semiconductor layer channel material, a semiconductor layer with the thickness of 10nm is prepared on the ferroelectric layer by a thermal evaporation method, and drying treatment is carried out;
(4) preparing an electrode: and evaporating a patterned metal masking plate on the semiconductor layer to prepare a source electrode and a drain electrode, wherein the source electrode and the drain electrode are made of metal silver (Ag), the thickness of the metal silver (Ag) is 0.15 mu m, the channel length (the distance between the two electrodes) is 5 mu m, and the channel width is 300 mu m.
The grid electrode, the source electrode and the drain electrode are respectively connected with a control power supply, a device and the like, and finally the thin film transistor TFT-D1 which can be used for controlling an electronic device is obtained.
COMPARATIVE EXAMPLE 2 (horizontal trench, Single layer insulation)
(1) Preparing a grid: preparing an aluminum (Al) metal grid with the thickness of 0.15 mu m on a glass substrate by a thermal evaporation method, and carrying out vacuum drying treatment;
(2) preparing a first insulating layer: controlling oxygen amount and temperature rise speed in the vacuum heating cavity to form compact Al on the surface of the aluminum gate2O3An insulating layer with a thickness of 15nm, and drying;
(3) preparation of a ferroelectric layer: selecting a ferroelectric material BiFeO3Preparing a dielectric layer with the thickness of 150nm on the first insulating layer by adopting a metal oxide chemical vapor deposition method as a dielectric layer material, and drying;
(4) preparing a semiconductor layer: ZnO is selected as an N-type semiconductor layer channel material, a thermal evaporation method is adopted to prepare a semiconductor layer with the thickness of 10nm on a ferroelectric layer, and drying treatment is carried out;
(5) preparing an electrode: and evaporating a patterned metal masking plate on the semiconductor layer to prepare a source electrode and a drain electrode, wherein the source electrode and the drain electrode are made of metal silver (Ag), the thickness of the metal silver (Ag) is 0.15 mu m, the channel length (the distance between the two electrodes) is 5 mu m, and the channel width is 300 mu m.
The grid electrode, the source electrode and the drain electrode are respectively connected with a control power supply, a device and the like, and finally the thin film transistor TFT-D2 which can be used for controlling an electronic device is obtained.
COMPARATIVE EXAMPLE 3 (horizontal trench, insulating layer too thin)
(1) Preparing a grid: preparing an aluminum (Al) metal grid with the thickness of 0.15 mu m on a glass substrate by a thermal evaporation method, and carrying out vacuum drying treatment;
(2) preparing a first insulating layer: controlling oxygen amount and temperature rise speed in the vacuum heating cavity to form compact Al on the surface of the aluminum gate2O3An insulating layer with a thickness of-3 nm, and drying;
(3) preparation of a ferroelectric layer: selecting a ferroelectric material BiFeO3Preparing a dielectric layer with the thickness of 150nm on the first insulating layer by adopting a metal oxide chemical vapor deposition method as a dielectric layer material, and drying;
(4) preparing a second insulating layer: in BiFeO3Preparing Al with thickness of 3nm on the ferroelectric layer by thermal evaporation method2O3Drying the second insulating layer;
(5) preparing a semiconductor layer: ZnO is selected as an N-type semiconductor layer channel material, a semiconductor layer with the thickness of 10nm is prepared on the second insulating layer by a thermal evaporation method, and drying treatment is carried out;
(6) preparing an electrode: and evaporating a patterned metal masking plate on the semiconductor layer to prepare a source electrode and a drain electrode, wherein the source electrode and the drain electrode are made of metal silver (Ag), the thickness of the metal silver (Ag) is 0.15 mu m, the channel length (the distance between the two electrodes) is 5 mu m, and the channel width is 300 mu m.
The grid electrode, the source electrode and the drain electrode are respectively connected with a control power supply, a device and the like, and finally the thin film transistor TFT-D3 which can be used for controlling an electronic device is obtained.
COMPARATIVE EXAMPLE 4 (horizontal Trench, insulating layer too thick)
(1) Preparing a grid electrode: preparing an aluminum (Al) metal grid with the thickness of 0.15 mu m on a glass substrate by a thermal evaporation method, and carrying out vacuum drying treatment;
(2) preparing a first insulating layer: controlling the oxygen amount and the temperature rise speed in the vacuum heating cavity to form compact Al on the surface of the aluminum grid2O3An insulating layer with a thickness of 50nm, and drying;
(3) preparation of a ferroelectric layer: selecting a ferroelectric material BiFeO3Preparing a dielectric layer with the thickness of 150nm on the first insulating layer by adopting a metal oxide chemical vapor deposition method as a dielectric layer material, and drying;
(4) preparing a second insulating layer: in BiFeO3Preparing Al with thickness of 50nm on the ferroelectric layer by thermal evaporation method2O3Drying the second insulating layer;
(5) preparing a semiconductor layer: ZnO is selected as an N-type semiconductor layer channel material, a semiconductor layer with the thickness of 10nm is prepared on the second insulating layer by a thermal evaporation method, and drying treatment is carried out;
(6) preparing an electrode: and evaporating a patterned metal masking plate on the semiconductor layer to prepare a source electrode and a drain electrode, wherein the source electrode and the drain electrode are made of metal silver (Ag), the thickness of the metal silver (Ag) is 0.15 mu m, the channel length (the distance between the two electrodes) is 5 mu m, and the channel width is 300 mu m.
The grid electrode, the source electrode and the drain electrode are respectively connected with a control power supply, a device and the like, and finally the thin film transistor TFT-D4 which can be used for controlling an electronic device is obtained.
COMPARATIVE EXAMPLE 5 vertical Trench, without isolation layer)
(1) Preparing a grid: preparing an aluminum (Al) metal grid with the thickness of 0.15 mu m on a glass substrate by a thermal evaporation method, and carrying out vacuum drying treatment;
(2) preparation of a ferroelectric layer: selecting a ferroelectric material BiFeO3Preparing a dielectric layer with the thickness of 150nm by adopting a metal oxide chemical vapor deposition method as a dielectric layer material, and drying;
(3) preparing a source electrode conducting layer: preparing a nano silver wire (Ag-NWs) conducting layer with the thickness of 20nm on the ferroelectric layer by a spin coating method, and drying;
(4) preparing a semiconductor layer: selecting DNTT as a semiconductor layer channel material, preparing a semiconductor layer with the thickness of 30nm on the source electrode conducting layer by adopting a spin coating method, and drying; removing part of the DNTT semiconductor layer by an ion beam etching method to expose part of the source electrode conducting layer (namely the nano silver layer) for depositing a source electrode;
(5) preparing an electrode: the source electrode and the drain electrode are prepared by a patterned metal masking plate evaporation method, metal silver (Ag) is selected, the thickness of the metal silver (Ag) is 0.15 mu m, the channel length (the distance between the two electrodes) is 5 mu m, and the channel width is 300 mu m.
The grid electrode, the source electrode and the drain electrode are respectively connected with a control power supply, a device and the like, and finally the thin film transistor V-TFT-D5 which can be used for controlling an electronic device is obtained.
COMPARATIVE EXAMPLE 6 vertical Trench, Single layer insulation layer)
(1) Preparing a grid: preparing an aluminum (Al) metal grid with the thickness of 0.15 mu m on a glass substrate by a thermal evaporation method, and carrying out vacuum drying treatment;
(2) preparing a first insulating layer: controlling oxygen amount and temperature rise speed in the vacuum heating cavity to form compact Al on the surface of the aluminum gate2O3An insulating layer with a thickness of 15nm, drying;
(3) preparation of a ferroelectric layer: selecting a ferroelectric material BiFeO3As dielectric layer materialPreparing a dielectric layer with the thickness of 150nm by adopting a metal oxide chemical vapor deposition method, and drying;
(4) preparing a source electrode conducting layer: preparing a nano silver wire (Ag-NWs) conducting layer with the thickness of 20nm on the ferroelectric layer by a spin coating method, and drying;
(5) preparing a semiconductor layer: DNTT is selected as a semiconductor layer channel material, a semiconductor layer with the thickness of 30nm is prepared by a spin-coating method, and drying treatment is carried out; removing part of the DNTT semiconductor layer by an ion beam etching method to expose part of the source electrode conducting layer (namely the nano silver wire layer) for depositing a source electrode;
(6) preparing an electrode: the source electrode and the drain electrode are prepared by a patterned metal masking plate evaporation method, metal silver (Ag) is selected, the thickness of the metal silver (Ag) is 0.15 mu m, the channel length (the distance between the two electrodes) is 5 mu m, and the channel width is 300 mu m.
The grid electrode, the source electrode and the drain electrode are respectively connected with a control power supply, a device and the like, and finally the thin film transistor V-TFT-D6 which can be used for controlling an electronic device is obtained.
The thin film transistor devices in the above examples and comparative examples were selected for electrical performance testing, and the final test results are shown in the following table:
as can be seen from the above table and fig. 5, the drain currents (I) of the horizontal channel ferroelectric thin film transistors (examples 1 to 3) and the vertical channel ferroelectric thin film transistors (example 4) obtained by the manufacturing method of the present invention are higher than those of the horizontal channel thin film transistors (comparative examples 1 to 4) and the vertical channel thin film transistors (comparative examples 5 and 6) in the comparative examplesD@VG3V) is higher, the average electron mobility is higher. Therefore, the first insulating layer and the second insulating layer in the ferroelectric thin film transistor can greatly reduce the free electrons in the semiconductor layer from migrating to the ferroelectric layer or the free electrons in the ferroelectric layer from migrating to the semiconductor layer, thereby generating a leakage current phenomenon, and further reducing the channel carrier concentration and the drain current density of the semiconductor layerAnd (4) degree. As seen from example 3 (having both the first insulating layer and the second insulating layer) and comparative examples 1 (having no insulating layer) and 2 (having a single insulating layer), the ferroelectric dielectric layer having both the first insulating layer and the second insulating layer is more significant in reducing the interface leakage phenomenon, and, secondly, having a single insulating layer, having no insulating layer, has a larger leakage current phenomenon. Therefore, the introduction of the first insulating layer and the second insulating layer improves the carrier transmission characteristic of the device and improves the leakage current phenomenon in the working process of the ferroelectric thin film transistor.
Next, in comparison between example 3 and comparative examples 3 and 4 (shown in fig. 1), the thickness of the ultra-thin insulating layer should be one tenth of the thickness of the ferroelectric dielectric layer, and the effects of dielectric insulation and reduction of leakage current are best. The insulating layer is too thin to play a role in preventing free electrons in the semiconductor layer from migrating to the dielectric layer, and because the quantum tunneling phenomenon of electrons is generated at the moment, the electrons can cross the potential barrier and reach the other side of the insulating layer; the insulating layer is too thick, the polarization electric field in the ferroelectric layer is weakened by the too thick insulating layer, and the function of regulating and controlling the carrier concentration and the drift in the semiconductor layer is not achieved, so that the advantage of the ferroelectric material as a dielectric layer in the field effect tube is lost.
By comparing example 4 with other examples, the vertical channel ferroelectric thin film transistor of the present invention has the highest ID，μeThe ferroelectric thin film transistor with the vertical channel structure has more excellent electrical properties, and the main reasons of the ferroelectric thin film transistor with the vertical channel structure are that the transmission path of a vertical channel carrier is shorter, the mobility is higher, and therefore the ferroelectric thin film transistor with the vertical channel structure has higher current density and faster switching characteristics.
The above embodiments are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited thereby, and any insubstantial changes and substitutions made by those skilled in the art based on the present invention are within the protection scope of the present invention.
Claims (8)
1. A ferroelectric thin film transistor, comprising:
a substrate;
the grid is arranged on the substrate;
the first insulating layer is arranged on the grid electrode;
the dielectric layer is made of ferroelectric materials and arranged on the first insulating layer;
a second insulating layer disposed on the dielectric layer;
a semiconductor layer disposed on the second insulating layer; and (c) a second step of,
the source electrode and the drain electrode are arranged at intervals, are electrically connected with the semiconductor layer and are used for forming a transmission channel in the semiconductor layer;
the ferroelectric thin film transistor further includes a source conductive layer disposed between the second insulating layer and the semiconductor layer, the drain electrode disposed on the semiconductor layer and the source electrode disposed on the source conductive layer.
2. A ferroelectric thin film transistor as in claim 1, wherein: the thicknesses of the first insulating layer and the second insulating layer are both smaller than the thickness of the dielectric layer.
3. A ferroelectric thin film transistor as in claim 1, wherein: the first insulating layer and the second insulating layer are made of metal oxide.
4. A ferroelectric thin film transistor as in claim 3, wherein: the metal oxide is Al2O3、MgO、HfO2、Y2O3、ZrO2One or more of (a).
5. A ferroelectric thin film transistor as in claim 1, wherein: the first insulating layer and the second insulating layer are one or more of silicon oxide, silicon nitride and silicon oxynitride.
6. A ferroelectric thin film transistor as in claim 1, wherein: the ferroelectric material used for manufacturing the dielectric layer is BiFeO3、BaTiO3、CaTiO3、PbTiO3And lead zirconate titanate piezoelectric ceramics; the substrate is a rigid substrate made of glass or plastic or sapphire or quartz; or the substrate is a flexible substrate made of PET or PI; the grid is made of one or more of chromium, aluminum, gold and alloy thereof; the semiconductor layer is made of organic polymer materials, metal oxides or silicon-based materials.
7. A method of manufacturing a ferroelectric thin film transistor as in claim 1, comprising:
arranging a substrate;
forming a gate on the substrate;
forming a first insulating layer on the gate electrode;
forming a dielectric layer made of a ferroelectric material on the first insulating layer;
forming a second insulating layer on the dielectric layer;
forming a source electrode conductive layer on the second insulating layer;
forming a semiconductor layer corresponding to the gate electrode on the source conductive layer;
and forming a drain electrode on the semiconductor layer and a source electrode on the source electrode conducting layer, and enabling the source electrode and the drain electrode to be separated by a certain distance to form a channel.
8. A method of manufacturing a ferroelectric thin film transistor as in claim 7, characterized in that: and setting the thickness of the first insulating layer and the second insulating layer to be smaller than that of the ferroelectric dielectric layer.
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| US6011285A (en) * | 1998-01-02 | 2000-01-04 | Sharp Laboratories Of America, Inc. | C-axis oriented thin film ferroelectric transistor memory cell and method of making the same |
| CN103474355A (en) * | 2013-09-16 | 2013-12-25 | 上海大学 | Manufacturing method of thin film transistor |
| CN104576758A (en) * | 2015-01-22 | 2015-04-29 | 合肥京东方光电科技有限公司 | Thin film transistor, array substrate, manufacturing method for thin film transistor and manufacturing method for array substrate |
| CN107170812A (en) * | 2017-06-08 | 2017-09-15 | 湘潭大学 | A kind of ferroelectrical thin film transistor and preparation method thereof |
| CN109801977A (en) * | 2019-01-28 | 2019-05-24 | 中国科学院微电子研究所 | Memory |
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| US7602007B2 (en) * | 1997-04-28 | 2009-10-13 | Yoshihiro Kumazaki | Semiconductor device having controllable transistor threshold voltage |
| US6642131B2 (en) * | 2001-06-21 | 2003-11-04 | Matsushita Electric Industrial Co., Ltd. | Method of forming a silicon-containing metal-oxide gate dielectric by depositing a high dielectric constant film on a silicon substrate and diffusing silicon from the substrate into the high dielectric constant film |
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| US6011285A (en) * | 1998-01-02 | 2000-01-04 | Sharp Laboratories Of America, Inc. | C-axis oriented thin film ferroelectric transistor memory cell and method of making the same |
| CN103474355A (en) * | 2013-09-16 | 2013-12-25 | 上海大学 | Manufacturing method of thin film transistor |
| CN104576758A (en) * | 2015-01-22 | 2015-04-29 | 合肥京东方光电科技有限公司 | Thin film transistor, array substrate, manufacturing method for thin film transistor and manufacturing method for array substrate |
| CN107170812A (en) * | 2017-06-08 | 2017-09-15 | 湘潭大学 | A kind of ferroelectrical thin film transistor and preparation method thereof |
| CN109801977A (en) * | 2019-01-28 | 2019-05-24 | 中国科学院微电子研究所 | Memory |
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