KR102162755B1 - Thin Film Transistor Substrate For High Resolution Liquid Crystal Display Having High Apperture Ratio and Manufacturing Method Thereof - Google Patents

Abstract

The present invention relates to a thin film transistor substrate for a high resolution liquid crystal display device having high transmittance and a method of manufacturing the same. A thin film transistor substrate according to the present invention includes n-th and (n+1)-th data lines running vertically on the substrate and disposed adjacent to each other; Gate wirings running in a horizontal direction on the substrate; An n-th thin film transistor and a (n+1)-th thin film transistor formed adjacent to each other at a portion where the two adjacent data lines and the gate line cross each other; A planarization layer including a pattern hole covering the entire substrate and simultaneously exposing the nth thin film transistor and the (n+1)th thin film transistor; An n-th pixel electrode connected to the n-th thin film transistor through the pattern hole; And a (n+1)-th pixel electrode connected to the (n+1)-th thin film transistor through the pattern hole.

Description

Thin Film Transistor Substrate For High Resolution Liquid Crystal Display Having High Apperture Ratio and Manufacturing Method Thereof}

The present invention relates to a thin film transistor (TFT) substrate for a high-resolution liquid crystal display (LCD) having high transmittance and a method of manufacturing the same. In particular, the present invention provides a thin film transistor substrate for a high-resolution liquid crystal display device having a high transmittance and a method for manufacturing the same, which solves the problem of lowering the transmittance that occurs when the size of a pixel decreases when implementing a high resolution in a portable liquid crystal display About.

The display device field has rapidly changed to a flat panel display device (FPD) that is thin, light, and capable of large area, replacing a bulky cathode ray tube (CRT). Flat panel displays include Liquid Crystal Display Device (LCD), Plasma Display Panel (PDP), Organic Light Emitting Display Device (OLED), and Electrophoretic Display Device. : ED).

In the case of an active liquid crystal display device, an organic light emitting display device, and an electrophoretic display device, a thin film transistor substrate including a thin film transistor allocated in a pixel region arranged in a matrix manner is disposed. A liquid crystal display device (LCD) displays an image by adjusting the light transmittance of a liquid crystal using an electric field. Such a liquid crystal display device is classified into a vertical electric field type and a horizontal electric field type according to the direction of an electric field driving the liquid crystal.

The vertical electric field type liquid crystal display drives a TN (Twisted Nematic) mode liquid crystal by a vertical electric field formed between a pixel electrode and a common electrode disposed opposite to the upper and lower substrates. Such a vertical electric field type liquid crystal display device has an advantage of having a large aperture ratio, but has a disadvantage of having a viewing angle of about 90 degrees.

In the horizontal electric field type liquid crystal display, a horizontal electric field is formed between a pixel electrode and a common electrode arranged parallel to a lower substrate to drive a liquid crystal in an in-plane switching (IPS) mode. The IPS mode liquid crystal display has an advantage of having a wide viewing angle of about 160 degrees, but has a low aperture ratio and transmittance. Specifically, in the IPS mode liquid crystal display, in order to form an in-plane field, the gap between the common electrode and the pixel electrode is made wider than the gap between the upper substrate and the lower substrate (cell gap: cell gap). In order to obtain the electric field of, the common electrode and the pixel electrode are formed in a strip shape having a certain width. An electric field that is substantially parallel to the substrate is formed between the pixel electrode and the common electrode of the IPS mode, but the electric field is not formed in the liquid crystal over the pixel electrode and the common electrodes having a predetermined width. That is, liquid crystal molecules placed on the pixel electrode and the common electrode are not driven and maintain the initial arrangement state. The liquid crystal that maintains the initial state cannot transmit light, which causes a decrease in the aperture ratio and transmittance.

In order to improve the shortcomings of the IPS mode liquid crystal display, a fringe field switching (FFS) liquid crystal display device operated by a fringe field has been proposed. The FFS type liquid crystal display device includes a common electrode and a pixel electrode in each pixel area with an insulating film interposed therebetween, and the common electrode and the pixel electrode overlap each other in the vertical direction or, even if they do not overlap, the separation distance in the horizontal direction is higher. It is formed to be narrower than the distance between the substrate and the lower substrate to form a parabolic fringe field over the common electrode and the pixel electrode. All of the liquid crystal molecules interposed between the upper and lower substrates by the fringe field operate, thereby improving the aperture ratio and transmittance.

In the fringe field type liquid crystal display device, since the common electrode and the pixel electrode are overlapped or disposed at considerably close positions, an auxiliary capacitor is formed between the common electrode and the pixel electrode. Therefore, unlike the IPS mode, there is an advantage in that there is no need to form an auxiliary capacity. However, when the large-screen display device is implemented in a fringe field method, the size of the pixel increases and the size of the auxiliary capacitor increases, and thus, there is a problem in that the thin film transistor needs to be enlarged to drive it.

In order to solve this problem, a thin film transistor substrate having a metal oxide semiconductor layer having a high capacity driving characteristic without increasing the size of the thin film transistor has been applied. 1 is a plan view illustrating a thin film transistor substrate having an oxide semiconductor layer included in a conventional fringe field type liquid crystal display device. FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along line I-I'.

The thin film transistor substrate having a metal oxide semiconductor layer shown in FIGS. 1 and 2 is a gate wiring GL and a data wiring DL intersecting a lower substrate SUB with a gate insulating layer GI therebetween, and a cross structure thereof. A thin film transistor T formed in each pixel region defined by is provided.

The thin film transistor T includes a gate electrode G branched from the gate line GL, a source electrode S branched from the data line DL, a drain electrode D facing the source electrode S, and a gate. It includes a semiconductor layer (A) forming a channel between the source electrode (S) and the drain electrode (D) when overlapping the gate electrode (G) on the insulating layer (GI).

In particular, when the semiconductor layer (A) is formed of an oxide semiconductor material, it is advantageous for a large-area thin film transistor substrate having a large charging capacity due to its high charge mobility characteristics. However, it is preferable that the oxide semiconductor material further includes an etch stopper (ES) for protection from an etchant on the upper surface in order to secure the stability of the device. Specifically, it is preferable to form the etch stopper ES to protect the semiconductor layer A from the etchant introduced through the separated portion between the source electrode S and the drain electrode D.

One end of the gate line GL includes a gate pad GP for receiving a gate signal from the outside. The gate pad GP contacts the gate pad intermediate terminal IGT through the first gate pad contact hole GH1 penetrating the gate insulating layer GI. The gate pad intermediate terminal IGT contacts the gate pad terminal GPT through the second gate pad contact hole GH2 penetrating the first passivation layer PA1 and the second passivation layer PA2. Meanwhile, at one end of the data line DL, a data pad DP for receiving pixel signals from the outside is included. The data pad DP contacts the data pad terminal DPT through the data pad contact hole DPH penetrating the first passivation layer PA1 and the second passivation layer PA2.

In the pixel area, a pixel electrode PXL and a common electrode COM formed with the second passivation layer PA2 interposed therebetween are provided to form a fringe field. The common electrode COM is connected to the common wiring CL arranged in parallel with the gate wiring GL. The common electrode COM receives a reference voltage (or a common voltage) for driving the liquid crystal through the common line CL.

The positions and shapes of the common electrode COM and the pixel electrode PXL may be variously formed according to a design environment and purpose. A constant reference voltage is applied to the common electrode COM, while a voltage value that changes at any time according to the video data to be implemented is applied to the pixel electrode PXL. Accordingly, parasitic capacitance may be generated between the data line DL and the pixel electrode PXL. Since such parasitic capacitance may cause a problem in image quality, it is preferable to cover the data line DL and the thin film transistor T with a planarization film PAC formed of a thick organic material having a low dielectric constant.

That is, after forming a planarization layer PAC in which an organic material having a low dielectric constant is thickly formed on the first passivation layer PA1 covering the data line DL and the thin film transistor T, the common electrode COM is formed. In addition, after forming the second passivation layer PA2 covering the common electrode COM, a pixel electrode PXL overlapping the common electrode COM is formed on the second passivation layer PA2. In this structure, since the pixel electrode PXL is separated by the data line DL, the first passivation layer PA1, the planarization layer PAC, and the second passivation layer PA2, the data line DL and the pixel electrode PXL are separated. In between, the parasitic capacity can be reduced.

The common electrode COM is formed in a rectangular shape corresponding to the shape of the pixel region, and the pixel electrode PXL is formed in the shape of a plurality of line segments. In particular, the pixel electrode PXL has a structure vertically overlapping the common electrode COM with the second passivation layer PA2 interposed therebetween. A fringe field is formed between the pixel electrode PXL and the common electrode COM, so that liquid crystal molecules arranged in a horizontal direction between the thin film transistor substrate and the color filter substrate rotate due to dielectric anisotropy. In addition, the light transmittance through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby implementing grayscale.

When such a thin film transistor substrate is applied to a high-resolution portable liquid crystal display, since the size of the pixel is reduced, it is necessary to secure a sufficient amount of light in a single pixel. However, in the thin film transistor substrate such as the structure shown in FIGS. 1 and 2, the drain electrode D contacts the pixel electrode PXL through the drain contact hole DH. That is, the drain electrode D has a structure extending toward the region of the pixel electrode PXL.

A sufficient space must be secured so that the drain electrode D extends toward the pixel electrode PXL to form the drain contact hole DH. Due to the space for forming the drain contact hole DH, the area of the pixel electrode PXL that determines the opening area is reduced. In the case of low resolution, the area ratio occupied by the drain contact hole DH is not a big problem. However, in an ultra-high resolution display device of 300 ppi (pixel per inch) or more, since the size of a single pixel is remarkably reduced, the size of the drain contact hole DH also has a great influence on reducing the aperture ratio.

Accordingly, there is a need for a thin film transistor substrate having a structure capable of securing a high aperture ratio in a liquid crystal display device for realizing ultra-high resolution in a portable display device having a relatively small screen size.

An object of the present invention is to overcome the above problems, and to provide a thin film transistor substrate for a liquid crystal display and a method of manufacturing the same for realizing ultra-high resolution in a portable display device having a relatively small screen size. Another object of the present invention is to provide a thin film transistor substrate for an ultra-high resolution liquid crystal display device having high transmittance for securing a high aperture ratio, and a method for manufacturing the same at a simple and low cost.

In order to achieve the object of the present invention, a thin film transistor substrate according to the present invention includes n-th and (n+1)-th data lines running vertically on the substrate and disposed adjacent to each other; Gate wirings running in a horizontal direction on the substrate; An n-th thin film transistor and a (n+1)-th thin film transistor formed adjacent to each other at a portion where the two adjacent data lines and the gate line cross each other; A planarization layer including a pattern hole covering the entire substrate and simultaneously exposing the nth thin film transistor and the (n+1)th thin film transistor; An n-th pixel electrode connected to the n-th thin film transistor through the pattern hole; And a (n+1)-th pixel electrode connected to the (n+1)-th thin film transistor through the pattern hole.

A passivation layer covering the n-th pixel electrode and the (n+1)-th pixel electrode; And it characterized in that it further comprises a common electrode having a plurality of line segments overlapping the pixel electrode on the passivation layer.

A spacing distance between the pattern holes simultaneously exposing the n-th and (n+1)-th thin film transistors along the gate wiring is characterized by having a sufficient gap for disposing a spacer.

Each of the thin film transistors may include a gate electrode branched from the gate line; A semiconductor layer overlapping the gate electrode; A source electrode branching from the data line and contacting one side of the semiconductor layer; And a drain electrode spaced apart from the source electrode by a predetermined distance and in contact with the other side of the semiconductor layer.

The n-th thin film transistor is branched from the gate line and includes an n-th gate electrode formed at a portion where the two neighboring data lines and the gate line intersect, and the (n+1)-th thin film transistor is And a (n+1)-th gate electrode branched from the gate line and formed at a portion where the two adjacent data lines and the gate line cross each other.

The n-th gate electrode and the (n+1)-th gate electrode are formed as one body.

In addition, a method of manufacturing a thin film transistor substrate according to the present invention includes: a first mask process of forming a gate wiring in a horizontal direction by applying and patterning a gate metal material on the substrate; A gate insulating material, a semiconductor material, and a source metal material are continuously applied and patterned on the gate wiring to form n-th and (n+1)-th data lines to intersect the semiconductor layer and the gate wiring and to be disposed adjacent to each other. A second mask process; A third mask process of forming a pattern hole exposing a region where the n-th and (n+1)-th data lines and the gate lines intersect by applying and patterning a planarization layer on the data lines; And by coating and patterning a transparent conductive material on the entire substrate on which the pattern hole is formed, a source electrode branching from the data line, a drain electrode spaced apart from the source electrode by a predetermined distance, and extending in contact with the upper layer surface of the drain electrode And a fourth mask process of forming the formed pixel electrode.

Applying a protective film on the substrate on which the pixel electrode is formed; And a fifth mask process of forming a common electrode having a plurality of line segments overlapping the pixel electrode by applying and patterning a transparent conductive material on the passivation layer.

In the first mask process, forming a gate electrode branched from the gate wiring to a position overlapping with the n-th and (n+1)-th data lines; In the second mask process, an n-th source-drain element overlapping the gate electrode and branching from the n-th data line, and (n+1) overlapping the gate electrode and branching from the (n+1)-th data line 1) forming a second source-drain element; In the fourth mask process, the source-drain element is patterned with the transparent conductive material to form the source electrode, the drain electrode, and the pixel electrode, and a channel exposed between the source electrode and the drain electrode. It is characterized by defining an area.

The thin film transistor substrate for a high resolution liquid crystal display device having a high transmittance according to the present invention has a structure in which two thin film transistors adjacent in a horizontal direction are disposed in close proximity. Then, a pattern hole is formed to open the adjacent thin film transistor, and the drain electrode and the pixel electrode are connected through the pattern hole. Accordingly, the size of the pixel electrode occupying the pixel area can be maximized, and a high aperture ratio can be secured even in an ultra-high resolution pixel structure. In addition, by disposing two adjacent thin film transistors in one pattern hole, a spacer may be disposed between the pattern holes, thereby maintaining a uniform cell spacing.

1 is a plan view showing a thin film transistor substrate included in a conventional fringe field type liquid crystal display.
FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along line I-I'.
3 is a plan view showing a thin film transistor substrate for a high resolution liquid crystal display device having high transmittance according to a first embodiment of the present invention.
4 is a cross-sectional view of the thin film transistor substrate shown in FIG. 3 taken along line II-II'.
5 is a plan view showing a thin film transistor substrate for a high-resolution liquid crystal display device having high transmittance according to a second embodiment of the present invention.
6 is a cross-sectional view of the thin film transistor substrate shown in FIG. 5 taken along line III-III'.
7A to 7F are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a second exemplary embodiment of the present invention, cut by a cut line III-III' in FIG. 5.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals throughout the specification mean substantially the same constituent elements. In the following description, when it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

3 is a plan view showing a thin film transistor substrate for a high resolution liquid crystal display device having high transmittance according to a first embodiment of the present invention. FIG. 4 is a cross-sectional view of the thin film transistor substrate shown in FIG. 3 taken along line II-II'.

3 and 4, the thin film transistor substrate according to the first embodiment of the present invention includes a gate wiring GL and a data wiring DL intersecting a lower substrate SUB with a gate insulating layer GI interposed therebetween. , The thin film transistor T formed in each pixel region defined by the cross structure, the pixel electrode PXL connected to the thin film transistor T, and the pixel electrode PXL with the second passivation layer PA2 interposed therebetween. The common electrode COM is provided.

The thin film transistor T includes a gate electrode G branched from the gate line GL, a source electrode S branched from the data line DL, a drain electrode D facing the source electrode S, and a gate. It includes a semiconductor layer A forming a channel between the source electrode S and the drain electrode D while overlapping the gate electrode G on the insulating layer GI.

In the pixel area, a pixel electrode PXL and a common electrode COM formed with the second passivation layer PA2 interposed therebetween are provided to form a fringe field. The common electrode COM is connected to the common wiring CL arranged in parallel with the gate wiring GL. The common electrode COM receives a reference voltage (or a common voltage) for driving the liquid crystal through the common line CL.

The positions and shapes of the common electrode COM and the pixel electrode PXL may be variously formed according to a design environment and purpose. In the present invention, a manufacturing process method is applied for convenience in the manufacturing process and for efficiently protecting the channel area in the process of defining and forming the channel area. Accordingly, it has a structure in which the pixel electrode PXL is first formed and the common electrode COM is formed thereon. The manufacturing process will be described in Example 2, which is the most preferred embodiment of the present invention.

A constant reference voltage is applied to the common electrode COM, while a voltage value that changes at any time according to the video data to be implemented is applied to the pixel electrode PXL. Accordingly, parasitic capacitance may be generated between the data line DL and the pixel electrode PXL. Since such parasitic capacitance may cause a problem in image quality, it is preferable to cover the data line DL and the thin film transistor T with a planarization film PAC formed of a thick organic material having a low dielectric constant.

That is, after forming the planarization layer PAC in which an organic material having a low dielectric constant is thickly formed on the first passivation layer PA1 covering the data line DL and the thin film transistor T, the pixel electrode PXL is formed. In addition, after forming the second passivation layer PA2 covering the pixel electrode PXL, a common electrode COM overlapping the pixel electrode PXL is formed on the second passivation layer PA2. In this structure, since the pixel electrode PXL is separated from the data line DL by the first passivation film PA1 and the planarization film PAC, a parasitic capacitance is formed between the data line DL and the pixel electrode PXL. It can be minimized enough.

It is preferable that the pixel electrode PXL has a rectangular shape having a maximum size within a pixel area defined while surrounding the gate line GL and the data line DL. The common electrode COM is preferably formed as one body covering most of the substrate SUB on which the pixel array is disposed on the second passivation layer PA2. In particular, it is preferable that the common electrode COM is provided with a slit COMSL within the pixel region so that a plurality of parallel line segment shapes overlap the pixel electrode PXL.

That is, the pixel electrode PXL has a structure vertically overlapping the common electrode COM with the second passivation layer PA2 therebetween. A fringe field is formed between the pixel electrode PXL and the common electrode COM, so that liquid crystal molecules arranged in a horizontal direction between the thin film transistor substrate and the color filter substrate rotate due to dielectric anisotropy. In addition, the light transmittance through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby implementing grayscale.

The main object of the present invention is to secure a high aperture ratio in a small liquid crystal display panel having an ultra-high resolution. In particular, the main feature is to increase the aperture ratio by minimizing the size of the contact hole connecting the drain electrode D and the pixel electrode PXL.

To this end, in the first embodiment of the present invention, a pattern hole PH for opening the thin film transistor T among the first passivation layer PA1 and the planarization layer PAC is provided. The drain electrode D and the pixel electrode PXL are connected through the pattern hole PH. Accordingly, the drain electrode D does not need to extend to the pixel region, and can be formed only with a minimum size. That is, the thin film transistor T is formed with the minimum size, and the pixel electrode PXL is formed to overlap the drain electrode D of the thin film transistor T. As a result, the size of the pixel electrode PXL can be formed to the maximum size within the pixel area.

In the first embodiment of the present invention, the pixel electrode PXL is a method to have the maximum area ratio within the pixel area, and the pixel electrode PXL is formed through the pattern hole PH that opens the entire thin film transistor T. And a drain electrode (D). That is, it has a pattern hole PH corresponding to the size of the single thin film transistor T.

In general, in the case of a liquid crystal display panel, a thin film transistor substrate TFTS and a color filter substrate CFS are bonded, and a spacer CS for maintaining the bonding gap is disposed. Typically, the spacer CS includes a column spacer and a ball spacer. Here, for convenience, it will be described as a column spacer CS.

In addition, it is important to arrange the spacers CS so that they do not overlap with the pixel electrodes PXL occupying the opening area. For example, it may be disposed to overlap the gate line GL or the data line DL. However, most preferably, it is preferably formed on the thin film transistor T. The size of the spacer CS has a width of approximately 8 to 16 μm. In particular, in the case of the column spacer, the upper side has a width of 14 to 16 μm, and the lower side has an inverse tapered shape having a width of 8 to 9 μm. Meanwhile, the size of the thin film transistor T also has a square shape of about 10x10㎛ to 15x15㎛.

In the thin film transistor substrate according to the first exemplary embodiment of the present invention, when the spacer CS is disposed to overlap the thin film transistor T, some spacers CS are formed in the thin film transistor T region. Can be inserted in. As a result, there may be a case where the bonding distance between the thin film transistor substrate and the color filter substrate is not kept constant.

In order to avoid such a problem situation, it may be considered to arrange the spacers CS so as to overlap the gate wiring GL between the thin film transistors T. However, in the pixel array implementing the ultra-high resolution, the size of the unit pixel is reduced, so that the gap between the thin film transistor T and the thin film transistor T may have a gap of 8 μm or less. In this case, it is difficult to uniformly and accurately design the arrangement of the spacers CS. That is, some spacers CS overlap with the thin film transistor T, and the spacers CS may not maintain a constant height.

Hereinafter, with reference to FIGS. 5 and 6, in the second exemplary embodiment, a thin film transistor substrate capable of maintaining a constant bonding distance of a liquid crystal display panel that may occur in the first exemplary embodiment will be described. 5 is a plan view illustrating a thin film transistor substrate for a high resolution liquid crystal display device having high transmittance according to a second exemplary embodiment of the present invention. 6 is a cross-sectional view of the thin film transistor substrate shown in FIG. 5 taken along line III-III'.

The thin film transistor substrate according to the second embodiment of the present invention is defined by a gate wiring GL and a data wiring DL intersecting a lower substrate SUB with a gate insulating layer GI interposed therebetween, and the cross structure thereof. A thin film transistor (T) formed in each pixel area, a pixel electrode (PXL) connected to the thin film transistor (T), and a common electrode (COM) overlapping the pixel electrode (PXL) with a second passivation layer (PA2) therebetween is provided. do.

In particular, in the second embodiment, the two data lines DL are arranged close to each other. That is, the odd-numbered data line and the even-numbered data line may be disposed in close proximity to each other, so that the even-numbered pixel column and the odd-numbered pixel column are disposed adjacent to each other. For example, the first data line DL1 and the second data line DL2 may be arranged so that they are close to each other, and the third data line DL3 and the fourth data line DL4 are close to each other.

In this case, a first thin film transistor T1 connected to the first data line DL1 and allocated to the first pixel column, and a second thin film transistor T2 connected to the second data line DL2 and allocated to the second pixel column. Have structures that are oriented to each other (positioned back to back). In addition, the third thin film transistor T3 connected to the third data line DL3 and allocated to the third pixel column and the fourth thin film transistor T4 connected to the fourth data line DL4 and allocated to the fourth pixel column are It has a structure that is oriented (positioned back to back) to each other. As a result, the second pixel area P2 disposed in the second pixel column and the third pixel area P3 disposed in the third pixel column may have adjacent structures without a data line DL therebetween.

Since the odd-numbered thin film transistors and the even-numbered thin film transistors are disposed close to each other, they can share a gate electrode. As shown in FIG. 5, the first thin film transistor T1 and the second thin film transistor T2 may have a structure in which the gate electrode G is shared. In such a structure, the pattern holes PH exposing the thin film transistors T may be formed to simultaneously expose odd-numbered thin film transistors and even-numbered thin film transistors arranged adjacent to each other by oriented with each other. As shown in FIG. 5, the first thin film transistor T1 and the second thin film transistor T2 may have a structure in which one pattern hole PH is exposed.

In this case, a separation distance between two adjacent pattern holes PH along the gate line GL may be about twice as large as that of the first embodiment. Accordingly, even if the size of the unit pixel is reduced in the pixel array implementing ultra-high resolution, the separation distance between neighboring pattern holes PH may be maintained at least 12 μm or more. That is, the spacing of the pattern holes PH secures a space larger than 8 to 9 μm, which is the lower width of the spacer CS. Accordingly, by arranging the spacer CS to overlap the gate line GL between the pattern hole PH and the pattern hole PH, the spacer CS may not overlap the pattern hole PH. In addition, the arrangement density of the spacers CS can be uniformly designed, and a cell gap between the thin film transistor substrate and the color filter substrate can be uniformly maintained over the entire substrate.

As described above, in the second embodiment of the present invention, by arranging to have one pattern hole PH per two neighboring pixel areas along the gate line GL, between the pattern hole PH and the pattern hole PH A sufficient space for arranging the spacers CS can be secured. As a result, since the spacer CS can be formed in a uniform distribution so that the cell gap can be kept constant, it is possible to prevent screen stains due to the spacer CS and the cell gap defect.

Hereinafter, a method of manufacturing a thin film transistor substrate according to a second embodiment of the present invention will be described with reference to FIGS. 7A to 7F. 7A to 7F are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a second exemplary embodiment of the present invention, cut by a cut line III-III' in FIG. 5.

A gate metal material is applied on the substrate SUB and patterned by a first mask process to form a gate element. The gate element includes a gate wiring GL running in the horizontal direction of the substrate SUB and a gate electrode G branching from the gate wiring GL. It is preferable to form the gate electrode G over two adjacent pixel regions. In particular, a gate electrode G is formed at the boundary between the first pixel region P1 and the second pixel region P2 to span the two pixel regions P1 and P2.

More specifically, the gate electrode G1 of the first pixel region P1 and the gate electrode G2 of the second pixel region P1 are formed to be one gate electrode. Also, the gate electrode G3 of the third pixel region P3 and the gate electrode G4 of the fourth pixel region P4 are formed to be one gate electrode. (Fig. 7a)

A gate insulating film GI is applied on the substrate SUB on which the gate element is formed. Subsequently, a semiconductor material and a source-drain metal material are continuously deposited on the gate insulating layer GI. A semiconductor material and a source-drain metal material are continuously patterned in a second mask process to form a semiconductor layer A and a source-drain element overlapping the gate electrode G. The source-drain elements proceed in the vertical direction of the substrate SUB, and are branched so as to overlap the gate electrode G in the data line DL and the data line DL crossing the gate line GL. SD). Here, the source-drain electrode SD has not yet been separated and is formed as a single body. The semiconductor layer (A) is formed in the same shape as the source-drain element.

For example, a first source-drain electrode SD1 and a first semiconductor layer A1 are formed on the gate electrode G1 of the first pixel region P1, and the gate electrode G2 of the second pixel region P2. A second source-drain electrode SD2 and a second semiconductor layer A2 are formed thereon. That is, on one gate electrode G formed at the boundary between the first pixel region P1 and the second pixel region P2, the first source-drain electrode SD1, the first semiconductor layer A1, and two The second source-drain electrode SD2 and the second semiconductor layer A2 are formed adjacent to each other.

Similarly, the third source-drain electrode SD3 and the third semiconductor layer A3 are placed on the gate electrode G3 of the third pixel area P3, and the fourth source-drain electrode SD3 and the third semiconductor layer A3 are placed on the gate electrode G4 of the fourth pixel area P4. A fourth source-drain electrode SD4 and a fourth semiconductor layer A4 are formed. That is, on one gate electrode G formed at the boundary between the third pixel region P3 and the fourth pixel region P4, the third source-drain electrode SD3 and the third semiconductor layer A3, and four The fourth source-drain electrode SD4 and the fourth semiconductor layer A4 are formed adjacent to each other. (Fig. 7b)

A first passivation layer PA1 and a planarization layer PAC are successively applied on the source-drain element. A pattern hole PH exposing the thin film transistor T is formed by patterning the first passivation layer PA1 and the planarization layer PAC in a third mask process. For example, the pattern hole PH is formed to simultaneously expose the first thin film transistor T1 disposed in the first pixel area P1 and the second thin film transistor T2 disposed in the second pixel area P2. do. Similarly, a pattern hole PH is formed to simultaneously expose the third thin film transistor T3 disposed in the third pixel area P3 and the fourth thin film transistor T4 disposed in the fourth pixel area P4. . (Fig. 7c)

A transparent conductive material such as Indium-Tin-Oixide (ITO) and Indium-Zinc-Oxide (IZO) is applied on the entire surface of the substrate SUB in which the pattern holes PH are formed. . In the fourth mask process, a transparent conductive material and a source-drain electrode are simultaneously patterned to form a source electrode (S) and a drain electrode (D) to define a channel region, and a pixel electrode connected to the drain electrode (D) (PXL) is formed.

For example, the first source-drain electrode SD1 formed on the first semiconductor layer A1 is separated to form a first source electrode S1 and a first drain electrode D1. In particular, since the transparent conductive material is stacked on the first drain electrode D1, the first pixel electrode PXL1 extending to the pixel region can be simultaneously formed. Similarly, the second source-drain electrode SD2 formed on the second semiconductor layer A2 is separated to form a second source electrode S2 and a second drain electrode D2, and the second drain electrode D2 and A second pixel electrode PXL2 in contact is formed. Hereinafter, in the third and fourth pixel regions, the third source electrode S3, the third drain electrode D3, and the third pixel electrode PXL3, respectively, and the fourth source electrode S4 and the fourth drain electrode ( D4) and a fourth pixel electrode PXL4 are formed.

Since the pixel electrodes PXL directly contact the drain electrode D through the pattern hole PH, the drain electrode D itself does not extend to contact the pixel electrode PXL, and the drain electrode D There is no need to secure a contact hole area for exposing. That is, the drain electrode D itself is exposed by the pattern hole PH exposing the thin film transistor, and the pixel electrode PXL is in direct contact with the exposed drain electrode D. Accordingly, by maximizing the size of the pixel electrode PXL, it is possible to secure a high aperture ratio in the ultra-high resolution liquid crystal display panel. (Fig. 7d)

A second passivation layer PA2 is formed to cover the entire substrate SUB on which the pixel electrodes PXL1 to PXL4 are formed. Subsequently, a transparent conductive material such as Indium-Tin-Oixide (ITO) and Indium-Zinc-Oxide (IZO) is applied on the entire surface of the second passivation layer PA2. In a fifth mask process, the common electrode COM is formed by patterning a transparent conductive material. The common electrode COM is formed as one body covering the entire upper surface of the substrate SUB. However, in the pixel region, the slit COMSL is formed so as to form a fringe field between the pixel electrode PXL, thereby forming a plurality of parallel line segment shapes. (Fig. 7e)

The thin film transistor substrate TFTS formed as described above is bonded to the color filter substrate CFS on which the color filter is formed at a predetermined interval (cell gap). In order to keep the cell gap constant, spacers CS are formed on the color filter substrate CFS or the thin film transistor substrate TFTS. In the second embodiment of the present invention, the spacer CS is disposed between two adjacent pattern holes PH along the gate line GL. (Fig. 7f)

Accordingly, in a portable liquid crystal display panel having an ultra-high resolution, the size of the pixel electrode PXL per unit pixel can be maximized. In addition, since the spacers CS can be arranged at the same position with a uniform distribution, the cell gap can be kept constant and display quality can be ensured satisfactorily.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the spirit of the present invention. Accordingly, the present invention should not be limited to the content described in the detailed description, but should be defined by the claims.

T: thin film transistor SUB: substrate
GL: Gate wiring CL: Common wiring
DL: data wiring PXL: pixel electrode
COM: common electrode GP: gate pad
DP: Data pad GPT: Gate pad terminal
DPT: Data pad terminal IGT: Gate pad middle terminal
GPH: gate pad contact hole GH1: first gate pad contact hole
GH2: second gate pad contact hole DPH: data pad contact hole
G: gate electrode S: source electrode
D: drain electrode A: semiconductor channel layer
GI: gate insulating film DH: drain contact hole
PA1: first protective film PA2: second protective film
PAC: planarization film ES: etch stopper
PH: Pattern hole CS: Spacer
TFTS: thin film transistor substrate CFS: color filter substrate

Claims (11)

First and second data lines running vertically on the substrate and disposed adjacent to each other;
A gate wiring running on the substrate in a horizontal direction;
A first thin film transistor and a second thin film transistor formed adjacent to each other at a portion where the first and second data lines and the gate line cross each other;
A third and a third disposed adjacent to each other such that a second pixel electrode and a third pixel electrode disposed adjacent to each other are disposed between the first and second data lines, and disposed adjacent to each other between the second data lines and the second data lines Fourth data lines;
A third thin film transistor and a fourth thin film transistor formed adjacent to each other at a portion where the third and fourth data lines and the gate line cross each other;
A first pixel electrode disposed on one side of the first data line; a fourth pixel electrode disposed on one side of the fourth data line; And
A planarization layer including a first pattern hole that covers the entire substrate and simultaneously exposes the first thin film transistor and the second thin film transistor and a second pattern hole that simultaneously exposes the third and fourth thin film transistors. Including,
In order to maintain a cell gap with the color filter substrate disposed to face the substrate, a spacer is positioned between the first pattern hole and the second pattern hole so as to overlap the gate wiring,
The first gate electrode of the first thin film transistor and the second gate electrode of the second thin film transistor are a partial region of a first pixel region in which the first pixel electrode is located, and a second pixel in which the second pixel electrode is located A thin film transistor substrate comprising a single body so as to overlap with a partial region of the region and a partial region of the first and second data lines between the first and second pixel regions.
The method of claim 1,
A passivation layer covering the first to fourth pixel electrodes; And
And a common electrode having a plurality of line segments overlapping the first to fourth pixel electrodes on the passivation layer.
delete The method of claim 1,
Each of the first to fourth thin film transistors,
A gate electrode branched from the gate wiring;
A semiconductor layer overlapping the gate electrode;
A source electrode branching from the data line and contacting one side of the semiconductor layer; And
And a drain electrode spaced apart from the source electrode by a predetermined distance and in contact with the other side of the semiconductor layer,
The first thin film transistor,
A first gate electrode on the substrate;
A first semiconductor layer disposed to overlap the first gate electrode on a gate insulating layer covering the first gate electrode;
A first drain electrode disposed on one side of the first semiconductor layer and having an upper surface in contact with one end of the first pixel electrode; And
And a first source electrode disposed to be spaced apart from the first drain electrode on the other side of the first semiconductor layer,
The second thin film transistor,
A second gate electrode positioned on the substrate and extending from the first gate electrode;
A second semiconductor layer disposed on the gate insulating layer to be spaced apart from the first semiconductor layer and disposed to overlap the second gate electrode;
A second drain electrode positioned on one side of the second semiconductor layer and having an upper surface in contact with one end of the second pixel electrode; And
And a second source electrode disposed to be spaced apart from the second drain electrode on the other side of the second semiconductor layer,
The first source electrode,
A first sub-source electrode layer positioned on the same layer as the first drain electrode; And
A second sub-source electrode layer disposed to contact a top surface of the first sub-source electrode layer, a side surface of the first semiconductor layer, and a portion of an upper surface of the gate insulating layer,
The second source electrode,
A third sub source electrode layer positioned on the same layer as the second drain electrode; And,
A fourth sub-source electrode layer disposed to contact a top surface of the third sub-source electrode layer, a side surface of the second semiconductor layer, and a portion of the top surface of the gate insulating layer,
The second sub-source electrode layer and the fourth sub-source electrode layer are formed of the same material as the first pixel electrode and the second pixel electrode, and are made of a material different from the first sub-source electrode layer and the third sub-source electrode layer. Thin film transistor substrate, characterized in that formed.
delete delete delete delete delete The method of claim 1,
The third gate electrode of the third thin film transistor and the fourth gate electrode of the fourth thin film transistor are a partial region of a third pixel region in which the third pixel electrode is located, and a fourth pixel in which the fourth pixel electrode is located A thin film transistor substrate, characterized in that the thin film transistor substrate is formed as another body so as to overlap a partial region of the region and a partial region of the first and second data lines between the third and fourth pixel regions.
The method of claim 1,
The first pixel electrode is connected to the first thin film transistor through the first pattern hole, the second pixel electrode is connected to the second thin film transistor through the first pattern hole,
The third pixel electrode is connected to the third thin film transistor through the second pattern hole, and the fourth pixel electrode is connected to the fourth thin film transistor through the second pattern hole. .

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