KR102081134B1 - Cholesteric liquid crystal display device and driving method for the same - Google Patents

Abstract

The present invention discloses a liquid crystal display device. More specifically, the present invention, when implementing the display device using the characteristics of the cholesteric liquid crystal, an efficient pixel control method for this, and improves the flicker characteristics caused by the control method A cholesteric liquid crystal display device and a driving method thereof are provided.
According to an exemplary embodiment of the present invention, a cholesteric liquid crystal panel is provided without a high output main driver IC by providing a plurality of thin film transistors in one pixel and applying a high voltage to the cholesteric liquid crystal through bootstrapping. There is an effect that can perform a stable control with low power consumption.

Description

Cholesteric liquid crystal display and its driving method {CHOLESTERIC LIQUID CRYSTAL DISPLAY DEVICE AND DRIVING METHOD FOR THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device. In particular, when a display device is implemented using characteristics of cholesteric liquid crystal, an efficient pixel control method and flicker generated due to the control method are provided. A liquid crystal display device having improved characteristics and a driving method thereof are provided.

Recently, various portable devices such as mobile phones and laptop computers, and information electronic devices that implement high resolution and high quality images such as HDTVs have been developed. The demand for devices is gradually increasing. Such flat panel displays include liquid crystal displays (LCDs), plasma display panels (PDPs), field emission displays (FEDs), and organic light emitting diodes (OLEDs), but mass production technologies, ease of driving, Liquid crystal displays (LCDs) are currently in the spotlight due to their realization and realization of large-area screens.

Such a liquid crystal display device is generally composed of a liquid crystal panel having two substrates spaced apart from each other by a predetermined distance to face each other, a liquid crystal panel having a liquid crystal layer interposed therebetween, and a backlight unit for supplying light thereto. By forming an electric field corresponding to the image to be displayed on the liquid crystal layer through, the light transmittance of the liquid crystal layer is changed to display an image.

In the conventional liquid crystal display device, a backlight unit, which is a separate light source rather than external light, must be provided, which causes an increase in manufacturing cost and power consumption for driving the liquid crystal display device. In addition, the liquid crystal display device must be provided with polarizing plates on both sides of the liquid crystal panel to express the gray level of the image, which reduces the efficiency of the light emitted from the backlight unit, so that the backlight unit must be driven at a higher luminance. Cause to raise.

In order to overcome the above limitations, the polarizing plate is omitted by using a cholesteric LC having a property of selectively reflecting light depending on the molecular arrangement of the liquid crystal layer instead of a general nematic LC. A liquid crystal display device having improved light efficiency through reflective driving has been proposed.

1 is a view schematically showing a structure of a liquid crystal display device using a conventional cholesteric liquid crystal.

Referring to FIG. 1, a conventional Cholesteric liquid crystal display device includes a liquid crystal panel 10 having a cholesteric liquid crystal layer 18 interposed on two substrates 11 and 12, and one surface of the liquid crystal panel 10. It is disposed in the backlight unit 20 for supplying light.

The liquid crystal panel 10 includes a first substrate 11 having a plurality of signal wirings and electrodes formed thereon, and a thin film transistor disposed at the intersections of the signal wirings to form a metal pattern 13 constituting one pixel; The first substrate 11 includes a second substrate 12 facing the substrate 11 and having a color filter and a black matrix 15, and a cholesteric liquid crystal 18 is interposed between the two substrates 11 and 12.

In addition, the backlight unit 20 is disposed on one surface of the liquid crystal panel 10. The backlight unit 20 includes a light source including any one of fluorescent lamps and LEDs, and a plurality of optical members for increasing light efficiency thereof.

In contrast to the nematic liquid crystal display device, the cholesteric liquid crystal display device having such a structure can express gray scales without a polarizing plate, unlike the nematic liquid crystal display, and can be driven in a reflective type according to its optical characteristics. have. Therefore, the polarizing plates provided on both surfaces of the liquid crystal panel 10 may be omitted, and the light efficiency of the backlight unit may be improved and the light source itself may be omitted.

On the other hand, cholesteric liquid crystals are characterized by having three states: a planner state, a focal conic state, and a homeotropic state. These three phases are switched by applying a voltage of a predetermined level or more to the liquid crystal, and once entering a stable state after phase switching, voltages above or below the threshold of each phase should be applied to escape the state. In general, in order to change the state of the cholesteric liquid crystal, an image is realized by switching to a homeotropic phase in any of the above three states, and then to a planar or focal conic phase capable of expressing a desired gradation. .

However, when switching from an arbitrary phase to a homeotropic phase, a voltage of at least 40 V should be applied to the liquid crystal layer. A commercially available main driver IC does not have an IC capable of stably supplying a high voltage of at least 40 V. However, even when using such a data driver IC, there is a limit that the efficiency is low due to the high power consumption due to the high voltage driving.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to implement a voltage for entering a clear section of a cholesteric liquid crystal display device in a pixel instead of the main driver IC, so that a low output of 40 V or less is achieved. The present invention provides a liquid crystal display device and a driving method thereof which can be controlled using a main driver IC having a voltage.

In addition, another object of the present invention is to provide a cholesteric liquid crystal display device and a driving method thereof which minimize image degradation caused by signal distortion of a cholesteric liquid crystal display device performing phase conversion on a frame basis.

In the cholesteric liquid crystal display according to the exemplary embodiment of the present invention, the first and second gate lines and the data lines are cross-formed, and the pixel including the liquid crystal capacitor bootstrap voltage applied through the data lines to form the liquid crystal. A liquid crystal panel including a plurality of thin film transistors and a storage capacitor for switching the liquid crystal state of the capacitor; A gate driver configured to alternately output first and second gate driving signals to the pixels; A data driver outputting a data signal to the pixel; And a timing controller configured to control the gate driver and the data driver, wherein the pixel comprises: a first thin film transistor connecting the data line and the first node in response to the first gate drive signal of the first gate line; A second thin film transistor connecting the second node and the common voltage terminal in response to the first gate driving signal of the first gate line; A third thin film transistor connecting the data line and the second node in response to a second gate driving signal of the second gate line; A first storage capacitor coupled to the first node and the second node; And a second storage capacitor connected to the second node and the common voltage terminal, wherein the liquid crystal capacitor is connected to the first node and the common voltage terminal.

In the driving method of the cholesteric liquid crystal display device according to the embodiment of the present invention, the pixel including the cholesteric liquid crystal capacitor is driven by being divided into a clear period, a rest period, and a data period, and the clear period is for two horizontal periods. The idle period and the data period are each performed over one horizontal period.

According to an exemplary embodiment of the present invention, a cholesteric liquid crystal panel is provided without a high output main driver IC by providing a plurality of thin film transistors in one pixel and applying a high voltage to the cholesteric liquid crystal through bootstrapping. There is an effect that can perform a stable control with low power consumption.

In addition, according to another embodiment of the present invention, the liquid crystal display device can be controlled more stably than the method of performing phase conversion on a frame basis by controlling the Colexsteric liquid crystal display device in one horizontal period unit, thereby increasing the reliability of the device. There is an effect to improve.

1 is a view schematically showing a structure of a liquid crystal display device using a conventional cholesteric liquid crystal.
FIG. 2 is a view schematically showing the entire structure of a cholesteric liquid crystal display according to an embodiment of the present invention.
3 is an equivalent circuit diagram of one pixel of FIG. 2.
4 is a diagram illustrating a signal waveform when driving the liquid crystal display according to the exemplary embodiment of the present invention.
5A and 5B illustrate examples of signal waveforms when an image is implemented by a pixel driving method according to positive and negative polarities, respectively, according to an exemplary embodiment of the present invention.
6 is a diagram illustrating a signal waveform according to a driving method of a cholesteric liquid crystal display device according to another embodiment of the present invention, and FIGS. 7A to 7D are diagrams illustrating driving patterns of one pixel according to the signal waveform of FIG. 6. to be.
8A and 8B are diagrams illustrating examples of signal waveforms when an image is implemented by a pixel driving method according to positive and negative polarities, respectively, according to another embodiment of the present invention.

Hereinafter, a liquid crystal display and a driving method thereof according to a preferred embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a diagram schematically illustrating the entire structure of a cholesteric liquid crystal display device according to an exemplary embodiment of the present invention, and FIG. 3 is an equivalent circuit diagram of one pixel of FIG. 2.

2 and 3, the cholesteric liquid crystal display device of the present invention includes at least three thin film transistors T1 to T3 and a cholesteric liquid crystal capacitor CLC in one pixel PX. The liquid crystal panel in which the first and second storage capacitors Cst1 and Cst2 are formed, the first and second gate lines GL1 and GL2 connected to the plurality of pixels PX1, and the data line DL are formed. 100 and a gate driver 110 outputting gate driving signals Vg1 and Vg2 through the first and second gate lines GL1 and GL2 and a data driver outputting a data signal through the data line DL. And a timing controller 130 that controls each of the drivers 110 and 120.

In the liquid crystal panel 100, two transparent substrates made of glass or plastic are bonded to each other by a predetermined distance, and a cholesteric liquid crystal layer is interposed therebetween. Of the two substrates, a plurality of data lines DL are arranged in a matrix form on one substrate in a direction perpendicular to the gate lines GL1 and GL2 and the gate lines GL1 and GL2, and a pixel ( PX) is defined. Although not shown, separate polarizing plates are not provided on the surfaces of the two substrates of the liquid crystal panel 100.

A plurality of pixels PX form a display area, and a plurality of thin film transistors T1 to T3 are formed in each pixel PX. The first thin film transistor T1 serves to apply a data signal to the liquid crystal capacitor CLC, and the second and third thin film transistors T2 and T3 bootstrap the voltage stored in the liquid crystal capacitor CLC. It is provided for boosting up to the desired level via bootstrapping.

Here, the gate of the first thin film transistor T1 is connected to the first gate line GL to be turned on / off by the first gate driving signal Vg1, and the drain is connected to the data line DL. The source is connected to the pixel electrode. In addition, the pixel electrode forms a liquid crystal capacitor CLC with an opposite common electrode. As the charge corresponding to the data signal applied through the data line DL is charged in the liquid crystal capacitor CLC, the light of the cholesteric liquid crystal layer The transmittance is changed to display an image.

In this case, the second and third thin film transistors T2 and T3 are formed through the first and second storage capacitors Cst1 and Cst2 according to the first and second gate driving signals Vg1 and Vg2, respectively. The liquid crystal state of the liquid crystal capacitor (CLC) is converted into a state by any one of a planner, focal conic, and homeotropic by bootstrapping the voltage stored therein. Here, the liquid crystal capacitor (CLC) has to go through three steps of CLEAR, IDLE, and DATA to stably implement the gradation of the image to be displayed, and each step is performed for one frame period. . The driving method of the liquid crystal display device according to the structures of the plurality of thin film transistors T1 to T3 and the capacitors CLC, Cst1 and Cst2 will be described later.

The gate driver 110 is provided at one end of the liquid crystal panel 100, and an output terminal thereof is electrically connected to the plurality of first and second gate lines GL1 and GL2.

The gate driver 110 applies the gate driving signal Vg1 to the first and second gate lines GL1 and GL2 arranged on the liquid crystal panel 100 in response to the gate control signal GCS applied from the timing controller 130. , Vg2) is sequentially applied to each of the thin film transistors T1 to T3 to be turned on or turned off. Accordingly, data of the analog waveform supplied from the data driver 120 is provided. The signal charges and boosts up each capacitor (CLC, Cst1, Cst2).

The gate control signal GCS for controlling the gate driver 110 includes a gate start signal, a gate shift clock, a gate output enable, and the like.

The data driver 120 converts the aligned image signal aRGB, which is input according to the data control signal DCS input from the timing controller 130, into an analog data signal Vdata using a reference voltage. The data signals Vdata are latched by pixels on one horizontal line and are simultaneously output to the liquid crystal panel 100 through all the data lines DL in correspondence to the first and second gate driving signals Vg1 and Vg2. At this time, the data driver 120 properly outputs the data signal Vdata according to three stages of CLEAR, IDLE and DATA, and a level for boosting up in the CLEAR period. A voltage of 0 is output, and a voltage of 0 V is output during the idle period, and a data signal Vdata of a level corresponding to the gray level of the image to be actually displayed is output in the data DATA section.

The data control signal DCS for controlling the data driver 120 includes a source start pulse (SSP), a source shift clock (SSC), and a source output enable (SOE). And polarity inversion signals (Polarity, POL).

The timing controller 130 receives the image data RGB applied from the outside and predetermined timing signals Vsync and Hsync, and arranges the image data aRGB, the gate control signal GCS, and the data control signal DCS) and the like are output to each of the driving units 110 and 120. The timing controller 130 is designed to be connected to an external system through a predetermined interface and to receive image-related signals and timing signals outputted therefrom at high speed without noise. These interfaces include LVDS (Low Voltage Differential Signal) or TTL (Transistor-Transistor Logic) interface.

According to this structure, the cholesteric liquid crystal display device of the present invention can perform phase switching of the cholesteric liquid crystal by boosting up the voltage stored in the liquid crystal capacitor CLC in the pixel without a separate high voltage supply circuit. Hereinafter, a structure and a driving method of one pixel of the cholesteric liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a signal waveform when driving the liquid crystal display according to the exemplary embodiment of the present invention.

Referring to FIG. 4 together with FIG. 3, one pixel PX formed in the liquid crystal display according to the present invention has a structure in which a gate is connected to two gate lines GL1 and GL2 and one data line DL. A first thin film transistor T1 connected to the first gate line GL1, a drain connected to the data line DL, and a source connected to the first node N1, and a gate connected to the first gate line GL1. ) Is connected to the second node N2, a drain is connected to the second node N2, a source is connected to the common voltage Vcom, a gate is connected to the second gate line GL2, A drain is connected to the data line DL and a liquid crystal capacitor is connected between the third thin film transistor T3 having a source connected to the second node N2, and between the first node N1 and the common voltage Vcom. CLC, the first storage capacitor Cst1 connected between the first node N1 and the second node N2, the common voltage Vcom terminal, and the second node N2. In a second storage capacitor (Cst1) it is connected.

In the pixel driving of the above structure, first, a high level gate driving signal Vg1 is applied through the first gate line GL1, and in synchronization therewith, a data signal of the first voltage Vd + is applied through the data line DL. When Vdata is applied, as the first thin film transistor T1 is turned on, the first voltage Vd + is charged to the first node N1. Herein, the data signal Vdata has a reference voltage Vref, that is, a voltage level of maximum gradation for positive and negative polarities with respect to the common voltage Vcom and the first voltage Vd + and respectively. It is assumed that the second voltage Vd− is 25V and 0V in the embodiment of the present invention. In addition, the common voltage Vcom is a voltage that alternates 0V and 40V per frame for polarity inversion driving.

Thereafter, the gate driving signal Vg1 having a low level is applied through the first gate line GL1 to switch the first node N1 into a floating state, and the high state is transferred through the second gate line GL2. The first node N1 is bootstrapping by the first storage capacitor Cst1 by applying the gate driving signal Vg2 of the level to charge the first voltage vd + to the second node N2. As a result, the voltage level rises, so that the voltage stored in the liquid crystal capacitor CLC, that is, the pixel voltage Vp, rises to 40 V, which is a voltage capable of converting the cholesteric liquid crystal into a homeotropic state. do.

Accordingly, a voltage of 40 V is applied to the liquid crystal capacitor CLC and enters a clear period. This state is maintained for one frame, and then, after going through the IDLE period of one frame, the gradation value of the image to be actually displayed as the data period in the next one frame as the data signal Vdata. Supply to implement an image.

5A and 5B illustrate examples of signal waveforms when an image is implemented by a pixel driving method according to positive and negative polarities, respectively, according to an exemplary embodiment of the present invention.

Referring to FIGS. 5A and 5B, the cholesteric liquid crystal display device of the present invention is a liquid crystal state for displaying an image and should be in a planer state or a focal conic state. And a clear period, a rest period, and a data period of at least three frames.

First, in the clear period of one frame, the high level first and second gate driving signals Vg1 and Vg2 are sequentially input, and the voltage applied to the liquid crystal capacitor by applying the data signal Vdata to 25V, that is, the pixel voltage. Boost up (Vp) to 40V to switch the liquid crystal to the homeotropic state.

Subsequently, in the idle period of one frame, the first and second gate driving signals Vg1 and Vg2 are equally applied, but the pixel voltage Vp is set to 0V by applying the data signal Vdata to 0V, thereby providing a liquid crystal state. It will reset.

Subsequently, a voltage for converting the liquid crystal to a desired phase is applied according to the first and second gate driving signals Vg1 and Vg2 in the data period of one frame. In FIG. 5A, an example of applying 0 V as a voltage for switching a liquid crystal to a planer state is shown. Accordingly, the cholesteric liquid crystal is placed in a planer state by applying 0 V as a data signal Vdata. Conversion and maintenance.

In addition, in order to convert the cholesteric liquid crystal into the focal conic state in order to realize a desired image, the liquid crystal phase is controlled through the same three steps as described above. As shown in FIG. 5B, the pixel voltage Vp is charged to 40V by applying a data signal of 0V in a clear period in response to the common voltage Vcom swinging at 40V for negative driving. Subsequently, a 5V data signal is applied to charge the data signal Vdata in the focal conic state to be displayed in the data period, for example, the pixel voltage Vp of 30V.

By the pixel structure and driving method described above, the cholesteric liquid crystal display device of the present invention implements an image according to the intended liquid crystal state.

Meanwhile, in the above-described embodiment, the two frame periods except the data period for applying the actual data signal Vdata are sections in which the high-level voltage applied to the capacitor is maintained. In this case, the data is distorted and thus flickers in the image. Can be admitted in form. Hereinafter, a driving method of the cholesteric liquid crystal display device according to another embodiment of the present invention, which solves the data distortion problem, will be described.

6 is a diagram illustrating a signal waveform according to a driving method of a cholesteric liquid crystal display device according to another embodiment of the present invention, and FIGS. 7A to 7D are diagrams illustrating driving patterns of one pixel according to the signal waveform of FIG. 6. to be.

6, 7A, and 7D, the cholesteric liquid crystal display device of the present invention is cleared in one pixel PX for a total of 4 horizontal periods (1H to 4H) in units of 1 horizontal period (1H). Period, rest period and data period are performed.

First, referring to FIG. 7A, in the first first horizontal period 1H, the gate driving signal Vg1 having the high level VGH is applied through the first gate line, and in synchronization therewith, the first voltage, For example, when the data signal Vdata of 25V is applied, as the first thin film transistor T1 is turned on, the voltage of 25V is charged to the first node N1.

Subsequently, as shown in FIG. 7B, in the second horizontal period 2H, the gate driving signal Vg1 having the low level VGL is applied through the first gate line to form the first and second thin film transistors T1 and T2. By turning off), the first node N1 is in a floating state. In addition, as the gate driving signal Vg2 having the high level VGH is applied through the second gate line, the third thin film transistor T3 is turned on and the first node 25 has a first voltage of 25V. As the voltage is charged, the first node N1 is bootstrapping by the first storage capacitor Cst1 to increase the voltage level. As a result, the pixel voltage Vp stored in the liquid crystal capacitor CLC is 40 V, which is the second voltage, and the cholesteric liquid crystal is in a homeotropic state. That is, the clear periods are performed during the first and second horizontal periods 1H and 2H.

Next, referring to FIG. 7C, the gate driving signal Vg1 having the high level VGH is applied to the first gate wiring, and the gate driving signal Vg2 having the low level VGL is applied to the second gate wiring. Accordingly, the first and second thin film transistors T1 and T2 are turned off and the third thin film transistor T3 is turned on. At the same time, the data voltage Vdata of a third voltage, for example, 0V, is applied through the data line to discharge the first node N1 to 0V. Accordingly, the rest period is performed during the third horizontal period 3H. As a result, the cholesteric liquid crystal is reset.

Referring to FIG. 7D, the first and second thin film transistors T1 and T2 are turned off by applying the gate driving signal Vg1 having the low level VGL through the first gate line. N1) becomes a floating state. In addition, the gate driving signal Vg2 having the high level VGH is applied through the second gate wiring, and the data signal Vdata corresponding to the grayscale voltage to be displayed through the data wiring, for example, a voltage level of 20V is applied. When the data signal Vdata is output, the third thin film transistor T3 is turned on and a voltage of 20 V is charged in the second node N2 so that the first node N1 is connected to the first storage capacitor Cst1. By bootstrapping, the pixel voltage Vp rises from 0V to 20V.

Accordingly, the data period is performed during the fourth horizontal period 4H. Thus, the image to be displayed through the cholesteric liquid crystal is implemented.

8A and 8B are diagrams illustrating examples of signal waveforms when an image is implemented by a pixel driving method according to positive and negative polarities, respectively, according to another embodiment of the present invention.

8A and 8B, a cholesteric liquid crystal display device according to another embodiment of the present invention is a liquid crystal state for displaying an image as a planer state or a focal conic state. It is used to perform a clear period, a rest period and a data period over at least four horizontal periods 4H.

First, in the clear period of two horizontal periods 2H, the first and second gate driving signals Vg1 and Vg2 having high levels are sequentially input, and the voltage applied to the liquid crystal capacitor by applying the data signal Vdata to 25V. That is, the pixel voltage Vp is boosted to 40V to switch the liquid crystal to the homeotropic state.

Subsequently, the first and second gate driving signals Vg1 and Vg2 are equally applied in the idle period of one horizontal period 1H, but the pixel voltage Vp is set to 0V by applying the data signal Vdata to 0V. The liquid crystal state is reset.

Thereafter, in the data period of the last one horizontal period 1H, a voltage for converting the liquid crystal to a desired phase is applied according to the first and second gate driving signals Vg1 and Vg2. FIG. 5A shows an example of applying a common voltage of 0 V and 40 V and a data signal V data of 20 V as a voltage for switching the liquid crystal into a planer state of positive and negative polarity. Rick liquid crystal is switched to and maintained in the planer state.

In addition, in order to convert the cholesteric liquid crystal into a positive and negative focal conic state to realize a desired image, the image of the liquid crystal is controlled for the same four horizontal periods 4H. In FIG. 8B, a signal waveform according to a focal conic drive of 25V is shown.

By the pixel structure and driving method described above, the cholesteric liquid crystal display device of the present invention implements an image according to the intended liquid crystal state.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

100: liquid crystal panel 110: gate driver
120: data driver 130: timing controller
GL1, GL2: first and second gate wiring DL: data wiring
Vg1, Vg2: first and second gate driving signals Vdata: data signal
RGB: Image data aRGB: Sorted image data
Vsync, Hsync, CLK: Timing signal GCS: Gate control signal
DCS: Data Control Signal

Claims (12)

A plurality of thin film transistors each of which first and second gate lines and data lines are cross-formed, and each pixel including a liquid crystal capacitor bootstrap voltage applied through the data lines to switch the liquid crystal state of the liquid crystal capacitor; A liquid crystal panel including a storage capacitor;
A gate driver configured to alternately output first and second gate driving signals to the pixel;
A data driver for outputting a data signal to the pixel; And
A timing controller for controlling the gate driver and the data driver;
The pixel is
A first thin film transistor connecting the data line and the first node in response to the first gate driving signal of the first gate line;
A second thin film transistor connecting a second node and a common voltage terminal in response to the first gate driving signal of the first gate line;
A third thin film transistor connecting the data line and the second node in response to the second gate driving signal of the second gate line;
A first storage capacitor coupled to the first node and the second node; And
A second storage capacitor connected to the second node and the common voltage terminal;
And the liquid crystal capacitor is connected to the first node and the common voltage terminal. The method of claim 1,
The liquid crystal capacitor
Cholesteric liquid crystal layer; And
A cholesteric liquid crystal display device comprising first and second electrodes disposed above and below the cholesteric liquid crystal layer. The method of claim 1,
The pixel,
The first and second thin film transistors are turned on to apply a first voltage from the data driver to the first node and a common voltage from the common voltage terminal to the second node. A thin film transistor is turned on to apply the first voltage to the second node so that a second voltage higher than the first voltage is applied to the first node in a floating state by bootstrapping the first storage capacitor. section;
An idle period in which the first and second thin film transistors are turned on to apply a third voltage from the data driver to the first node and the common voltage to the second node;
The third thin film transistor is turned on so that the gray voltage from the data driving is applied to the second node, and the gray voltage is applied to the first node in the floating state by bootstrapping of the first storage capacitor. A cholesteric liquid crystal display device driven by a section. The method of claim 1,
The liquid crystal capacitor,
A cholesteric liquid crystal display device driven by a clear section of the first and second horizontal periods, a rest section of the third horizontal period, and a data section of the fourth horizontal period. In the driving method of a liquid crystal display device comprising a plurality of pixels including a liquid crystal capacitor having a cholesteric liquid crystal layer,
Each of the plurality of pixels is driven by being divided into a clear period, a pause period, and a data period.
The clearing interval is performed for two horizontal periods, and the idle period and the data interval are each performed over one horizontal period;
The pixel is
A first thin film transistor connecting the data line and the first node in response to a first gate driving signal of the first gate line;
A second thin film transistor connecting a second node and a common voltage terminal in response to the first gate driving signal of the first gate line;
A third thin film transistor connecting the data line and the second node in response to a second gate driving signal of a second gate line;
A first storage capacitor coupled to the first node and the second node; And
A second storage capacitor connected to the second node and the common voltage terminal;
And the liquid crystal capacitor is connected to the first node and the common voltage terminal. delete The method of claim 5, wherein
The clear section,
The first gate driving signal having a high level is applied to the first gate wiring, the second gate driving signal having a low level is applied to the second gate wiring, and a first voltage is applied to the data wiring. Charging a first node to the first voltage and charging the second node to a common voltage from the common voltage terminal; And
The first gate driving signal having a low level is applied to the first gate wiring, and the second gate driving signal having a high level is applied to the second gate wiring to charge the second node to the first voltage. And charging the first node in a floating state to a second voltage higher than the first voltage by bootstrapping the first storage capacitor. delete delete The method of claim 5, wherein
The rest period is,
The first gate driving signal having a high level is applied to the first gate wiring, the second gate driving signal having a low level is applied to the second gate wiring, and a third voltage is applied to the data wiring to apply the first voltage. Charging a node to the third voltage and charging the second node to a common voltage from the common voltage terminal. The method of claim 5, wherein
The data section,
The first gate driving signal having a low level is applied to the first gate wiring, the second gate driving signal having a high level is applied to the second gate wiring, and a gray voltage is applied to the data wiring, A method of driving a cholesteric liquid crystal display device comprising charging one node and a second node to the gray voltage. The method of claim 11,
The data section,
And a method of driving the cholesteric liquid crystal layer of the liquid crystal capacitor into a planar state or a focal conic state.

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