KR102059787B1 - Array substrate for liquid crystal display device - Google Patents

Abstract

The present invention, the substrate; A plurality of gate lines and data lines formed on the substrate to define a plurality of pixel regions crossing each other; A thin film transistor provided in each pixel area; And a pixel electrode provided in each pixel area and in contact with the drain electrode of the thin film transistor, and separated from each pixel area under the data line and having the semiconductor layer of the thin film transistor formed on the same layer. Provided is an array substrate for a fringe field switching mode liquid crystal display device having a shield pattern made of the same material.

Description

Array substrate for liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device capable of improving an aperture ratio.

In recent years, as the society enters the information age, the display field for processing and displaying a large amount of information has been rapidly developed. In recent years, as a flat panel display device having excellent performance of thinning, light weight, and low power consumption, Liquid crystal displays have been developed to replace existing cathode ray tubes (CRTs).

Among the liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor (Tr), which is a switching element capable of controlling voltage on and off for each pixel, has a resolution. And it is attracting the most attention because of its ability to implement video.

The liquid crystal has an elongated molecular structure, which is oriented in orientation, and when placed in an electric field, the direction of molecular arrangement changes according to its size and direction.

Accordingly, the liquid crystal display includes a liquid crystal panel in which a liquid crystal layer is positioned between two substrates on which electric field generating electrodes are formed, and artificially adjusts an arrangement direction of liquid crystal molecules through a change in an electric field generated between the two electrodes. Various images are displayed by changing the light transmittance accordingly.

The liquid crystal display device having such a configuration operates in various modes depending on the driving mode of the liquid crystal or the characteristics of the electric field applied to the liquid crystal.

That is, the liquid crystal display device operates in a vertical electric field mode, a transverse electric field mode, a fringe field switching mode, and the like.

In the liquid crystal display device for driving such various driving, an array substrate including a thin film transistor (Tr), which is essentially a switching element, is provided in order to remove each of the pixel areas on and off.

On the other hand, in recent years, the fringe field switching mode liquid crystal display device having excellent viewing angle characteristics among the various modes described above and relatively superior aperture ratio and transmittance is mainly used.

Therefore, the structure of the array substrate for fringe field switching mode liquid crystal display device will be described as an example.

1 is a plan view of a portion of a display area of a conventional array substrate for a fringe field switching mode liquid crystal display device.

As illustrated, a plurality of gate wires 43 are formed in a conventional fringe field switching mode liquid crystal display array substrate 1 in one direction, and intersect with each of the plurality of gate wires 43. The area P is defined and a plurality of data wires 51 are formed.

A thin film transistor Tr connected to the gate line 43 and the data line 51 is formed in each pixel region P, which is an area captured by the gate line 43 and the data line 51. have.

The thin film transistor Tr may be a source contacting and spaced apart from each other in contact with the semiconductor layer 41 of polysilicon, the gate insulating layer (not shown), the gate electrode 44, and the semiconductor layer 41 of the polysilicon, and The drain electrodes 55 and 58 are comprised.

At both ends of the semiconductor layer 41 of each polysilicon, a semiconductor layer contact hole (sch) is provided to contact the semiconductor layer 41 of the polysilicon and the source electrode and the drain electrode 55, 58, respectively. .

Meanwhile, a planarization layer (not shown) having a flat surface made of photoacryl over the thin film transistor Tr and having a drain contact hole dch exposing the drain electrode 58 of the thin film transistor is provided. The pixel electrode 60 is provided on the planarization layer (not shown) by contacting the drain electrode 58 of the thin film transistor Tr through the drain contact hole dch.

The common electrode 70 is formed on the pixel electrode 60 to correspond to the display area through an insulating layer (not shown).

In this case, the common electrode 70 formed in the display area has a bar shape parallel to the data line 51 corresponding to the pixel electrode 60 provided in each pixel area P. The opening op is provided.

On the other hand, the array substrate 1 for the fringe field switching mode liquid crystal display device having the above-described configuration is bonded to an opposing substrate (not shown) having a color filter layer to form a fringe field switching mode liquid crystal display device. The mode liquid crystal display device is used for a large display device such as a TV, or a personal portable device including a display area having a relatively small size, for example, a smartphone, a tablet PC, or the like.

In addition, such large and small display devices have high resolution specifications, and thus, products having excellent display quality are preferred.

In the display device, the resolution is defined as the number of pixels displayed per unit area (PPI: pixel per inch), and the high resolution product generally refers to a product having 300PPI (pixel per inch) or more, and recently, a high resolution of 500PPI or more. There is also a need for a display device having a.

On the other hand, in order to realize a high resolution in a display device, the number of pixel regions to be implemented per unit area must be increased, so that the size of each pixel region is reduced.

In this case, the size of the storage capacitor to be provided in each pixel area P is also reduced, thereby reducing the storage capacitor capacity.

In the array substrate 1 for the fringe field switching mode liquid crystal display device, the storage capacitor includes a pixel electrode 60 and a common electrode 70 overlapping the insulating layer in each pixel region P. The storage capacitor C _st having such a configuration has a smaller capacity in proportion to the area of the pixel region P. FIG.

In addition, a parasitic capacitor C _dp (hereinafter referred to as a first parasitic capacitor) is formed between the data line 51 and the pixel electrode 60 positioned adjacent thereto, and the first parasitic capacitor has a length of the pixel region P. Proportional to

After the pixel voltage is charged in the storage capacitor Cst provided in each pixel region P, the pixel voltage 60 of the pixel region P may vary according to the voltage variation of the data line 51.

At this time, the variation width ΔV (pixel voltage) of the pixel voltage fluctuated by one data line 51 is defined as follows.

ΔV (pixel voltage) = [ΔV (data wiring voltage) * Cdp / Cst]

On the other hand, when the array substrate 1 has a higher resolution, the pixel area becomes smaller and both the storage capacitor Cst and the first parasitic capacitor Cdp become smaller. Is much larger than the first parasitic capacitor Cdp.

Therefore, as the fringe field switching mode liquid crystal display array substrate 1 becomes higher in resolution, the variation width ΔV (pixel voltage) of the pixel voltage is increased by Cdp / Cst, so that the influence of the voltage variation of the data line 51 is greatly increased. As a result, the coupling quality between the pixel electrode 60 and the data line 51 is increased in each pixel area P, thereby degrading display quality due to cross talk.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an array substrate for a fringe field switching mode liquid crystal display device, which can improve display quality by reducing cross talk caused by coupling between a pixel electrode and a data line when high resolution is implemented. Its purpose is to provide.

An array substrate for a fringe field switching mode liquid crystal display device according to an embodiment of the present invention for achieving the above object, the substrate; A plurality of gate lines and data lines formed on the substrate to define a plurality of pixel regions crossing each other; A thin film transistor provided in each pixel area; And a pixel electrode provided in each pixel area and in contact with the drain electrode of the thin film transistor, and separated from each pixel area under the data line and having the semiconductor layer of the thin film transistor formed on the same layer. A shield pattern made of the same material is provided.

In this case, the plurality of shield connection patterns are connected to the shield pattern and are arranged side by side apart from each of the plurality of gate wires, and include a plurality of shield connection patterns made of the same material on the same layer constituting the shield pattern. It is characterized by both ends being connected.

The thin film transistor may include an interlayer insulating film having a semiconductor layer of polysilicon, a gate insulating film, a gate electrode, a semiconductor layer contact hole exposing the semiconductor layer of polysilicon, and the polysilicon through the semiconductor layer contact hole. And a stacked structure of the source electrode and the drain electrode which are in contact with and spaced apart from each other, respectively.

The thin film transistor may further include an active region made of pure polysilicon and an ohmic region made of polysilicon doped with impurities outside the active region, and the shield pattern may be the same as the ohmic region. It is characterized in that the impurity doped polysilicon, wherein the active region of the semiconductor layer of the polysilicon is formed so as to overlap with the gate wiring and the gate electrode, respectively.

The thin film transistor includes an oxide semiconductor layer made of an oxide semiconductor material, a gate insulating film having a semiconductor layer contact hole exposing the oxide semiconductor layer, a gate electrode, and the oxide semiconductor layer through the semiconductor layer contact hole. And a stacked structure of the source electrode and the drain electrode which are in contact with and spaced apart from each other.

Meanwhile, a first passivation layer including a drain contact hole exposing the drain electrode and having a flat surface made of an organic insulating material over the thin film transistor is provided, and the pixel electrode extends the drain contact hole over the first passivation layer. It is characterized in that the contact with the drain electrode through. At this time, the second protective layer formed on the front surface of the substrate above the pixel electrode; A common electrode having a plurality of first openings having a bar shape may be further provided on the second passivation layer to correspond to the pixel electrodes.

In an array substrate for a fringe field switching mode liquid crystal display device according to an embodiment of the present invention, a shield pattern overlapping the data line is provided at the boundary of each pixel region, and further, these shields are formed on the same layer using the same material as the shield pattern. A plurality of shield connection patterns are provided to connect the patterns in front of the display area, and the plurality of shield connection patterns are electrically connected to each other by having one end connected to each other in the non-display area outside the display area. When a predetermined voltage is applied in connection with a furnace or the like, the entire display area may have an equipotential.

Therefore, due to such a configuration, the array substrate for the fringe field switching mode liquid crystal display device according to the exemplary embodiment of the present invention causes the shield pattern to charge and discharge the charge in response to the change in the voltage applied to the data line. As a result of shielding and reducing or reducing the electric field, the capacity of the first parasitic capacitor having a data line and a pixel electrode adjacent thereto is finally reduced.

Furthermore, the array substrate for the fringe field switching mode liquid crystal display device according to the embodiment of the present invention has the effect of reducing the capacitance of the first parasitic capacitor and thus improving the display quality of the image by suppressing the cross talk phenomenon caused by it.

1 is a plan view of a portion of a display area of a conventional array substrate for a fringe field switching mode liquid crystal display device;
2 is a plan view of a portion of a display area in which a plurality of pixel areas are defined in an array substrate for a fringe field switching mode liquid crystal display device according to an exemplary embodiment of the present invention;
3 is a plan view illustrating only a shield pattern, a shield connection pattern, and a polysilicon semiconductor layer in an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention.
4 is a cross-sectional view of a portion taken along the line IV-IV of FIG. 2.
FIG. 5 is a cross-sectional view of a portion taken along the cutting line VV of FIG. 2. FIG.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a plan view of a portion of a display area in which a plurality of pixel areas are defined in an fringe field switching mode liquid crystal display array substrate according to an exemplary embodiment of the present invention, and FIG. 3 is a fringe field switching method according to an exemplary embodiment of the present invention. A plan view showing only a shield pattern, a shield connection pattern, and a polysilicon semiconductor layer in an array substrate for a mode liquid crystal display device.

As illustrated, the array substrate 101 for a fringe field switching mode liquid crystal display device according to an exemplary embodiment of the present invention includes a metal material having low resistance, for example, aluminum (Al), aluminum alloy (AlNd), and copper (Cu). ), A copper alloy, molybdenum (Mo), molybdenum alloy (MoTi) of any one having a single layer structure, or made of two or more materials having a multi-layer structure of more than one layer, extending in the first direction and spaced apart at regular intervals The wiring 113 is formed.

The data line 130 having a single layer or a multilayer structure made of a metal material having the above-described low resistance characteristic is formed in a second direction crossing the first direction in which the gate line 113 extends, and is spaced at regular intervals. have.

At this time, an area captured by the gate line 113 and the data line 130 that cross each other becomes the pixel area P. FIG.

Each pixel region P includes a thin film transistor Tr connected to the gate line 113 and the data line 130. In this case, the thin film transistor Tr provided in each pixel region P may include a coplanar structure by including a semiconductor layer 105 of polysilicon.

That is, the thin film transistor Tr may include a semiconductor layer 105 of polysilicon, a gate insulating layer (not shown), a gate electrode 115, and a semiconductor layer contact hole (sch) exposing the semiconductor layer 105. To form a stacked structure of an interlayer insulating film (not shown) having a semiconductor layer and source and drain electrodes 133 and 136 contacting the semiconductor layer 105 and spaced apart from each other through the semiconductor layer contact hole (sch). It is characteristic.

Next, a first passivation layer (not shown) having a flat surface is formed on the thin film transistor Tr. In this case, the thin film transistor (P) is formed in each pixel region P in the first passivation layer (not shown). A drain contact hole dch exposing the drain electrode 136 of Tr is provided.

In addition, a plate electrode is formed of a transparent conductive material on the first passivation layer (not shown) and has a plate shape for each pixel region (P).

In addition, a second protective layer (not shown) is formed on the entire surface of the substrate 101 on the pixel electrode 160, and a common electrode made of a transparent conductive material on the entire display area on the second protective layer (not shown). 170 is provided.

In this case, the common electrode 170 is provided with a plurality of first openings op1 having a bar shape corresponding to the pixel electrodes 160 provided in each pixel region P. Further, each of the thin films The second opening op2 is provided corresponding to the transistor Tr.

On the other hand, the array substrate 101 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention having such a configuration is the most characteristic, each pixel area (P) in the lower portion of each data line 130 The polysilicon overlapping the data line 130 and forming the semiconductor layer 105 is more particularly provided with a shield pattern 107 made of polysilicon doped with impurities.

The shield pattern 107 provided in each pixel region P is formed to be spaced apart from the semiconductor layer 105 as one component of the thin film transistor Tr, and has the same width as that of the data line 130. Or a larger width, and when the shield pattern 107 has a width larger than that of the data line 130, the counter substrate may be bonded to the array substrate 101 to form a display device. It is characterized in that it has a width smaller than the width of the black matrix (not shown) formed at the boundary of each pixel region P of the pixel area P (not shown) corresponding to the gate wiring 113 and the data wiring 130.

In the array substrate 101, the same layer may be formed of the same material as the shield pattern 107 penetrating through the pixel areas P and more precisely formed at the boundary of each pixel area P. A further feature is that a plurality of shield connection patterns 108 are formed on and connected to the shield pattern 107 and extend in parallel with the gate wiring 113.

The plurality of shield connection patterns 108 are formed for each pixel line defined as a plurality of pixel regions P connected to the same gate line 113, and the shield connection patterns 108 formed one for each pixel line It is characterized in that a wiring form penetrates the inside of each pixel region (P).

In addition, the plurality of shield connection patterns 108 may have a structure in which one end thereof is connected to each other in a non-display area outside the display area, so that the plurality of shield connection patterns 108 may be separated from each other by each pixel line in the display area. The ends are electrically connected to each other in the display area, and are connected to an external driving circuit to form an equipotential as a whole when the predetermined voltage is applied.

In this case, the shield pattern 107 formed to overlap the data line 130 under the data line 130 also contacts the shield connection pattern 108 and is connected to each other to form the pixel area P. The shield pattern 107 formed separately is also characterized in that it forms a substantially electrically connected state.

The formation of the shield pattern 107 made of polysilicon doped with impurities as described above under the data line 130 is coupled to the pixel electrode 160 due to the voltage variation of the data line 130. This is to suppress the.

When the shield pattern 107 made of polysilicon doped with impurities is formed at the lower portion of the shield pattern 107 overlapping with the data line 130, the shield pattern 107 made of polysilicon doped with such impurities is almost formed on the conductor. As it is close, it has the characteristics of a conductor.

Therefore, when the voltage applied to the data line 130 is changed, the shield pattern 107 charges and discharges in response to this, thereby shielding or reducing the electric field generated by the data line 130. Finally, the capacitance of the first parasitic capacitor including the data line 130 and the pixel electrode 160 adjacent thereto can be reduced.

This is explained in more detail.

In the array substrate 101 for a fringe field switching mode liquid crystal display device, a storage capacitor includes a pixel electrode 160 and a common electrode 170 overlapping each other in the pixel area P with the insulating layer interposed therebetween. The storage capacitor C _st having such a configuration has a smaller capacity in proportion to the area of the pixel region P. FIG.

When the area of the pixel region P implemented in the array substrate 101 is reduced to achieve high resolution of 300 PPI or more, the capacity of the storage capacitor provided in the pixel region P is naturally reduced.

As mentioned in the related art, after the pixel voltage is charged in the storage capacitor Cst included in each of the pixel regions P, the pixel voltage of the pixel region P may vary according to the voltage variation of the data line 130. Have

At this time, the variation width ΔV (pixel voltage) of the pixel voltage fluctuated by one data line 130 may be substantially expressed as follows.

ΔV (pixel voltage) = [ΔV (data wiring voltage) * Cdp / (Cst + Cdp + Clc + Cetc)]

(Cdp: parasitic capacitor (first parasitic capacitor) between the data wiring and the pixel electrode 160), Clc: parasitic capacitance due to the liquid crystal layer when forming the panel, Cetc: other parasitic capacitance (in this case, the thin film transistor Parasitic capacitance between gate and source and drain electrodes)

In this case, the total amount of the capacitors of one pixel region P is larger than other parasitic capacitances, that is, (Cst + Cdp + Clc + Cetc) ≒ Cst in the above equation.

Therefore, the above equation can be approximated as ΔV (pixel voltage) = [ΔV (data wiring voltage) * Cdp / Cst].

On the other hand, the array substrate 101 for the fringe field switching mode liquid crystal display device has a high pixel area, and the storage capacitor Cst and the first parasitic capacitor Cdp both become smaller when the resolution is increased. The extent is that the storage capacitor (Cst) is much larger than the first parasitic capacitor (Cdp).

Therefore, in order to maintain the above-mentioned pixel voltage fluctuation range ΔV (pixel voltage) at a low resolution array substrate level of less than 300 PPI, the capacity of the storage capacitor Cst including the pixel electrode 160 and the common electrode 170 is increased. Or to reduce the parasitic capacitance of the first parasitic capacitor Cdp.

However, in the fringe field switching mode liquid crystal display device which realizes a high resolution of 300 PPI or more, the capacity of the storage capacitor is limited. Therefore, the array substrate 101 for the fringe field switching mode liquid crystal display device according to the embodiment of the present invention is limited. It is proposed a configuration that can minimize the capacity of the parasitic capacitor (Cst).

On the other hand, in the case of the array substrate 101 for a fringe field switching mode liquid crystal display device according to an embodiment of the present invention, the thin film transistor (Tr) provided with a semiconductor layer 105 of polysilicon is described as an example, but It is not limited and may be variously modified.

In one embodiment of the present invention, the semiconductor layer 105 may include an oxide semiconductor material capable of imparting conductive properties, for example, indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), or zinc indium oxide (ZIO). The oxide semiconductor may include a thin film transistor (not shown) having a top gate structure formed of any one material and having an oxide semiconductor layer (not shown) disposed at the bottom thereof and a gate electrode (not shown) disposed thereon. The shield pattern 107 may be formed on the lower portion of the data line 130 using the same material forming a layer (not shown), and may include a shield connection pattern 108 connected thereto.

In this case, a thin film transistor (not shown) having an oxide semiconductor layer (not shown) having the top gate structure includes an oxide semiconductor layer (not shown) and a semiconductor layer contact hole exposing the oxide semiconductor layer (not shown). A source insulating layer (not shown) having a gate insulating layer (not shown), a source electrode and a drain electrode contacting the oxide semiconductor layer (not shown) and spaced apart from each other through a gate electrode (not shown) and the semiconductor layer contact hole (sch) It has a laminated structure (not shown).

Table 1 shows the capacity of the storage capacitor and the first parasitic capacitor of the conventional fringe field switching mode liquid crystal display array substrate having a resolution of 440 PPI and the fringe field switching mode liquid crystal display array substrate according to the embodiment of the present invention. Each shows the results of simulation using tekwiz.

Conventional Embodiment of the present invention Cdp (first parasitic capacitor) in F 7.85E-16 4.84-16 Cst (Storage Capacitor) in F 7.32E-14 7.33E-14 Cst / Cdp 93.2 151.4

Referring to Table 1, it can be seen that the capacity of the storage capacitor Cst is the same level as the array substrate having the same resolution.

However, the capacitance of the first parasitic capacitor Cdp generated between the data line 130 and the pixel electrode 160 is 7.85 * 10 ^-16 F in the case of the conventional array substrate, whereas in the embodiment of the present invention, It can be seen that according to the array substrate is 4.84 * 10 ^-16 F.

That is, it can be seen that the capacity of the first parasitic capacitor Cdp generated in each pixel area P of the array substrate according to the embodiment of the present invention is reduced by about 61% compared to the conventional array substrate.

Hereinafter, a cross-sectional structure of an array substrate for a fringe field switching mode liquid crystal display device according to an exemplary embodiment of the present invention having the above-described configuration will be described.

4 is a cross-sectional view of a portion taken along the cutting line IV-IV of FIG. 2, and FIG. 5 is a cross-sectional view of a portion taken along the cutting line V-V of FIG. 2. In this case, for convenience of description, a portion where the thin film transistor is formed is defined as a switching region TrA.

 As shown, a polysilicon semiconductor layer 105 is formed in an island shape in the switching region TrA on the front surface of the transparent insulating substrate 101, for example, on a glass substrate or a plastic substrate.

At this time, although not shown in the drawing, a buffer layer (not shown) made of an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is disposed under the semiconductor layer 105 of the polysilicon. It may be further provided to.

The buffer layer (not shown) is an alkali ion, for example, potassium ions (K +), sodium ions, present in the substrate 101 due to heat generated during laser irradiation or heating when amorphous silicon is crystallized with polysilicon. Na +) may be generated to prevent the film properties of the semiconductor layer 105 made of polysilicon from being deteriorated by such alkali ions.

In this case, the buffer layer (not shown) does not necessarily need to be formed, and may be omitted depending on what material the substrate 101 is made of.

In the drawings, the buffer layer (not shown) is omitted as an example.

On the other hand, the semiconductor layer 105 of the polysilicon is formed overlapping with the data line 130, the first portion crossing the gate line 113 and the first portion bent from the first portion overlapping with the gate electrode 115 It is characterized by one part.

In this case, the portion of the semiconductor layer 105 of the polysilicon overlapping with the gate wiring 113 and the gate electrode 115 is made of pure polysilicon to form the active regions 105a and 105b. It is characterized by forming the ohmic region 105c by being doped with impurities.

The polysilicon semiconductor layer 105 is formed to be bent as described above to have a form overlapping with the gate wiring 113 and the gate electrode 115a to achieve a double gate electrode structure.

On the other hand, in the case of the thin film transistor Tr having the semiconductor layer 105 of polysilicon, the mobility characteristics are several times to several hundred times better than those of the thin film transistor having the semiconductor layer of amorphous silicon. ) Tends to be large, and the double gate electrodes 115a and 115b are structured as described above in order to suppress the phenomenon in which the off current Ioff increases.

However, the semiconductor layer 105 of the polysilicon does not necessarily have to be bent to overlap the gate wiring 113 and the gate electrode, but may be formed to form a single gate structure.

Next, the most characteristic configuration of the array substrate 101 for a fringe field switching mode liquid crystal display device according to an exemplary embodiment of the present invention corresponds to a portion where the data line 130 is formed more precisely at the boundary of each pixel region P. FIG. Thus, a shield pattern 107 is formed between the pixel regions P adjacent to each other up and down, spaced apart from the semiconductor layer 105 of the polysilicon, and having a bar shape.

The shield pattern 107 is made of polysilicon, which is the same material constituting the semiconductor layer 105 of polysilicon, and is doped with impurities such as an ohmic region 105b provided in the semiconductor layer 105 of polysilicon. It is a characteristic that the characteristic of a conductor was further given.

In addition, the pixel line (P) penetrates the plurality of pixel regions (P) connected to each of the pixel lines (ie, one gate line 113) and is spaced apart from the gate line (113) to be parallel to the pixel regions (P). The shield connection pattern 108 for electrically connecting the shield pattern 107 is formed at a predetermined interval apart.

The shield connection pattern 108 is made of the same material as the shield pattern 107 and is characterized in that one end is connected to each other in a non-display area outside the display area.

Next, an inorganic insulating material, such as silicon oxide (SiO ₂ ) or nitride, is formed on the entire surface of the substrate 101 over the semiconductor layer 105, the shield pattern 107, and the shield connection pattern 108 of the polysilicon having such a configuration. A gate insulating layer 110 made of silicon (SiNx) is formed.

In addition, any one of a metal material having low resistance on the gate insulating layer 110, for example, aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), and molybdenum alloy (MoTi) The gate wiring 113, which is one component that defines the pixel region P, extends in the first direction and has a predetermined interval. Spaced apart and formed in large numbers.

In the switching region of each pixel region P, a first gate electrode 115a formed by branching from the gate line 113 is formed.

 Each of the gate wires 113 is a part of itself, more specifically, a portion of the gate wires 113 intersecting with the data wires 130 forms the second gate electrode 115b.

In this case, the first active region 105a of the first portion of the semiconductor layer 105 of the polysilicon overlaps the first gate electrode 115a, and the active region 105b of the second portion may be formed of the first portion. The structure overlaps with the 2 gate electrode 115b.

Next, an interlayer insulating layer 120 made of an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is formed on the entire surface of the substrate 101 over the gate wiring 113.

In this case, the interlayer insulating layer 120 is provided with a semiconductor layer contact hole (sch) that exposes the ohmic region 105c of the polysilicon semiconductor layer 105 to each switching region TrA.

The plurality of pixel regions P together with the gate wiring 113 are defined to extend in a second direction crossing the first direction on the interlayer insulating layer 120 having the semiconductor layer contact hole sch. A plurality of data lines 130 having a single layer or a multilayer structure made of a metal material are spaced apart at regular intervals.

In addition, each switching region TrA contacts the ohmic region 105c and is spaced apart from each other through a semiconductor layer contact hole Sch that exposes the ohmic region 105c of the semiconductor layer 105 of polysilicon. The electrode 133 and the drain electrode 136 are formed.

In this case, the source electrode 133 is formed as a part of the data line 130 itself, and the drain electrode 136 is formed in each switching region TrA in an island form spaced apart from the source electrode 136. have.

On the other hand, an interlayer including the semiconductor layer 105 of the polysilicon, the gate insulating layer 110, the gate electrodes 115a and 115b, and the semiconductor layer contact hole (sch) sequentially stacked in each switching region TrA. The insulating layer 120 and the source and drain electrodes 133 and 136 spaced apart from each other form a thin film transistor Tr, which is a switching element.

Next, a first passivation layer 140 is formed on an entire surface of the display area over the data line 130 and the thin film transistor Tr, and is formed of an organic insulating material, for example, photoacryl, and has a flat surface.

In this case, the first protective layer 140 is provided with a drain contact hole dch exposing the island-type drain electrode 136 provided in each switching region TrA.

The drain contact hole dch is formed to overlap the semiconductor layer contact hole (sch) provided in the interlayer insulating layer 120 so that the drain electrode 136 and the polysilicon semiconductor layer 105 are in contact with each other. It is characterized by being. This is to improve the aperture ratio of the pixel region P. The drain contact hole dch does not necessarily need to overlap the semiconductor layer contact hole sch.

Next, the thin film transistor Tr is disposed on the first passivation layer 140 having the drain contact hole dch in each switching region TrA through the drain contact hole dch in each pixel region P. Referring to FIG. In contact with the drain electrode 136, a plate-shaped pixel electrode 160 made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed.

A second protective layer 165 made of an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is disposed on the entire surface of the substrate 101 on the pixel electrode 160.

In addition, a common electrode 170 made of a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), is disposed on the entire display area over the second passivation layer 165.

In this case, the common electrode 170 is provided with a plurality of first openings op1 having a bar shape corresponding to each pixel electrode 160 provided in each pixel region P. The second opening op2 is provided corresponding to each thin film transistor Tr.

In the array substrate 101 for the fringe field switching mode liquid crystal display device having the above configuration, the shield pattern 107 overlapping the data line 130 is formed at the boundary of each pixel region P. As shown in FIG. Furthermore, a plurality of shield connection patterns 108 are provided to connect the shield patterns 107 on the same layer with the same material as the shield pattern 107 on the front of the display area, and the plurality of shield connection patterns 108 are provided. In the non-display area outside the display area, one end of the display area is electrically connected to each other, and when the predetermined voltage is applied to an external driving circuit, the entire display area may be equipotential.

Therefore, the shield pattern 107 reacts when the voltage applied to the data line 130 is changed in the array substrate 101 for the fringe field switching mode liquid crystal display according to the exemplary embodiment of the present invention. Charges and discharges charges to shield and suppress or reduce the electric field generated by the data wires 130, and finally the first wires having the data wires 130 and the pixel electrodes 160 adjacent thereto as components. The capacitance of the parasitic capacitor Cdp can be reduced.

Furthermore, since the capacitance of the first parasitic capacitor Cdp is thus reduced, the cross talk phenomenon due to this is suppressed, thereby improving the display quality of the image.

The present invention is not limited to the above-described embodiments and modifications, and various changes and modifications can be made without departing from the spirit of the present invention.

101: array substrate
107: shield pattern
108: shield connection pattern
110: gate insulating film
120: interlayer insulating film
130: data wiring
140: first protective layer
160: pixel electrode
165: second protective layer
170: common electrode
P: pixel area

Claims (9)

A substrate;
A plurality of gate lines and data lines formed on the substrate to define a plurality of pixel regions crossing each other;
A thin film transistor provided in each pixel area;
A pixel electrode provided in each pixel area and in contact with the drain electrode of the thin film transistor,
An array substrate for a fringe field switching mode liquid crystal display device having a shield pattern made of the same material as that of the semiconductor layer is provided on the same layer in which the semiconductor layer of the thin film transistor is formed below the data line. .
The method of claim 1,
And a plurality of shield connection patterns connected to the shield patterns and spaced apart from each of the plurality of gate lines, and having a plurality of shield connection patterns made of the same material on the same layer forming the shield pattern.
The method of claim 2,
And a plurality of shield connection patterns are connected at one end of the plurality of shield connection patterns.
The method of claim 1,
The thin film transistor,
An interlayer insulating film having a semiconductor layer of polysilicon, a gate insulating film, a gate electrode, a semiconductor layer contact hole exposing the semiconductor layer of polysilicon, and a semiconductor layer of the polysilicon through the semiconductor layer contact hole, respectively. An array substrate for a fringe field switching mode liquid crystal display device comprising a stacked structure of a source electrode and a drain electrode contacting and spaced apart from each other.
The method of claim 4, wherein
The thin film transistor,
The semiconductor layer of polysilicon includes an active region made of pure polysilicon and an ohmic region made of polysilicon doped with impurities outside the active region, and the shield pattern is made of polysilicon doped with impurities like the ohmic region. An array substrate for a fringe field switching mode liquid crystal display device.
The method of claim 5,
And wherein the active region of the polysilicon semiconductor layer overlaps the gate line and the gate electrode, respectively.
The method of claim 1,
The thin film transistor,
A gate insulating film having an oxide semiconductor layer made of an oxide semiconductor material and a semiconductor layer contact hole exposing the oxide semiconductor layer, a gate electrode, and a contact between the oxide semiconductor layer and a spaced apart from each other through the semiconductor layer contact hole An array substrate for a fringe field switching mode liquid crystal display device comprising a stacked structure of a source electrode and a drain electrode.
The method according to any one of claims 1 to 7,
A first passivation layer including a drain contact hole exposing the drain electrode and having a flat surface formed of an organic insulating material over the thin film transistor is provided, and the pixel electrode is disposed on the first passivation layer through the drain contact hole. An array substrate for a fringe field switching mode liquid crystal display device, wherein the liquid crystal display contacts the drain electrode.
The method of claim 8,
A second passivation layer formed over an entire surface of the substrate over the pixel electrode;
An array substrate for a fringe field switching mode liquid crystal display device further comprising a common electrode having a plurality of bar-shaped first openings corresponding to the pixel electrodes on the second passivation layer.

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