KR102022658B1 - Semiconductor device having insulation structure and method of fabricating the same - Google Patents

Abstract

Disclosed are a semiconductor device having an insulating structure and a method of manufacturing the same. This semiconductor element comprises a substrate; A gallium nitride based semiconductor laminate positioned on the substrate; And an insulating structure positioned between the substrate and the semiconductor laminate to insulate the semiconductor laminate from the substrate. The insulating structure may further include a mask pattern having a mask region and an opening region; And a cavity located in the opening region of the mask pattern. Accordingly, the semiconductor laminate may be electrically insulated from the substrate by the mask pattern and the cavity.

Description

A semiconductor device having an insulating structure and a method of manufacturing the same {SEMICONDUCTOR DEVICE HAVING INSULATION STRUCTURE AND METHOD OF FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and to a semiconductor device having an insulating structure that insulates a semiconductor laminate from a substrate and a method of manufacturing the same.

Gallium nitride compound semiconductors are used in visible and ultraviolet light emitting devices, high power electronic devices and the like. A gallium nitride compound semiconductor layer is usually grown on a substrate using a growth technique such as MBE, MOCVD or HVPE.

In general, gallium nitride compound semiconductors are grown on heterogeneous substrates, such as sapphire substrates. The semiconductor laminate is grown on a sapphire substrate, and various semiconductor devices can be manufactured using the semiconductor laminate.

Recently, a light emitting device in which a plurality of semiconductor laminates are connected in series on a single substrate using a wiring to drive at high voltage has been used. Such a light emitting element is generally formed using a sapphire substrate which is an insulating substrate as a growth substrate. Thus, electrical isolation between semiconductor stacks can be achieved relatively easily by patterning the semiconductor layers grown on the growth substrate to expose the substrate.

However, semiconductor laminates grown on sapphire substrates have a relatively high crystal defect density. Furthermore, gallium nitride compound semiconductors grown in the C-axis direction on a sapphire substrate having a c plane as a growth plane exhibit polarity due to spontaneous polarization and piezoelectric polarization, and thus, the recombination rate of electrons and holes is lowered, thereby limiting the improvement in luminous efficiency. have.

In order to overcome the limitation of the sapphire substrate, recently, a technique for growing a gallium nitride compound semiconductor using a gallium nitride substrate as a growth substrate has been developed. Since a gallium nitride substrate, which is a homogeneous substrate, is used as a growth substrate, the crystal defect density can be significantly reduced. Furthermore, when a nonpolar or semipolar gallium nitride substrate is used as a growth substrate, it is possible to grow a nonpolar or semipolar gallium nitride compound semiconductor having good crystal quality, thereby solving the problem due to polarization.

However, gallium nitride substrates have electrical conductivity unlike sapphire substrates. Even if a gallium nitride substrate having a relatively high resistance is manufactured by controlling a method of manufacturing a gallium nitride substrate, current leakage through the gallium nitride substrate cannot be ignored because the gallium nitride substrate is very thick compared to the semiconductor laminate. Therefore, in order to connect a plurality of semiconductor laminates in series on an electrically conductive substrate such as a gallium nitride substrate, it is necessary to insulate the plurality of semiconductor laminates and the substrate.

To insulate the gallium nitride substrate and the semiconductor laminate, a gallium nitride based semi-insulating layer doped with p-type impurities may be used. However, counter-doping p-type impurities has a limit in forming a uniform insulating layer. Moreover, since the semi-insulating layer does not completely block the current, leakage of current through the semi-insulating layer can easily occur.

An object of the present invention is to provide a semiconductor device having a novel insulating structure capable of insulating a semiconductor laminate from a substrate, and a method of manufacturing the same.

Another object of the present invention is to provide a semiconductor device capable of blocking current leakage from a semiconductor laminate to a substrate and a method of manufacturing the same.

Another object of the present invention is to provide a semiconductor device, in particular a light emitting device, having a plurality of semiconductor laminates connected in series with a GaN substrate as a growth substrate.

According to one aspect of the present invention, a semiconductor device includes: a substrate; A gallium nitride based semiconductor laminate positioned on the substrate; And an insulating structure positioned between the substrate and the semiconductor laminate to insulate the semiconductor laminate from the substrate. The insulating structure may include a mask pattern having a mask region and an opening region; And a cavity positioned in the opening region of the mask pattern. Accordingly, the semiconductor laminate may be electrically insulated from the substrate by the mask pattern and the cavity.

The semiconductor device may further include a gallium nitride-based sacrificial layer disposed between the insulating structure and the substrate. In addition, a portion of the cavity may be located between the mask region and the sacrificial layer. Meanwhile, the sacrificial layer may have a Si doping concentration within the range of 1E17 / cm ³ to 1E19 / cm ³ . Thus, the semiconductor laminate is electrically insulated from the sacrificial layer by the mask pattern and the cavity, and as a result, electrically insulated from the substrate.

The substrate is not particularly limited as long as it is a substrate capable of growing a gallium nitride series semiconductor layer. The present invention is particularly useful when the substrate is conductive, but may also be applied when the substrate is non-conductive. In particular, the substrate may be a polar, nonpolar or semipolar gallium nitride substrate.

The mask pattern may be formed of an insulating material, for example, SiO ₂ , SiN, MgO, TaO, TiO _2, or a combination thereof.

The mask pattern may be an embossed pattern in which the mask area has a specific shape or an intaglio pattern in which the opening area has a specific shape. For example, the mask area may have a stripe, circle, rectangle, rhombus, or hexagon shape, or the opening area may have a circle, rectangle, rhombus, or hexagon shape.

The semiconductor device may be a light emitting device, but the present invention is not limited to the light emitting device. It can also be applied to various electronic devices utilizing semiconductor laminates that are electrically insulated from the substrate.

Meanwhile, a plurality of semiconductor stacks may be located on the substrate, and the insulating structure may be located between the substrate and the plurality of semiconductor stacks. Thus, the plurality of semiconductor laminates are electrically insulated from the substrate.

The semiconductor device may further include at least one wiring that connects the plurality of semiconductor laminates in series. Thus, a series array of semiconductor stacks driven under high voltage can be formed.

In some embodiments, an insulating layer may be interposed between the wiring and the substrate to insulate the wiring from the substrate. In addition, the insulating layer may cover the side surface of the semiconductor laminate to prevent the semiconductor laminates from being shorted by the wiring.

In example embodiments, the semiconductor device may further include a separation mask positioned at the same level as the mask pattern between the plurality of semiconductor stacks. The separation mask is positioned under the wiring and insulates the wiring from the substrate. In addition, the separation mask may be formed of the same material as the mask pattern.

According to another aspect of the present invention, a semiconductor device manufacturing method having a growth substrate and a semiconductor laminate insulated from the growth substrate is provided. This method comprises preparing a growth substrate; Forming a sacrificial layer and a mask pattern on the growth substrate, wherein the mask pattern has a mask region and an opening region, and the sacrificial layer is exposed to the opening region of the mask pattern; Etching the sacrificial layer using electrochemical etching (ECE); Growing a gallium nitride based semiconductor laminate covering the mask pattern.

By using electrochemical etching, a cavity may be formed in the sacrificial layer, and thus the semiconductor laminate may be electrically insulated from the growth substrate by a mask pattern and a cavity.

The mask pattern may be formed on the sacrificial layer.

In some embodiments, a cavity may be formed in the sacrificial layer while forming the semiconductor laminate. However, the present invention is not limited thereto, and a cavity may be formed in the sacrificial layer before forming the semiconductor laminate.

The sacrificial layer is 1E17 / cm ³ to 1E19 / cm ³ may be a semiconductor layer of GaN-based having a Si doping concentration in the range of, preferably, 1E18 / cm ³ or more, more preferably 3E18 / cm ³ or more Si doping concentration It can have

In some embodiments, the sacrificial layer may be partially etched by applying a voltage of one step. In other embodiments, the sacrificial layer may be partially etched by applying at least two levels of voltage, wherein the first applied voltage is lower than the later applied voltage. As a result, relatively small micropores are formed on the surface of the sacrificial layer, so that the surface maintains relatively good crystallinity, and relatively large micropores are generated inside the sacrificial layer.

In some embodiments, the semiconductor device manufacturing method may further include forming a plurality of semiconductor laminates separated from each other by patterning the grown gallium nitride based semiconductor laminate. Accordingly, a plurality of semiconductor laminates electrically insulated from the growth substrate can be manufactured on the growth substrate. Furthermore, the method of manufacturing a semiconductor device may further include forming at least one wiring electrically connecting the plurality of semiconductor laminates separated from each other.

In other embodiments, the method of manufacturing the semiconductor device may further include forming a separation mask that separates the mask pattern into a plurality of regions before growing the gallium nitride based semiconductor laminate. The gallium nitride based semiconductor laminates are grown to be spaced apart from each other on the separation mask. As a result, a plurality of semiconductor laminates are formed by the separation mask, and thus a patterning process for separating the grown semiconductor laminates can be omitted.

In addition, the separation mask may be formed together while forming the mask pattern. Therefore, the separation mask may be formed of the same material as the mask material of the mask pattern.

Meanwhile, the method of manufacturing a semiconductor device may further include forming at least one wiring electrically connecting a plurality of semiconductor laminates spaced apart from each other.

According to embodiments of the present invention, the semiconductor laminate may be insulated from the substrate by using a mask pattern and a cavity. Current leakage from the semiconductor laminate to the substrate can be blocked by the mask pattern and the cavity. Accordingly, a semiconductor device, in particular a light emitting device, having a plurality of semiconductor laminates connected in series with each other while using a substrate having an electrical conductivity such as a GaN substrate as a growth substrate can be provided.

Furthermore, a GaN substrate can be used as a growth substrate, and thus a semiconductor laminate having good crystal quality can be grown, and thus a light emitting device having high efficiency can be provided. Moreover, nonpolar or semipolar semiconductor laminates can be used to overcome the light efficiency limitations due to polarization.

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.
2 and 3 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
4 to 6 are plan views illustrating mask patterns according to embodiments of the present invention, respectively.
7 is a cross-sectional view illustrating a semiconductor device in accordance with still another embodiment of the present invention.
8 and 9 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.
10 is an SEM photograph showing a cavity formed by using electrochemical etching.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to ensure that the spirit of the present invention can be fully conveyed to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, the same reference numerals denote the same components, and the width, length, thickness, etc. of the components may be exaggerated for convenience.

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1, the semiconductor device includes a substrate 110, an insulating structure 140, and a semiconductor laminate 200. Furthermore, the semiconductor device may further include a sacrificial layer 120, a transparent electrode 190, an insulating layer 210, and a wiring 220.

The substrate 110 is not particularly limited as long as it is a growth substrate used for growing a gallium nitride based semiconductor layer. In particular, the substrate 110 may be a substrate having electrical conductivity such as a gallium nitride substrate, a silicon substrate, or a SiC substrate. However, the present invention is not necessarily limited to that the substrate 110 is electrically conductive, and the substrate 110 may be an insulating substrate such as a sapphire substrate.

Substrate 110 may in particular be a gallium nitride substrate, in which case the gallium nitride substrate is a polar substrate having a c-plane growth plane, a nonpolar substrate having a non-polar growth plane such as a plane or m plane, or (20-21) , (20-2-1), (10-11), (10-1-1), (11-22), (11-2-2), (30-31), (30-3-1) It may be a semipolar substrate having a semipolar growth surface such as.

The semiconductor laminate 200 is positioned on the substrate 110. As illustrated in FIG. 1, a plurality of semiconductor stacks 200 may be separated from each other by a cell isolation region 200a on a single substrate 110. The semiconductor laminate 200 may include gallium nitride-based semiconductor layers, and in particular, may include a first nitride semiconductor layer 160, an active layer 170, and a second nitride semiconductor layer 180.

The first nitride semiconductor layer 160 is a nitride semiconductor layer doped with a first conductivity type impurity, for example, a III-N type compound semiconductor doped with n-type impurity, such as (Al, In, Ga) N-based nitride It may be formed of a semiconductor layer, it may include a gallium nitride layer. In addition, the first nitride semiconductor layer 160 may include an undoped layer that is not intentionally doped with impurities.

The active layer 170 may be formed of a III-N-based compound semiconductor, for example, an (Al, Ga, In) N semiconductor layer, and a single quantum well structure or a well layer (not shown) and a barrier layer (not shown) are alternated. It may be a multi-quantum well structure stacked with.

The second nitride semiconductor layer 180 includes a III-N-based compound semiconductor doped with a second conductivity type impurity, such as a P-type impurity, for example, an (Al, Ga, In) N-based group III nitride semiconductor layer. For example, it may include a GaN layer.

On the other hand, the insulating structure 140 is positioned between the substrate 110 and the semiconductor laminate 200 to electrically insulate the semiconductor laminate 200 from the substrate 110. The insulating structure 140 may electrically insulate the plurality of semiconductor laminates 200 from the substrate 110.

The insulating structure 140 includes a mask pattern 130 having a mask region and an opening region and a cavity 150a positioned in the opening region of the mask pattern 130. The mask pattern 130 may be an embossed pattern or an engraved pattern. For example, the mask area of the mask pattern 130 may have a specific shape such as a stripe shape, a circle, a rectangle, a rhombus, and a hexagon. Alternatively, the opening region of the mask pattern 130 may have a specific shape such as a circle, a rectangle, a rhombus, or a hexagon.

The mask pattern 130 is formed using an insulating material. Such an insulating material may be formed of, for example, SiO ₂ , SiN, MgO, TaO, TiO _2, or a combination thereof.

The cavity 150a is electrically insulating as an empty space. The cavity 150a is formed in the entire opening region of the mask pattern 130 positioned in the lower region of the semiconductor stack 200. Therefore, the semiconductor laminate 200 is electrically insulated from the substrate 110 by the mask region of the mask pattern 130 and the cavity 150a. As illustrated in FIG. 1, the cavity 150a may be positioned below the level at which the mask pattern 130 is located, and may be positioned below the mask region so that a part thereof overlaps with the mask region. Thus, the bottom surface of the mask area may be exposed to the cavity 150a.

In the present exemplary embodiment, although the cavity 150a is positioned below the mask pattern 130 and the side surface of the mask pattern 130 is covered by the first nitride semiconductor layer 160, the mask pattern 130 may be formed. The side may be exposed to the cavity 150a.

The sacrificial layer 120 may be located between the insulating structure 140 and the substrate 110. That is, the insulating structure 140 may be located on the sacrificial layer 120. The sacrificial layer 120 may be formed of a gallium nitride based semiconductor, such as GaN, having a Si doping concentration within the range of 1E17 / cm ³ to 1E19 / cm ³ . The sacrificial layer 120 may have a preferably, 1E18 / cm ³ or more, more preferably 3E18 / cm ³ or more Si doping concentration.

The cavity 150a is positioned on the top surface of the sacrificial layer 120 to electrically insulate the first conductivity-type semiconductor layer 160 from the sacrificial layer 120, and consequently, to electrically insulate the substrate 110.

The cell isolation region 200a separates the semiconductor stack 200 into a plurality of cell regions. The cell isolation region 200a may separate the sacrificial layer 120 as well as the semiconductor stack 200. In this embodiment, two semiconductor laminates 200 are shown, but the present invention is not limited to two semiconductor laminates 200, and two or more further separated by cell isolation regions 200a. Many semiconductor stacks 200 may be included.

Meanwhile, one or more wires 220 may electrically connect the semiconductor stacks 200 separated from each other. As illustrated in FIG. 1, the wiring 220 may connect the semiconductor stacks 200 in series. That is, one end of the wiring 220 is electrically connected to the first nitride semiconductor layer 160 of one semiconductor laminate 200, and the other end of the wiring 220 is the second nitride semiconductor of the other semiconductor laminate 200. It may be electrically connected to layer 180. In this way two or more more semiconductor stacks 200 can be electrically connected, so a series array can be provided on a single substrate 110 that can be driven under a high voltage of a desired voltage.

The transparent electrode layer 190 may be positioned on the semiconductor laminate 200, for example, on the second nitride semiconductor layer 180. The transparent electrode layer 190 may be in electrical contact with the second nitride semiconductor layer 180, and one end of the wiring 220 may be connected to the transparent electrode layer 190.

Meanwhile, an insulating layer 210 may be interposed between the semiconductor laminate 200 and the wiring 220 to prevent a short circuit between the wiring 220 and the semiconductor laminate 200. The insulating layer 210 may also be interposed between the wiring 220 and the substrate 110 to prevent shorting of the wiring 220 and the substrate 110.

According to the present embodiment, an insulating structure 140 capable of electrically insulating the semiconductor laminate 200 from the growth substrate 110 is provided. Therefore, even when a conductive substrate such as a gallium nitride substrate is used as the growth substrate, electrical insulation between the semiconductor laminate 200 and the substrate 110 can be achieved. Accordingly, the leakage current flowing from the semiconductor stack 200 to the substrate 110 can be blocked, and as a result, a light emitting device capable of driving under high voltage by connecting a plurality of semiconductor stacks in series can be provided.

2 and 3 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

First, referring to FIG. 2A, a growth substrate 110 is prepared. The growth substrate 110 may be a sapphire substrate, a GaN substrate, a silicon carbide (SiC) substrate, a silicon (Si) substrate, or the like. In particular, the growth substrate 110 may be a polar, nonpolar, or semipolar GaN substrate.

The sacrificial layer 120 is formed on the growth substrate 110. The sacrificial layer 120 may be grown on the growth substrate 110 using, for example, metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The sacrificial layer 120 may have an impurity concentration within the range of 1E17 / cm ³ to 1E19 / cm ³ . The sacrificial layer 120 may be preferably 1E18 / cm ³ or more, more preferably 3E18 / cm ³ or more Si-doped gallium nitride, for example, a GaN layer. The nitride-based semiconductor layers described below may be grown by using MOCVD or MBE technology, like the sacrificial layer 120, and the description thereof is not described.

Referring to FIG. 2B, a mask pattern 130 is formed on the sacrificial layer 120. The mask pattern 130 may be formed of an insulating material, for example, SiO ₂ , SiN, MgO, TaO, TiO _2, or a combination thereof. As shown in FIG. 4A, the mask pattern 130 may have a stripe shape, and as shown in FIG. 4B, stripes extending in different directions may cross each other. Can have In contrast, the mask pattern 130 is an embossed pattern, and as shown in FIG. 5A, the mask region may have a hexagonal shape, or as shown in FIG. 6A, the mask region may be It may have a rhombus shape. Alternatively, the mask pattern 130 is an intaglio pattern, and as shown in FIG. 5B, the opening region may have a hexagonal shape, or as shown in FIG. 6B, the opening region may be formed. It may have a rhombus shape. The mask pattern 130 may also be an embossed pattern in which the mask area is circular or rectangular, or an intaglio pattern in which the opening area is circular or rectangular.

Referring to FIG. 2C, the sacrificial layer 120 is partially etched using electrochemical etching (ECE) to form micropores 150 in the sacrificial layer 120.

In the electrochemical etching process, the growth substrate 110 and the cathode electrode (eg, Pt electrode) on which the sacrificial layer 120 is formed are immersed in an ECE solution, and then a positive voltage is applied to the sacrificial layer 120 and a negative electrode is applied to the cathode electrode. It is performed by applying a voltage of the, it is possible to adjust the size of the micro-pores 150 by adjusting the molar concentration, the process time and the applied voltage of the ECE solution.

The ECE solution may be an electrolyte solution, for example, an electrolyte solution including oxalic acid, HF or NaOH.

In the present embodiment, the sacrificial layer 120 may be partially etched by one-step electrochemical etching (ECE) that continuously applies the same voltage, for example, a voltage in the range of 10 to 60V. However, the present invention is not limited thereto, and may be partially etched by two-step electrochemical etching (ECE) that initially applies a relatively low voltage and then applies a relatively high voltage. FIG. 2 (c) shows micropores 152 and 154 formed by two-step electrochemical etching, and micropores 152 are formed in one step of applying a relatively low voltage, and relatively large micropores. 154 is formed in two steps of applying a relatively high voltage. For example, the sacrificial layer 120 having a Si doping concentration of 6E18 / cm ³ using a 0.3M oxalic acid solution at 20 ° C. was applied at a voltage of 8 to 9 V in the first step and 15 to 17 V in the second step. The electrochemical etching may be performed by applying a voltage of.

By using a two-step electrochemical etching, the surface of the sacrificial layer 120 can maintain relatively good crystallinity, and can also form relatively large micropores 154 inside the sacrificial layer 120. It is advantageous for the subsequent process.

Referring to FIG. 2D, a nitride semiconductor laminate including a first nitride semiconductor layer 160, an active layer 170, and a second nitride semiconductor layer 180 using the sacrificial layer 120 as a seed ( 200) is grown. The nitride semiconductor laminate 200 covers the mask pattern 130 as well as the sacrificial layer 120 by horizontal growth.

The first nitride semiconductor layer 160 may be a single layer, but is not limited thereto and may be a multilayer. Such multilayers may include an undoped layer and a doped layer.

Meanwhile, during the growth of the semiconductor stack 200, the micropores 152 and 154 merge with each other and grow to form a cavity 150a. The cavity 150a is formed to electrically separate the sacrificial layer 120 and the first nitride semiconductor layer 160 in the opening region of the mask pattern 130. In FIG. 2D, a portion of the sacrificial layer 120 may remain on the cavity 150a. Alternatively, all of the portions of the sacrificial layer 120 on the cavity 150a may be removed.

Referring to FIG. 3A, as described above, during the formation of the semiconductor stack 200, the voids 152 and 154 in the sacrificial layer 120 are formed in the sacrificial layer 120 by the micropores 152 and 154. 150a) is formed. Here, FIG. 3 (a) shows the same process steps as FIG. 2 (d) and is simply expressed by different scales.

The first nitride semiconductor layer 160 is a nitride semiconductor layer doped with a first conductivity type impurity, for example, a III-N type compound semiconductor doped with n-type impurity, such as (Al, In, Ga) N-based nitride It may be formed of a semiconductor layer, it may include a gallium nitride layer. In addition, the first nitride semiconductor layer 160 may include an undoped layer that is not intentionally doped with impurities.

The active layer 170 may be formed of a III-N-based compound semiconductor, for example, an (Al, Ga, In) N semiconductor layer, and a single quantum well structure or a well layer (not shown) and a barrier layer (not shown) are alternated. It may be a multi-quantum well structure stacked with.

The second nitride semiconductor layer 180 includes a III-N-based compound semiconductor doped with a second conductivity type impurity, such as a P-type impurity, for example, an (Al, Ga, In) N-based group III nitride semiconductor layer. For example, it may include a GaN layer.

Referring to FIG. 3B, a cell isolation region 200a is formed by patterning the grown nitride semiconductor stack 200. The cell isolation region 200a may be formed using a photolithography and an etching process. A plurality of nitride semiconductor stacks 200 separated into a plurality of cell regions are formed by the cell isolation region 200a.

Meanwhile, as shown, the cell isolation region 200a may also separate the sacrificial layer 120, and thus the surface of the substrate 110 may be exposed to the cell isolation region 200a.

In addition, the second nitride semiconductor layer 180 and the active layer 170 of each semiconductor laminate 200 are partially etched to partially expose the top surface of the first nitride semiconductor layer 160. The process of exposing the top surface of the first nitride semiconductor layer 160 may be performed before or after forming the cell isolation region 200a.

Referring to FIG. 3C, a transparent electrode layer 190 may be formed on the second nitride semiconductor layer 180. The transparent electrode layer 190 may be formed of a transparent oxide such as ITO or a metal layer such as Ni / Au.

In the present embodiment, it is described that the transparent electrode layer 190 is formed after the semiconductor laminate 200 is separated and the upper surface of the first nitride semiconductor layer 160 is partially exposed. It may be formed before the semiconductor laminate 200 is separated, or may be formed before exposing the upper surface of the first nitride semiconductor layer 160.

Meanwhile, an insulating layer 210 may be formed to cover side surfaces of the semiconductor stacks 200. The insulating layer 210 may also cover the exposed surface of the substrate 110 and may cover a portion of the transparent electrode layer 190. However, the insulating layer 210 is formed to expose at least a portion of the upper surface of the first nitride semiconductor layer 160 and at least a portion of the upper surface of the transparent electrode layer 190.

Referring to FIG. 3 (d), the wiring 220 connecting the semiconductor stacks 200 to each other in series is formed. The wiring 220 is formed on the insulating layer 210 to be insulated from the side surfaces of the semiconductor stacks 200 and is also insulated from the substrate 110. One end of the wiring 220 is electrically connected to the first nitride semiconductor layer 160 of one semiconductor laminate 200, and the other end thereof is the second nitride semiconductor layer of the other semiconductor laminate 200 ( 180 is electrically connected.

The plurality of semiconductor stacks 200 may be variously connected by the wirings 220. Accordingly, various wirings of the plurality of semiconductor stacks 200 may be formed on the single substrate 110, such as series connection, parallel connection, anti-parallel connection, or serial / parallel mixed connection. The semiconductor device having the plurality of semiconductor stacks 200 may be manufactured by dividing the substrate 110 to include the plurality of semiconductor stacks 200.

In the present embodiment, a method of fabricating a semiconductor device having a plurality of semiconductor stacks 200 on a single substrate 110 has been described. However, the present embodiment can also be applied to manufacturing a semiconductor device having a single semiconductor stack 200 on the substrate 110.

7 is a cross-sectional view illustrating a semiconductor device in accordance with still another embodiment of the present invention.

Referring to FIG. 7, the semiconductor device according to the present exemplary embodiment is generally similar to the semiconductor device described with reference to FIG. 1, except that the isolation mask 132 is positioned at the bottom of the cell isolation region 300a. Accordingly, the sacrificial layer 120 may remain continuously without being separated by the cell isolation region 300a.

The isolation mask 132 may be positioned at the same level as the mask pattern 130. That is, the isolation mask 132 may be formed on the sacrificial layer 120 and is located between the semiconductor stacks 200. As illustrated in FIG. 7, an edge of the isolation mask 132 may be located under the semiconductor stacks 200.

As described with reference to FIG. 1, the cavity 150a is positioned in the opening regions of the mask pattern 130. Further, the cavity 150a may be located in the opening region between the mask pattern 130 and the separation mask 132.

The wiring 220 is electrically insulated from the sacrificial layer 120 by the isolation mask 132. The insulating layer 210 may be further interposed between the separation mask 132 and the wiring 220.

According to the present exemplary embodiment, since the cell isolation region 300a is positioned above the sacrificial layer 120, the depth of the cell isolation region 300a may be reduced as compared with the previous exemplary embodiment. Therefore, the depth at which the wiring 220 is formed can be reduced, thereby preventing disconnection of the wiring 220, and further increasing the size of the semiconductor laminates 200.

8 and 9 are plan and cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with still another embodiment of the present invention. Here, FIG. 8A is a plan view showing the mask pattern 130 and the separation mask 132, and FIG. 8B is a cross-sectional view taken along the cutting line A-A of FIG. 8A.

Referring to FIGS. 8A and 8B, first, as described with reference to FIG. 1A, a sacrificial layer 120 is formed on a substrate 110. In addition, as described with reference to FIG. 1B, a mask pattern 130 is formed on the sacrificial layer 120. However, in the present exemplary embodiment, the mask pattern 130 is divided into a plurality of regions. The mask pattern 130 may be separated into a plurality of regions by, for example, the separation mask 132. The isolation mask 132 may be formed of the same material as the mask pattern 130 by the same process. However, the present invention is not limited thereto, and the isolation mask 132 may be formed by another process as an insulating material different from the mask pattern 130.

The isolation mask 132 is formed corresponding to the cell isolation region 300a of FIG. 7, and each mask pattern 130 is formed corresponding to the cell region. Here, although the isolation mask 132 is described as being formed corresponding to the cell isolation region 300a, the isolation mask 132 may also be formed in the device isolation region, that is, the scribing line.

The mask pattern 130 may be a stripe pattern as described with reference to FIGS. 1B and 4 to 6, or an embossed or intaglio pattern.

Referring to FIG. 9A, as described with reference to FIG. 1C, the sacrificial layer 120 exposed to the opening region of the mask pattern 130 is partially etched using electrochemical etching (ECE). do.

Referring to FIG. 9B, the semiconductor stack 200 is grown using the sacrificial layer 120 as a seed. However, in the present embodiment, since the growth of the nitride semiconductor laminate 200 is blocked on the isolation mask 132, the cell isolation region () may be formed on the isolation mask 132 by the growth process of the nitride semiconductor laminate 200. 300a) is formed, whereby the nitride semiconductor laminate 200 is separated into a plurality of cell regions. That is, the cell isolation region 300a is self-aligned by the growth process of the semiconductor stack 200, and a separate patterning process for forming the cell isolation region 300a is omitted.

Referring to FIG. 9C, the second nitride semiconductor layer 180 and the active layer 170 of each semiconductor laminate 200 are partially etched to partially expose the top surface of the first nitride semiconductor layer 160. do. The second nitride semiconductor layer 180 and the active layer 170 may be etched using a photolithography and an etching process.

Referring to FIG. 9D, as described with reference to FIG. 3C, a transparent electrode layer 190 may be formed on the second nitride semiconductor layer 180. In the present embodiment, the transparent electrode layer 190 is formed after partially exposing the top surface of the first nitride semiconductor layer 160, but before exposing the top surface of the first nitride semiconductor layer 160. It may be formed.

In addition, as described with reference to FIG. 3C, an insulating layer 210 may be formed to cover side surfaces of the semiconductor stacks 200 and a part of the transparent electrode layer 190. Insulating layer 210 may also cover isolation mask 132.

Thereafter, as described with reference to FIG. 3D, a wiring 220 for connecting the semiconductor stacks 200 in series with each other is formed. However, the separation mask 132 may be positioned between the wiring 220 and the substrate 110 to insulate them from each other. In addition, an insulating layer 210 may be interposed between the separation mask 132 and the wiring 220.

The plurality of semiconductor stacks 200 may be variously connected by the wirings 220. Accordingly, various wirings of the plurality of semiconductor stacks 200 may be formed on the single substrate 110, such as series connection, parallel connection, anti-parallel connection, or serial / parallel mixed connection. The semiconductor device having the plurality of semiconductor stacks 200 may be manufactured by dividing the substrate 110 to include the plurality of semiconductor stacks 200.

According to the present exemplary embodiment, unlike the semiconductor device manufacturing method described with reference to FIGS. 2 and 3, it is not necessary to perform a patterning process to form the plurality of semiconductor laminates 200. In addition, since the cell isolation region 300a is formed to be shallower than the cell isolation region 200a of the previous embodiment, the wiring 220 can be easily formed. Accordingly, the light emitting area may be increased by narrowing the width of the cell isolation region 300a or the side surface of the semiconductor laminate 200 may be inclined to improve light efficiency.

FIG. 10 is a SEM photograph showing a cavity 150a formed using electrochemical etching (ECE). Here, a GaN layer doped with Si of about 6E18 / cm 3 as a sacrificial layer 120 is grown on the gallium nitride substrate 110, and a stripe SiO ₂ having a width of about 4 μm is formed on the sacrificial layer 120. The mask pattern 130 was formed. The space | interval between each stripe was about 5 micrometers. Then, using an oxalic acid solution at 20 ° C of 0.3M, the first step was applied with a voltage of 8V, the second step was applied with a voltage of 15V, and electrochemical etching was performed thereon. The laminate 200 was grown.

As shown in FIG. 10, it is observed that the cavity 150a is formed in the opening area of the mask pattern 130 under the mask pattern 130. The semiconductor laminate 200 is electrically insulated from the sacrificial layer 120 by the mask pattern 130 and the cavity 150a, and as a result, from the substrate 110.

As shown in FIG. 10, a portion of the cavity 150a may extend below the mask region of the mask pattern 130, but the present invention is not limited to the cavity 150a, and variously using electrochemical etching. Can be formed. For example, the cavity 150a may be formed to be limited to the opening region of the mask pattern 130.

While various embodiments have been described above, the invention should not be construed as limited to the specific embodiments. In addition, the components described in a specific embodiment may be applied to other embodiments without departing from the spirit of the present invention.

110: growth substrate, 120: sacrificial layer
130: mask pattern, 140: insulating structure,
150a: cavity, 160: first nitride semiconductor layer,
170: active layer, 180: second nitride semiconductor layer,
190: transparent electrode layer, 200: nitride semiconductor laminate,
200a, 300a: cell isolation region, 210: insulating layer,
220: wiring

Claims (23)

Board;
A gallium nitride based semiconductor laminate positioned on the substrate;
An insulating structure positioned between the substrate and the semiconductor laminate to insulate the semiconductor laminate from the substrate; And
Including a gallium nitride-based sacrificial layer between the insulating structure and the substrate,
The insulating structure,
A mask pattern having a mask region and an opening region; And
A cavity located in an opening region of the mask pattern,
The cavity is located below the level where the mask pattern is located,
A portion of the cavity positioned between the mask region and the sacrificial layer below the mask region so as to overlap a portion of the cavity. delete delete The method according to claim 1,
The sacrificial layer has a Si doping concentration within the range of 1E17 / cm ³ to 1E19 / cm ³ . The method according to claim 1,
And the substrate is a polar, nonpolar or semipolar gallium nitride substrate. The method according to claim 1,
The mask pattern is a semiconductor device formed of at least one insulating material selected from the group consisting of SiO ₂ , SiN, MgO, TaO and TiO ₂ . The method according to claim 1,
The mask pattern is a semiconductor device in which the mask area is an embossed pattern of stripe, circle, rectangle, rhombus or hexagon shape. The method according to claim 1,
The mask pattern is a semiconductor device in which the opening region is an intaglio pattern of a circular, rectangular, rhombus, or hexagonal shape. The method according to claim 1,
The semiconductor device is a semiconductor device, characterized in that the light emitting device. The method according to any one of claims 1 and 4 to 9,
A plurality of semiconductor laminates are located on the substrate,
And the insulating structure is positioned between the substrate and the plurality of semiconductor laminates. The method according to claim 10,
And at least one wiring for connecting the plurality of semiconductor laminates in series with each other. The method according to claim 10,
And a separation mask positioned at the same level as the mask pattern between the plurality of semiconductor laminates. The method according to claim 12,
The isolation mask is formed of the same material as the mask pattern. delete delete delete delete delete delete delete delete delete delete

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