KR102015962B1 - Semiconductor device - Google Patents

Abstract

A semiconductor device having an element region in which a semiconductor element is formed and an outer circumferential region disposed around the element region, wherein the first semiconductor region of the first conductive type and the first semiconductor region extends over the element region and the outer circumferential region. a second semiconductor region of a second conductive type, which constitutes a superjunction structure in which a pn junction is disposed, and a second conductive type second to a total amount of impurities in the first semiconductor region of the first conductive type in the outer peripheral region The impurity total ratio of the impurity total amount in the semiconductor region is closer to 1 than the impurity total ratio in the element region.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device having a super junction structure.

A superjunction (SJ) structured MOS transistor (hereinafter referred to as "SJMOS"), in which a pn junction between a drift region and a p-type pillar region is formed periodically, has a high breakdown voltage and low on-resistance. (on 抵抗) has the property. In the SJMOS, the on-resistance can be lowered by the current flowing through the drift region where the impurity concentration is increased. On the other hand, in the case of reverse bias, the drift region is depleted by the depletion layer extending from the pn junction, thereby ensuring high breakdown voltage. At this time, in order to completely deplete the drift region, the ratio of the p-type impurity total amount and the n-type impurity total amount is set in the vicinity of one.

In the case of using the SJMOS as a power semiconductor element, an outer periphery disposed around the element region rather than the breakdown voltage of the element region in which the semiconductor element is disposed in order to improve the avalanche content and maintain reliability. It is preferable to set the internal pressure of an area | region high. As a result, the outer circumferential region becomes the negative resistance mode before sufficient avalanche current flows, thereby reducing the avalanche content. In particular, in SJMOS, the electric field strength of the drift region increases at breakdown time. For this reason, when the breakdown voltage in the outer circumferential region is low, avalanche breakdown occurs and breakage is reached while the avalanche current and voltage increase are small, and reliability is lowered.

However, in SJMOS, the internal pressure is ensured by the ratio of the total amount of impurities in the SJ structure as described above.

For this reason, there is a method of setting the internal pressure of the outer circumferential region higher than the element region by deepening the p-type columnar region in the outer circumferential region rather than the element region (see Patent Document 1, for example). According to this structure, the internal pressure of the outer peripheral region can be made higher than that of the element region by forming a depletion layer in the depth direction in the outer peripheral region.

Japanese Unexamined Patent Publication No. 2008-78282

However, if the depth of the p-type columnar region is different between the element region and the outer circumferential region, the distortion of the potential distribution is sharply increased at the boundary between the element region and the outer circumferential region. As a result, the reliability of the semiconductor device is lowered, such as lowering of internal pressure, oscillation, lowering of avalanche content, and the like.

In view of the above problems, an object of the present invention is to provide a semiconductor device having a high superjunction structure with high reliability while increasing the internal pressure of the outer peripheral region than the element region.

According to one aspect of the present invention, there is provided a semiconductor device having an element region in which a semiconductor element is formed and an outer circumferential region disposed around the element region, which (a) a first conductive type first extending over the element region and the outer circumferential region; And a second semiconductor region of the second conductive type, which constitutes a superjunction structure in which a pn junction is disposed between the semiconductor region and (b) the first semiconductor region, wherein the first conductive type is formed in the outer peripheral region. There is provided a semiconductor device in which the impurity total ratio of the impurity total amount in the second semiconductor region of the second conductivity type to the impurity total amount in the first semiconductor region is closer to one than the impurity total ratio in the element region.

According to another aspect of the present invention, there is provided a semiconductor device having an element region in which a semiconductor element is formed and an outer circumferential region disposed around the element region, wherein (a) a first semiconductor of the first conductive type extends over the element region and the outer circumferential region; A superjunction structure in which the pn junctions are periodically arranged and spaced apart from each other within the first semiconductor region so as to form pn junctions extending in the film thickness direction between the region and (b) the first semiconductor region. And a plurality of second semiconductor regions of the second conductive type constituting the second conductive type, so that the impurity total ratio of the total amount of impurities of the second conductive type to the total amount of impurities of the first conductive type is closer to 1 in the peripheral region than the element region, The width of the upper portion of the second semiconductor region is equal in the element region and the outer peripheral region, and the width of the lower portion of the second semiconductor region is equal to the element region and the outer peripheral region. In contrast, another semiconductor device is provided.

According to still another aspect of the present invention, there is provided a semiconductor device having an element region in which a semiconductor element is formed and an outer circumferential region disposed around the element region, which comprises: (a) a first conductive type first extending over the element region and the outer circumferential region; Superjunctions spaced apart from each other within the first semiconductor region so as to form pn junctions extending along the film thickness direction between the semiconductor region and (b) the first semiconductor region, and the pn junctions are periodically arranged. And a plurality of second semiconductor regions of the second conductive type constituting the structure, such that the impurity total ratio of the total amount of impurities of the second conductive type to the total amount of impurities of the first conductive type is closer to 1 in the outer region than the element region. A semiconductor device is provided in which the width of the lower portion of the second semiconductor region is equal in the element region and the outer peripheral region and the width of the upper portion of the second semiconductor region is different in the element region and the outer peripheral region.

According to the present invention, it is possible to provide a semiconductor device having a superjunction structure with high reliability while increasing the breakdown voltage of the outer peripheral region than the element region.

1 is a schematic cross-sectional view showing the configuration of a semiconductor device according to the first embodiment of the present invention.
Fig. 2 is a schematic plan view showing the structure of a semiconductor device according to the first embodiment of the present invention.
3 is a schematic sectional view showing the structure of a semiconductor device of a comparative example.
In FIG. 4, FIG. 4A is a graph showing the results of simulating the potential distribution of the comparative example shown in FIG. 3, and FIG. 4B shows the results of simulating the electric field distribution of the comparative example shown in FIG. It is a graph.
5 is a graph showing the relationship between the impurity total amount ratio and the internal pressure in the drift region.
6 is a schematic cross-sectional view showing the first example of the shape of the p-type columnar region of the semiconductor device according to the first embodiment of the present invention.
FIG. 7 is a graph showing the distribution of impurities in the p-type columnar region in the outer circumferential region shown in FIG.
Fig. 8 is a schematic plan view showing the width of the p-type columnar region shown in Fig. 6.
FIG. 9 is a graph showing the distribution of impurities in the p-type columnar region in the element region shown in FIG.
In FIG. 10, FIG. 10 (a) is a graph showing the results of simulating the potential distribution of the semiconductor device according to the first embodiment of the present invention, and FIG. 10 (b) shows the first embodiment of the present invention. It is a graph which shows the result of simulating the electric field distribution of a semiconductor device.
Fig. 11 is a schematic cross sectional view showing a second example of the shape of the p-type columnar region of the semiconductor device according to the first embodiment of the present invention.
FIG. 12 is a schematic plan view showing the width of the p-type columnar region shown in FIG.
FIG. 13 is a graph showing the distribution of impurities in the p-type columnar region in the element region shown in FIG.
14 is a schematic cross-sectional view showing a third example of the shape of the p-type columnar region of the semiconductor device according to the first embodiment of the present invention.
Fig. 15 is a schematic plan view showing the width of the p-type columnar region shown in Fig. 14.
FIG. 16 is a graph showing the distribution of impurities in the p-type columnar region in the outer circumferential region shown in FIG.
17 is a schematic cross-sectional view showing the fourth example of the shape of the p-type columnar region of the semiconductor device according to the first embodiment of the present invention.
FIG. 18 is a schematic plan view showing the width of the p-type columnar region shown in FIG. 17. FIG.
FIG. 19 is a graph showing the distribution of impurities in the p-type columnar region in the outer circumferential region shown in FIG.
20 is a schematic view for explaining an example of a method for forming a p-type columnar region.
21 is a schematic sectional view showing the structure of a semiconductor device according to a modification of the first example of the first embodiment of the present invention.
Fig. 22 is a schematic sectional view showing the structure of a semiconductor device according to a modification of the second embodiment of the first embodiment of the present invention.
Fig. 23 is a schematic sectional view showing the structure of a semiconductor device according to a modification of the third example of the first embodiment of the present invention.
24 is a schematic sectional view showing the structure of a semiconductor device according to a modification of the fourth embodiment of the first embodiment of the present invention.
25 is a schematic plan view showing the structure of a semiconductor device according to a second embodiment of the present invention.
Fig. 26 is a schematic plan view showing the structure of a semiconductor device according to a modification of the second embodiment of the present invention.

EMBODIMENT OF THE INVENTION Next, embodiment of this invention is described with reference to drawings. In description of the following drawings, the same or similar code | symbol is attached | subjected to the same or similar part. It is to be noted, however, that the drawings are schematic and that the thickness ratio of each layer is different from the reality. Therefore, specific thickness or dimensions should be determined in consideration of the following description. Moreover, of course, the part from which the relationship and the ratio of a mutual dimension differ also in between drawings is contained.

In addition, embodiment shown below illustrates the apparatus and method for actualizing the technical idea of this invention, and embodiment of this invention specifies the material, shape, structure, arrangement | positioning, etc. of a component as follows. no. Embodiment of this invention can add a various change in a Claim.

(First embodiment)

In the semiconductor device 1 according to the first embodiment of the present invention, as shown in FIG. 1, the peripheral region disposed around the element region 101 and the element region 101 where the semiconductor element is formed. Iii) 102. The semiconductor device 1 includes a first semiconductor region (drift region 10) of a first conductivity type extending over the element region 101 and the outer circumferential region 102, A plurality of second semiconductor regions (p-shaped pillar regions 20) of the second conductive type are arranged inside the first semiconductor region.

The first conductive type and the second conductive type are opposite conductive types. That is, if the first conductivity type is n type, the second conductivity type is p type, and if the first conductivity type is p type, the second conductivity type is n type. Here, the first conductive type is n type and the second conductive type is p type.

The p-type columnar regions 20 are arranged so as to form pn junctions extending along the film thickness direction (depth direction of the semiconductor device 1) between the drift regions 10. In other words, the drift region 10 and the p-type columnar region 20 form a super junction (SJ) structure in which pn junctions are periodically arranged. Although details will be described later, the impurity total ratio of the impurity total amount of the second conductivity type to the impurity total amount of the second conductivity type in the outer circumferential region 102 (hereinafter referred to as "impurity total amount ratio") is the element region ( It is set to be closer to 1 than the impurity total amount ratio in 101).

Here, the total amount of impurities of the second conductivity type is the total amount of p-type impurities between the centers of the p-type columnar regions 20 in the region of the SJ structure, and the total amount of impurities of the first conductivity type is the p-type in the region of the SJ structure. The total amount of n-type impurities in the drift region 10 existing between the centers of the columnar regions 20.

In the semiconductor device 1, the high concentration n-type semiconductor region 40 is disposed on the drain electrode 30. The n-type semiconductor region 40 is formed by doping phosphorus (P), which is an n-type impurity, on a semiconductor substrate such as silicon (Si), for example. The n-type semiconductor region 40 functions as a drain region. The drain electrode 30 and the n-type semiconductor region 40 are ohmic connected.

On the n-type semiconductor region 40, a drift region 10 having a lower impurity concentration than the n-type semiconductor region 40 is disposed. The bottom portion of the p-type columnar region 20 formed inside the drift region 10 has reached the upper surface of the n-type semiconductor region 40. As shown in Fig. 1, in the element region 101 and the outer circumferential region 102, the depths of the p-type columnar regions 20 are equal.

In the element region 101, a p-type base region 50 having a higher impurity concentration than the p-type columnar region 20 is disposed above each of the p-type columnar region 20. have. Adjacent base regions 50 are separated by the drift region 10. The upper end of the p-type columnar region 20 reaches the lower surface of the base region 50.

An n-type source region 60 is arranged in an island shape inside the base region 50. The upper surface of the source region 60 is at the same plane level as the upper surfaces of the base region 50 and the drift region 10.

The gate electrode is formed at least above the region facing the base region 50, for example, above the adjacent source region 60 and above the drift region 10 between the source region 60. 70) is arranged. The gate electrode 70 is a polysilicon film, for example. The gate electrode 70 is covered with an insulating film 80, and the gate electrode 70, the source region 60, the base region 50, and the drift region 10 are attached to the insulating film 80. Is electrically insulated. The insulating film 80 between the gate electrode 70 and the base region 50 functions as a gate insulating film. For example, a silicon oxide film or the like is used for the insulating film 80.

In addition, the source electrode 90 is disposed to cover the top and side surfaces of the insulating film 80. The source electrode 90 is connected to the source region 60 and the base region 50 exposed to the region where the insulating film 80 is not disposed.

In the semiconductor device 1, a gate voltage of a threshold value or more is applied to the gate electrode 70 in a state where a predetermined voltage is applied between the drain electrode 30 and the source electrode 90, thereby providing the gate electrode of the base region 50. Channels are formed in the region opposite 70. As a result, a drain current flows between the drain electrode 30 and the source electrode 90.

In the outer circumferential region 102, for example, the base region 50 is in contact with the upper portion of the p-type columnar region 20 closest to the element region 101 and has a higher impurity concentration than the p-type columnar region 20. The p-type region 110 having an impurity concentration equal to is disposed above the drift region 10. A p-type resurf region 120 extending from the p-type region 110 toward the outer edge of the outer circumferential region 102 is formed above the drift region 10. The impurity concentration of the resurf region 120 is lower than that of the base region 50 or the p-type region 110. By forming the resurf region 120 on the surface of the drift region 10, the depletion layer from the pn junction extends outward during reverse bias, so that the depletion layer elongates slowly in the outer circumferential region 102. Done. As a result, electric field concentration is alleviated, and the breakdown voltage of the semiconductor device 1 is improved.

As shown in FIG. 2, in the semiconductor device 1, the p-type pillar-shaped region 20 continuously extends between the main surface of the drift region 10 over the element region 101 and the outer circumferential region 102. In parallel, it is stretched in a stripe shape. That is, in plan view, the n-type drift region 10 and the p-type pillar region 20 are alternately arranged in a stripe shape.

In the SJMOS, it is preferable to set the internal pressure of the outer circumferential region 102 to be higher than the internal pressure of the element region 101 in order to improve the avalanche content and maintain the reliability. For this reason, as in the comparative example shown in FIG. 3, the p-type columnar region 20 is deeper in the outer peripheral region 102 than in the element region 101, thereby making the internal pressure of the outer peripheral region 102 higher than the element region 101. FIG. There is a way to set it. However, in the semiconductor device of the comparative example, as shown in the region A of Fig. 4A, a sharply high dislocation distribution occurs at the boundary between the element region 101 and the outer peripheral region 102. As a result, lowering of internal pressure, oscillation, lowering of avalanche content, etc. occur in a semiconductor device. Due to the sharply distorted electric potential distribution, for example, as shown in region B of FIG. 4 (b), the electric field is formed at the end of the element region 101 near the boundary with the outer circumferential region 102. Concentration occurs. As a result, the breakdown voltage of the semiconductor device of the comparative example is lowered.

In contrast, in the semiconductor device 1 shown in FIG. 1, the element region 101 and the outer circumferential region are in a state where the depths of the p-type columnar regions 20 in the element region 101 and the outer circumferential region 102 are equal. Impurity amount distribution in the depth direction of the p-type columnar region 20 in 102 is controlled to set the internal pressure of the outer peripheral region 102 to be higher than the internal pressure of the element region 101. The control of the impurity amount distribution of the p-type columnar region 20 in the semiconductor device 1 will be described below.

5 shows the relationship between the ratio of the total amount of p-type impurities and the total amount of n-type impurities and the breakdown voltage VB in the semiconductor device 1. 5 is a ratio of the p-type impurity total amount Qp to the n-type impurity total amount Qn (hereinafter referred to as "impurity total amount ratio R"). Here, R = Qp / Qn. As shown in Fig. 5, when the impurity total amount ratio R is 1, that is, when the relationship between the impurity total amount Qp and the impurity total amount Qn is Qp = Qn, the breakdown voltage VB is the highest. As the absolute value of the difference from 1 in the impurity total amount ratio R increases, the internal pressure decreases.

In the semiconductor device 1, the breakdown voltage of the outer peripheral region 102 is set higher than the breakdown voltage of the element region 101 based on the relationship between the impurity total amount ratio R and the breakdown voltage VB shown in FIG. 5. That is, p-type so that the absolute value of the difference from 1 of the impurity total amount ratio R1 in the element region 101 becomes larger than the absolute value of the difference from 1 of the impurity total amount ratio R2 in the outer peripheral region 102. The total amount of impurities and the total amount of n-type impurities are set. Therefore, the absolute value ΔR1 (ΔR1 = | 1-R1 |) of the difference from 1 of impurity total ratio R1 and the absolute value ΔR2 (ΔR2 = | 1-R2 |) of difference from 1 of impurity total ratio R2 are ΔR1> ΔR2.

When the distance L between the centers of the p-type columnar regions 20 is the same in the element region 101 and the outer circumferential region 102, the narrower the width of the p-type columnar region 20 is, the less the total amount of impurities Qp decreases. do. In other words, the impurity total amount ratio R becomes small. On the contrary, as the width of the p-type columnar region 20 is wider, the impurity total amount Qp is increased, and the impurity total amount ratio R becomes larger. In the semiconductor device 1 shown in FIG. 1, the width Wp of the p-type columnar region in the element region 101 and the outer peripheral region 102 is set so as to satisfy the relationship of ΔR1> ΔR2.

On the other hand, for example, only in the element region 101, the width Wp of a part of the p-type columnar region 20 in the depth direction of the semiconductor device 1 is different from that of the p-type columnar region 20 and the like. Do it differently (for example, widen). Thus, by widening the width Wp of a part of the p-type columnar region 20 in the depth direction, the impurity total amount ratio R1 in the element region 101 is larger than the impurity total amount ratio R2 in the outer peripheral region 102. Increase

In the depth direction of the outer circumferential region 102, the width Wp of the p-type columnar region 20 is constant. Here, the width of the p-type columnar region 20 and the center position of the p-type columnar region 20 in the outer circumferential region 102 are such that the impurity total amount Qp and the impurity total amount Qn are equal, so that the impurity total ratio R2 is 1. Is set. For this reason, the absolute value ΔR2 of the difference in the outer circumferential region 102 is smaller than the absolute value ΔR1 of the difference in the element region 101. Moreover, even if the impurity total amount Qp and the impurity total amount Qn are not completely equal in the outer peripheral area 102, the absolute value ΔR2 of the difference may be smaller than the absolute value ΔR1 of the difference.

For example, as in the first embodiment shown in FIG. 6, when the width Wp of the p-type columnar region 20 of the outer circumferential region 102 is constant to the width Wa in the depth direction, the impurity total amount Qp and impurities The total amount Qn is the same, so that the impurity total amount ratio R2 is close to one. At this time, the impurity total amount Qp and the impurity total amount Qn are impurity amounts Qa as shown in FIG. The vertical axis of the graph showing the impurity amount distribution is the depth D in the depth direction, and the horizontal axis is the impurity amount Q (hereinafter the same).

At this time, the width Wp of the upper portion of the p-type columnar region 20 in the element region 101 is made wider than the width Wp of the lower portion, so that the impurity total amount ratio R1 in the element region 101 is circumscribed. It is set as the value farther from 1 than the impurity total amount ratio R2 in the area | region 102. As a result, the absolute value ΔR2 of the difference becomes smaller than the absolute value ΔR1 of the difference. In the first embodiment shown in Fig. 6, the distance L between the centers of the p-type pillar-shaped regions 20 repeatedly formed in the element region 101 is equal to that of the outer circumferential region 102. The upper width Wb of the p-type columnar region 20 of the region 101 is wide, and the lower width Wa is equal to the width Wa of the p-type columnar region 20 of the outer circumferential region 102. Same (Wa <Wb). Here, it is preferable that the area | region of the upper part of the p-type columnar area | region 20 which is width Wb is formed above the half position of the depth direction of the p-type columnar area | region 20 whole. In other words, the width Wp of the p-type columnar region 20 of the element region 101 is different from the width Wp of the p-type columnar region 20 of the outer circumferential region 102. It is preferable that it is half or less of the total thickness of the pattern area 20. Moreover, it is more preferable that the area | region of the width Wb is formed in the range of the upper 1/3 area | region of the p-type columnar area | region 20. 8 shows a plan view of the p-type columnar region 20 in the boundary region between the element region 101 and the outer circumferential region 102. The lower portion of the p-type columnar region 20 of the element region 101 is indicated by a dashed line, and the p-type columnar region 20 of the element region 101 is the element region 101 and the outer peripheral region 102. It is formed continuously in the p-type columnar region 20 of the outer circumferential region 102 in the boundary region of. On the other hand, the upper portion of the p-type columnar region 20 of the element region 101 is wider than the upper portion of the p-type columnar region 20 of the outer circumferential region 102 and narrower at the boundary region.

In the impurity amount distribution of the p-type columnar region 20 in the element region 101 shown in Fig. 6, as shown in Fig. 9, the impurity amount Qb in the upper portion is larger than the impurity amount Qa in the lower portion. For this reason, since the impurity total amount ratio R1 in the element region 101 is larger than 1 and farther from 1 than the impurity total amount ratio R2 in the outer peripheral region 102, it can be set to (DELTA) R1> (DELTA) R2.

Therefore, in the semiconductor device 1, the internal pressure of the element region 101 is smaller than the internal pressure of the outer circumferential region 102. FIG. 10A shows a simulation result of the potential distribution near the boundary between the element region 101 and the outer circumferential region 102 in the semiconductor device 1. Unlike in FIG. 4A, which is a case of the comparative example, the potential distribution is smoothly changed at the boundary between the element region 101 and the outer peripheral region 102. As a result, as shown in Fig. 10B, electric field concentration at the end of the element region 101 does not occur.

6 shows an example in which the impurity total amount ratio R1 in the element region 101 is larger than 1, but is sandwiched in the p-type columnar region 20 of the element region 101, which is a current path. The width of the drift region 10 becomes narrow. Therefore, it is preferable to make impurity total ratio R1 smaller than 1 as (DELTA) R1> (DELTA) R2. That is, the distance L between the centers of the p-type pillar-shaped region 20 repeatedly formed as in the second embodiment shown in FIG. 11 is the same in the element region 101 and the outer circumferential region 102. The width Wc of the narrow area | region of the lower part of the p-type columnar area | region 20 in () is made into the width | variety, and the width | variety Wa of the p-type columnar area | region 20 of the outer periphery area | region 102 is made into the upper width. (Wa> Wc). Here, it is preferable that the width | variety of the p-type columnar area | region 20 is formed below half of the p-type columnar area | region 20, and the lower 1/3 of the p-type columnar area | region 20 It is more preferable to form in the range of an area | region.

12 shows a plan view of the p-type columnar region 20 in the boundary region between the element region 101 and the outer circumferential region 102. The lower portion of the p-type columnar region 20 of the element region 101 is indicated by a dashed-dotted line, and is narrower in width than the p-type columnar region 20 of the outer circumferential region 102 and wider in the boundary region. . On the other hand, the upper part of the p-type columnar region 20 of the element region 101 is continuously formed in the p-type columnar region 20 of the outer circumferential region 102 in the boundary region. Since Wa> Wc, as shown in FIG. 13, the impurity amount Qc of the lower part of the p-type columnar region 20 in the element region 101 is smaller than the impurity amount Qa of the upper part. For this reason, the impurity total amount ratio R1 in the element region 101 is smaller than 1, and can be set to (DELTA) R1> (DELTA) R2 as a value which is farther from 1 than the impurity total amount ratio R2 in the outer peripheral area 102.

In the above, the width Wp of each p-type columnar region 20 in the depth direction of the outer circumferential region 102 is made constant, and each p-type columnar region in the depth direction of the element region 101 is provided. The width Wp of a portion of the region 20 is different from the width Wp of the p-type columnar region 20 of the outer circumferential region 102, and the width Wp of the remaining region of the p-type columnar region 20. ) Shows an example equivalent to the width Wp of the p-type columnar region 20 in the outer circumferential region 102. However, the width Wp of the p-type columnar region 20 in the depth direction of the element region 101 is constant, and a part of the region of the p-type columnar region 20 in the depth direction of the outer peripheral region 102. The width Wp is different from the width Wp of the p-type columnar region 20 of the outer circumferential region 102, and the width Wp of the remaining region of the p-type columnar region 20 is the element region 101. By satisfying the width equivalent to the p-type columnar region 20 of (), the relationship of ΔR1> ΔR2 may be satisfied. In this case, since the structure of the element region 101 which is the current path does not change from the conventional one, the on-resistance does not increase.

For example, the distance L between the centers of the p-type pillar-shaped region 20 repeatedly formed as in the third embodiment shown in FIG. 14 is the same in the element region 101 and the outer circumferential region 102, and is the outer circumferential region. The p-type columnar region 20 in 102 has a wide upper region and a narrow lower region, and the impurity total amount ratio R2 is close to one. Here, the width | variety of the area | region of the upper part where the p-type columnar area | region 20 in the outer periphery area | region 102 is wide Wd, and the width | variety of the narrow lower area | region is made width We. It is preferable to form the area of the width We of the p-type columnar region 20 below the half of the p-type columnar region 20, and to form it within the range of the area of the lower 1/3. More preferred. On the other hand, the width of the p-type columnar region 20 in the element region 101 is the width Wd, and is made constant in the depth direction of the p-type columnar region 20. 15 is a plan view of the p-type columnar region 20 in the boundary region between the element region 101 and the outer circumferential region 102. As shown in FIG. Since Wd> We, as shown in FIG. 16, the impurity amount Qe in the width We of the p-type columnar region 20 in the outer circumferential region 102 is equal to that of the p-type columnar region 20. As shown in FIG. It is less than the impurity amount Qd in the width Wd. For this reason, the impurity total amount ratio R2 in the outer circumferential region 102 is closer to 1 than the impurity total amount ratio R1 in the element region 101, and can be set to ΔR1> ΔR2.

Alternatively, the distance L between the centers of the p-type pillar-shaped region 20 repeatedly formed as in the fourth embodiment shown in FIG. 17 is the same in the element region 101 and the outer peripheral region 102, and the outer peripheral region 102. The width of the upper region where the p-type pillar-shaped region 20 is wide is Wg, and the width of the narrow lower region is Wf, and the impurity total ratio R2 is the impurity total ratio R1. Closer to 1 Here, it is preferable to form the area of the width Wg of the p-type columnar region 20 above the half of the p-type columnar region 20, and more preferably to form it within the range of the upper 1/3 area. desirable. On the other hand, the width of the p-type columnar region 20 in the element region 101 is the width Wf, and is made constant in the depth direction of the p-type columnar region 20. 18 shows a plan view of the p-type columnar region 20 in the boundary region between the element region 101 and the outer circumferential region 102. As shown in FIG. Since Wg > Wf, as shown in FIG. 19, the amount of impurities Qg in the width Wg of the p-type columnar region 20 in the outer circumferential region 102 is reduced to that of the p-type columnar region 20. As shown in FIG. It is less than the impurity amount Qf in the width Wf. For this reason, the impurity total amount ratio R2 in the outer circumferential region 102 is closer to 1 than the impurity total amount ratio R1 in the element region 101, and can be set to ΔR1> ΔR2.

SJMOS has a high degree of integration in columnar areas to improve the trade-off relationship between on voltage and breakdown voltage. Since the width Wp of the p-type columnar region 20 is narrow, if the width Wp is uniformly changed in the depth direction, it is difficult to control because the amount of change in the total amount of impurities is large and the amount of change in internal pressure is also large. In particular, in the case of forming the p-type columnar region 20 using a mask, it is necessary to consider the margin of the mask dimension, which is more difficult to control. Therefore, it is difficult to set the balance of the amount of impurities by uniformly changing the entire width Wp of the p-type columnar region 20 in the depth direction. For this reason, it is preferable not to change the whole width Wp of the p-type columnar area | region 20, but to change one part as already demonstrated.

As described above, in the semiconductor device 1, a p-type column is formed in one of the outer circumferential region 102 and the element region 101 so that the inner pressure of the outer circumferential region 102 becomes higher than that of the element region 101. The impurity amount distribution in the depth direction of the region 20 is constant, and the impurity amount distribution in the depth direction of the p-type columnar region 20 changes in the other of the outer peripheral region 102 and the element region 101. For example, the width Wp of the p-type columnar region 20 is set so that the impurity total amount ratio R2 is close to 1 and satisfies the relationship of ΔR1> ΔR2. Accordingly, it is possible to improve reliability by forming a difference in the breakdown voltage in the element region 101 and the outer peripheral region 102 while maintaining a high breakdown voltage. That is, in the semiconductor device 1, high reliability is realized by the improvement of the avalanche tolerance.

In addition, the SJ structure of the semiconductor device 1 includes a p-type epitaxial layer in a groove (trench) formed by, for example, etching the drift region 10 vertically and deeply. The filling can be formed by the "K trench method." When the p-type columnar region 20 is formed by the K trench method, only the groove width of a part of the p-type columnar region 20 is changed in the depth direction. For this reason, since the p-type columnar region 20 of the element region 101 and the p-type columnar region 20 of the outer circumferential region 102 can be formed at the same time, a part of the p-type columnar region 20 can be formed. The increase in the process can be suppressed as compared with the case where the impurity concentration is changed to ΔR1> ΔR2.

Alternatively, the SJ structure may be formed by a "multi epitaxial layer method" in which a multilayer epitaxial layer is deposited. 20 shows an example of the p-type columnar region 20 formed by the multi-epitaxial layer method. In the multi-epitaxial layer method, after the n-type epitaxial layer is formed, p-type impurity ions such as boron are formed into the epitaxial layer by using a mask formed by photolithography or the like. Inject into the area. Then, the p-type region 200 is formed in the n-type epitaxial layer by an annealing process. By repeating the above process while widening the semiconductor region by thermal diffusion, the upper and lower p-type regions 200 are connected to each other to form a p-type columnar region in the n-type semiconductor region. In the multi-epitaxial layer system, a plurality of constricted places occur along the depth direction. For this reason, as shown in FIG. 20, the p-type pillar-shaped area | region 20 is formed in the shape in which the several end-shaped p-type area | region 200 was connected in the depth direction.

In the case of forming the p-type columnar region 20 by the multi-epitaxial layer method, the mask may be changed to a mask having a different exposure dimension while the p-type columnar region 20 is formed in the depth direction. good. For this reason, the p-type columnar region 20 of the element region 101 and the p-type columnar region 20 of the outer circumferential region 102 can be formed simultaneously. Therefore, the increase in the process can be suppressed as compared with the case where the impurity concentration of a part of the p-type columnar region 20 is changed to ΔR1> ΔR2. Here, when the maximum width Wp of each p-type area | region 200 is constant, the p-type columnar area | region 20 shall be constant in a depth direction. On the contrary, when the maximum width Wp of each p-type area | region 200 changes in the depth direction, it is assumed that the p-type columnar area | region 20 changes in the depth direction.

In one p-pillar region 20, the width of the plurality of (2-5) tip-shaped p-type regions 200 is different from the width of the remaining p-type regions 200. , It is desirable to satisfy the relationship of ΔR1> ΔR2.

<Variation example>

Between the element region 101 and the outer circumferential region 102, a transition region in which the impurity total amount ratio R is intermediate between the element region 101 and the outer circumferential region 102 may be disposed. For example, in at least one of the element region 101 and the outer circumferential region 102, the width Wp of the p-type columnar region 20 is wide in a part in the depth direction and constant in the remaining region, and the other. In the case of constant in the depth direction, the width Wp of the p-type pillar-shaped region 20 is also wider in part in the depth direction and constant in the remaining region in the transition region. At this time, the thickness of the region where the width Wp is wide in the transition region is set to be halfway between the thickness of the element region 101 and the outer circumferential region 102.

For example, as in the first embodiment shown in FIG. 6, the p-type columnar region 20 of the element region 101 has an area above the width Wa and an area below the width Wb, and the outer peripheral area. When the p-type columnar region 20 of 102 has a constant width Wb in the depth direction (Wa <Wb), as shown in FIG. 21, the width Wa of the transition region 103 is also shown. The p-type columnar region 20 is formed to have an upper region and a lower region of the width Wb. At this time, the thickness of the area Wa of the p-type columnar region 20 of the transition region 103 so that the area of the width Wb is smaller than the p-type columnar region 20 of the element region 101. Is smaller than the thickness of the region of the width Wa of the p-type columnar region 20 of the element region 101. As a result, the impurity total amount ratio R in the transition region 103 is halfway between the element region 101 and the outer circumferential region 102.

The same applies to the case where the width Wp of the p-type columnar region 20 is changed as in the second embodiment shown in FIG. 11, the third embodiment shown in FIG. 14 and the fourth embodiment shown in FIG. Examples of the transition region 103 in which the p-type columnar region 20 is disposed in the semiconductor device 1 having the shapes shown in FIGS. 11, 14, and 17 are shown in FIGS. 22, 23, and 24, respectively.

By arranging the transition region 103, the change in the potential distribution at the boundary between the element region 101 and the outer circumferential region 102 becomes small, and the occurrence of distortion can be suppressed. As a result, the change in the electric field distribution becomes smooth, and the breakdown voltage of the semiconductor device 1 can be further improved.

21 to 24, the resurf region 120 is preferably disposed outside the transition region 103 in a plan view. This is because the resurf region 120 is in contact with the p-type columnar region 20 of the transition region 103 having a lower breakdown voltage than the outer circumferential region 102, resulting in a decrease in the breakdown voltage of the semiconductor device 1. to be.

(2nd Embodiment)

In the semiconductor device 1 according to the second embodiment of the present invention, as shown in Fig. 25, the p-type pillar-shaped region 20 has a dot shape with a constant center distance L in plan view. It is arranged. About a structure other than this, it is the same as that of 1st Embodiment shown in FIG.

That is, as shown in Fig. 25, also in the p-type columnar region 20 having a rectangular cross section perpendicular to the depth direction, the p-type columnar region ( 20) Adjust the amount of impurity distribution in the depth direction. For example, in either of the element region 101 and the outer circumferential region 102, the impurity amount distribution in the depth direction of the p-type columnar region 20 is made constant. On the other hand, the impurity content distribution in the depth direction is changed. As a result, the withstand voltage of the outer circumferential region 102 can be set higher than the withstand voltage of the element region 101. FIG. 25 shows an example in which the diameter of the p-type columnar region 20 in the element region 101 is made smaller in the lower portion. Other than this is substantially the same as 1st Embodiment, and the overlapping description is abbreviate | omitted.

As described above, also in the semiconductor device 1 according to the second embodiment, the difference in the breakdown voltage is formed in the element region 101 and the outer circumferential region 102 while maintaining the high breakdown voltage, thereby improving the reliability of the semiconductor device 1. You can.

In addition, a transition region 103 may be disposed between the element region 101 and the outer circumferential region 102 in which the impurity total amount ratio R is intermediate between the element region 101 and the outer circumferential region 102. For example, when the diameter of the p-type columnar region 20 of the outer circumferential region 102 is constant and the diameter of the p-type columnar region 20 of the element region 101 is made smaller from the lower side, the transition region ( Also in 103, the diameter of the p-type columnar region 20 is made smaller at the bottom. At this time, the impurity total amount ratio R in the transition region 103 is set to be halfway between the element region 101 and the outer peripheral region 102. In other words, the thickness of the lower region having a smaller diameter of the p-type columnar region 20 in the transition region 103 is the lower region having a smaller diameter of the p-type pillar region 20 in the element region 101. Set to become smaller than the thickness of.

Alternatively, the change amount of the diameter of the p-type columnar region 20 of the transition region 103 may be smaller than the change amount of the diameter of the p-type columnar region 20 of the element region 101 or the outer circumferential region 102. . For example, as shown in FIG. 26, the diameter of the p-type columnar region 20 of the outer circumferential region 102 is constant at the diameter d1, and the diameter of the p-type columnar region 20 of the element region 101 is constant. When the diameter d1 changes small from the diameter d2 (d1> d2), the diameter of the p-type columnar region 20 of the transition region 103 is changed from the diameter d1 to the diameter d3. Let's do it. At this time, by setting d1> d3> d2, the impurity total amount ratio R in the transition region 103 can be set between the element region 101 and the outer circumferential region 102.

In addition, in the above, the semiconductor device 1 whose cross section perpendicular | vertical to the depth direction of the p-type pillar-shaped area | region 20 is rectangular shape is shown by way of example. However, the cross section of the p-type columnar region 20 can adopt various shapes such as polygonal shape or circular shape other than rectangular shape.

(Other Embodiments)

As mentioned above, although this invention was described by embodiment, the description and drawings which form a part of this indication should not be understood as limiting this invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

In the above description, the p-type columnar region 20 is changed by changing a part of the width Wp in the depth direction with respect to either of the p-type columnar region 20 of the element region 101 and the outer circumferential region 102. An example of adjusting the width in the depth direction is described. However, the impurity concentration distribution of the p-type columnar region 20 may be adjusted instead of the width of the p-type columnar region 20.

Moreover, you may change the distance L between the centers of the p-type columnar area | region 20 in the outer peripheral area 102 in the range which satisfy | fills the relationship of (DELTA) R1> (DELTA) R2. Moreover, in the range which satisfy | fills the relationship of (DELTA) R1> (DELTA) R2, you may change a part of width Wp in the part which made width Wp constant in the depth direction of the p-type columnar area | region 20. As shown in FIG.

In addition, the depth of the p-type columnar region 20 is equal in the device region 101 and the outer circumferential region 102, and the bottom of the p-type columnar region 20 does not reach the top surface of the n-type semiconductor region 40. You may not do it.

In the transition region 103, a plurality of p-type columnar regions 20 are formed from the element region 101 toward the outer circumferential region 102, and the circumferential region from the element region 101 is formed through a plurality of steps. The total amount of impurities in the p-type columnar region 20 may be gradually changed toward 102.

Thus, of course, this invention includes various embodiment etc. which are not described here. Therefore, the technical scope of the present invention is defined only by the specific matters of the invention with respect to the claims which are appropriate from the above description.

The semiconductor device of this invention can be used for the use of the semiconductor device which employ | adopts a superjunction structure.

Claims (11)

A semiconductor device having an element region in which a semiconductor element is formed and an outer circumferential region disposed around the element region,
A first semiconductor region of a first conductivity type extending over the element region and the outer circumferential region;
The pn junctions are arranged to be spaced apart from each other in the first semiconductor region so as to form pn junctions extending along the film thickness direction between the first semiconductor region and the first semiconductor region, respectively. The second semiconductor region of the second conductivity type constituting the superjunction structure
Equipped,
The width of the upper portion of the second semiconductor region is greater than the element region and the outer circumference so that the impurity total ratio of the total amount of impurities of the second conductivity type to the total amount of impurities of the first conductivity type is closer to 1 in the outer region than the element region. The semiconductor device according to claim 1, wherein the width of the lower portion of the second semiconductor region is the same in the region and is different in the element region and the outer peripheral region.
The method of claim 1,
In one of the outer circumferential region and the element region, the second semiconductor region is a constant width in the depth direction,
In the other of the outer circumferential region and the element region, the second semiconductor region has a region having a width different from the region having the same width as the constant width along the depth direction.
A semiconductor device characterized by the above-mentioned.
delete A semiconductor device having an element region in which a semiconductor element is formed and an outer circumferential region disposed around the element region,
A first semiconductor region of a first conductivity type extending over the element region and the outer circumferential region;
Forming a superjunction structure in which the pn junctions are arranged to be spaced apart from each other within the first semiconductor region so as to form pn junctions extending in the film thickness direction with the first semiconductor region, respectively. The second semiconductor region of the second conductivity type
Equipped,
The width of the lower portion of the second semiconductor region is lower than that of the element region so that the impurity total ratio of the total amount of impurities of the second conductivity type to the total amount of impurities of the first conductivity type is closer to 1 in the outer region than the element region. The semiconductor device according to claim 1, wherein the width of the upper portion of the second semiconductor region is the same in the region and the peripheral region.
The method according to claim 1 or 4,
The thickness of the area | region in which the said width | variety of the said 2nd semiconductor region differs is less than half of the thickness of the whole said 2nd semiconductor region, The semiconductor device characterized by the above-mentioned.
The method according to claim 1 or 4,
And a transition region in which the impurity total amount ratio is between the element region and the outer circumferential region between the element region and the outer circumferential region.
The method of claim 6,
In at least one of the element region and the outer circumferential region, the width of the second semiconductor region changes in a depth direction,
In the transition region, the width of the second semiconductor region changes in the depth direction,
The position in the depth direction in which the width changes in the transition region is different from the position in which the width of the second semiconductor region in the element region or the outer peripheral region changes.
A semiconductor device characterized by the above-mentioned.
The method of claim 6,
And a resurf region (RESURF ') formed on the first semiconductor region in the outer circumferential region,
And the resurf region is disposed outside of the transition region in a plan view.
The method according to claim 1 or 4,
And said depths of said second semiconductor region are equal in said element region and said outer circumferential region.
The method according to claim 1 or 4,
The second semiconductor region extends in a stripe shape in parallel with the main surface of the first semiconductor region over the element region and the outer circumferential region, and the distance between the centers of the second semiconductor regions is A semiconductor device, characterized in that the same in the element region and the outer peripheral region.
The method according to claim 1 or 4,
And the second semiconductor region is arranged in a dot shape when viewed in a plane, and a distance between the centers of the second semiconductor regions is the same in the element region and the outer peripheral region.

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