KR102010312B1 - 디펜던시들을 정리하고 리빌딩하는 시스템 및 방법 - Google Patents

디펜던시들을 정리하고 리빌딩하는 시스템 및 방법 Download PDF

Info

Publication number
KR102010312B1
KR102010312B1 KR1020130160342A KR20130160342A KR102010312B1 KR 102010312 B1 KR102010312 B1 KR 102010312B1 KR 1020130160342 A KR1020130160342 A KR 1020130160342A KR 20130160342 A KR20130160342 A KR 20130160342A KR 102010312 B1 KR102010312 B1 KR 102010312B1
Authority
KR
South Korea
Prior art keywords
entry
counter
entries
value
dependent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020130160342A
Other languages
English (en)
Korean (ko)
Other versions
KR20140113304A (ko
Inventor
라비 아이옌가
샌딥 쿠마 두베이
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Publication of KR20140113304A publication Critical patent/KR20140113304A/ko
Application granted granted Critical
Publication of KR102010312B1 publication Critical patent/KR102010312B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
KR1020130160342A 2013-03-14 2013-12-20 디펜던시들을 정리하고 리빌딩하는 시스템 및 방법 Expired - Fee Related KR102010312B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/831,434 2013-03-14
US13/831,434 US9400653B2 (en) 2013-03-14 2013-03-14 System and method to clear and rebuild dependencies

Publications (2)

Publication Number Publication Date
KR20140113304A KR20140113304A (ko) 2014-09-24
KR102010312B1 true KR102010312B1 (ko) 2019-08-13

Family

ID=51419103

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020130160342A Expired - Fee Related KR102010312B1 (ko) 2013-03-14 2013-12-20 디펜던시들을 정리하고 리빌딩하는 시스템 및 방법

Country Status (5)

Country Link
US (2) US9400653B2 (https=)
JP (2) JP6320801B2 (https=)
KR (1) KR102010312B1 (https=)
CN (1) CN104050215B (https=)
DE (1) DE102014103188A1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10198263B2 (en) 2015-09-19 2019-02-05 Microsoft Technology Licensing, Llc Write nullification
US11681531B2 (en) 2015-09-19 2023-06-20 Microsoft Technology Licensing, Llc Generation and use of memory access instruction order encodings
US10180840B2 (en) * 2015-09-19 2019-01-15 Microsoft Technology Licensing, Llc Dynamic generation of null instructions
US10031756B2 (en) 2015-09-19 2018-07-24 Microsoft Technology Licensing, Llc Multi-nullification
US10061584B2 (en) 2015-09-19 2018-08-28 Microsoft Technology Licensing, Llc Store nullification in the target field
US10185568B2 (en) * 2016-04-22 2019-01-22 Microsoft Technology Licensing, Llc Annotation logic for dynamic instruction lookahead distance determination
US11474821B1 (en) * 2021-05-12 2022-10-18 International Business Machines Corporation Processor dependency-aware instruction execution

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000194556A (ja) 1998-12-23 2000-07-14 Tera Computer Co 命令ルックアヘッドシステムおよびハ―ドウェア
JP2003519833A (ja) 2000-01-03 2003-06-24 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 依存性連鎖の発行および再発行が可能なスケジューラ
US20100318995A1 (en) 2009-06-10 2010-12-16 Microsoft Corporation Thread safe cancellable task groups
WO2012045941A1 (fr) 2010-10-07 2012-04-12 Commissariat A L'energie Atomique Et Aux Energies Alternatives Systeme d'ordonnancement de l'exécution de taches cadence par un temps logique vectoriel

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6065105A (en) 1997-01-08 2000-05-16 Intel Corporation Dependency matrix
US6334182B2 (en) 1998-08-18 2001-12-25 Intel Corp Scheduling operations using a dependency matrix
US6557095B1 (en) 1999-12-27 2003-04-29 Intel Corporation Scheduling operations using a dependency matrix
US6877086B1 (en) 2000-11-02 2005-04-05 Intel Corporation Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter
US6981129B1 (en) 2000-11-02 2005-12-27 Intel Corporation Breaking replay dependency loops in a processor using a rescheduled replay queue
US6950927B1 (en) 2001-04-13 2005-09-27 The United States Of America As Represented By The Secretary Of The Navy System and method for instruction-level parallelism in a programmable multiple network processor environment
JP2007029421A (ja) 2005-07-27 2007-02-08 Aruze Corp 遊技機及び遊技システム
US20070043932A1 (en) 2005-08-22 2007-02-22 Intel Corporation Wakeup mechanisms for schedulers
CN101258469B (zh) 2005-09-05 2010-09-15 日本电气株式会社 信息处理设备
US8291431B2 (en) 2006-08-29 2012-10-16 Qualcomm Incorporated Dependent instruction thread scheduling
US9946547B2 (en) * 2006-09-29 2018-04-17 Arm Finance Overseas Limited Load/store unit for a processor, and applications thereof
US7979844B2 (en) 2008-10-14 2011-07-12 Edss, Inc. TICC-paradigm to build formally verified parallel software for multi-core chips
US8099582B2 (en) 2009-03-24 2012-01-17 International Business Machines Corporation Tracking deallocated load instructions using a dependence matrix
US8453146B2 (en) * 2009-12-23 2013-05-28 Intel Corporation Apportioning a counted value to a task executed on a multi-core processor
JP5548037B2 (ja) 2010-06-11 2014-07-16 パナソニック株式会社 命令発行制御装置及び方法
US20120023314A1 (en) 2010-07-21 2012-01-26 Crum Matthew M Paired execution scheduling of dependent micro-operations

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000194556A (ja) 1998-12-23 2000-07-14 Tera Computer Co 命令ルックアヘッドシステムおよびハ―ドウェア
JP2003519833A (ja) 2000-01-03 2003-06-24 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 依存性連鎖の発行および再発行が可能なスケジューラ
US20100318995A1 (en) 2009-06-10 2010-12-16 Microsoft Corporation Thread safe cancellable task groups
WO2012045941A1 (fr) 2010-10-07 2012-04-12 Commissariat A L'energie Atomique Et Aux Energies Alternatives Systeme d'ordonnancement de l'exécution de taches cadence par un temps logique vectoriel

Also Published As

Publication number Publication date
DE102014103188A1 (de) 2014-09-18
US20140281404A1 (en) 2014-09-18
JP6320801B2 (ja) 2018-05-09
US20160321079A1 (en) 2016-11-03
US9400653B2 (en) 2016-07-26
JP2018106760A (ja) 2018-07-05
CN104050215A (zh) 2014-09-17
US10552157B2 (en) 2020-02-04
JP2014179101A (ja) 2014-09-25
JP6604689B2 (ja) 2019-11-13
CN104050215B (zh) 2019-04-09
KR20140113304A (ko) 2014-09-24

Similar Documents

Publication Publication Date Title
KR102010312B1 (ko) 디펜던시들을 정리하고 리빌딩하는 시스템 및 방법
CN110688157B (zh) 一种计算装置及计算方法
TWI644208B (zh) 藉由對硬體資源之限制實現的向後相容性
TWI654562B (zh) 藉由演算法匹配、停用特徵或限制效能之回溯相容性
US9639369B2 (en) Split register file for operands of different sizes
US10459727B2 (en) Loop code processor optimizations
KR20080089313A (ko) 곱셈 기능을 수행하기 위한 방법 및 장치
JP2017107579A (ja) リードマスク及びライトマスクにより制御されるベクトル移動命令
US11531562B2 (en) Systems, methods, and apparatuses for resource monitoring
US20170024205A1 (en) Non-shifting reservation station
US9940139B2 (en) Split-level history buffer in a computer processing unit
US20170344372A1 (en) Power management of branch predictors in a computer processor
US20180024949A1 (en) Method of achieving low write latency in a data storage system
KR20150079429A (ko) 캐시 미시들에 대한 프로세서 읽기 후 쓰기 해저드를 다루기 위한 장치 및 그것의 동작 방법
US10592252B2 (en) Efficient instruction processing for sparse data
CN109564510B (zh) 用于在地址生成时间分配加载和存储队列的系统和方法
US20220027162A1 (en) Retire queue compression
KR20190092245A (ko) 엣지 특성이 검증된 마이크로 분기 타깃 버퍼를 이용하여 컴퓨터 프로세서의 전력 소모를 감소시키는 시스템 및 방법
US20170192896A1 (en) Zero cache memory system extension
US20180004516A1 (en) Administering instruction tags in a computer processor
US10540183B2 (en) Accelerated execution of execute instruction target
US10846095B2 (en) System and method for processing a load micro-operation by allocating an address generation scheduler queue entry without allocating a load queue entry
US20130046961A1 (en) Speculative memory write in a pipelined processor

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

A201 Request for examination
A302 Request for accelerated examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PA0302 Request for accelerated examination

St.27 status event code: A-1-2-D10-D17-exm-PA0302

St.27 status event code: A-1-2-D10-D16-exm-PA0302

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E90F Notification of reason for final refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20220706

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20240808

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20240808