DE102014103188A1 - System und Verfahren zum Löschen und Wiederherstellen von Abhängigkeiten - Google Patents

System und Verfahren zum Löschen und Wiederherstellen von Abhängigkeiten Download PDF

Info

Publication number
DE102014103188A1
DE102014103188A1 DE102014103188.1A DE102014103188A DE102014103188A1 DE 102014103188 A1 DE102014103188 A1 DE 102014103188A1 DE 102014103188 A DE102014103188 A DE 102014103188A DE 102014103188 A1 DE102014103188 A1 DE 102014103188A1
Authority
DE
Germany
Prior art keywords
entry
counter
entries
data processing
response
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE102014103188.1A
Other languages
German (de)
English (en)
Inventor
Ravi Iyengar
Sandeep Kumar DUBEY
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE102014103188A1 publication Critical patent/DE102014103188A1/de
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
DE102014103188.1A 2013-03-14 2014-03-11 System und Verfahren zum Löschen und Wiederherstellen von Abhängigkeiten Withdrawn DE102014103188A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/831,434 2013-03-14
US13/831,434 US9400653B2 (en) 2013-03-14 2013-03-14 System and method to clear and rebuild dependencies

Publications (1)

Publication Number Publication Date
DE102014103188A1 true DE102014103188A1 (de) 2014-09-18

Family

ID=51419103

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102014103188.1A Withdrawn DE102014103188A1 (de) 2013-03-14 2014-03-11 System und Verfahren zum Löschen und Wiederherstellen von Abhängigkeiten

Country Status (5)

Country Link
US (2) US9400653B2 (https=)
JP (2) JP6320801B2 (https=)
KR (1) KR102010312B1 (https=)
CN (1) CN104050215B (https=)
DE (1) DE102014103188A1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10198263B2 (en) 2015-09-19 2019-02-05 Microsoft Technology Licensing, Llc Write nullification
US11681531B2 (en) 2015-09-19 2023-06-20 Microsoft Technology Licensing, Llc Generation and use of memory access instruction order encodings
US10180840B2 (en) * 2015-09-19 2019-01-15 Microsoft Technology Licensing, Llc Dynamic generation of null instructions
US10031756B2 (en) 2015-09-19 2018-07-24 Microsoft Technology Licensing, Llc Multi-nullification
US10061584B2 (en) 2015-09-19 2018-08-28 Microsoft Technology Licensing, Llc Store nullification in the target field
US10185568B2 (en) * 2016-04-22 2019-01-22 Microsoft Technology Licensing, Llc Annotation logic for dynamic instruction lookahead distance determination
US11474821B1 (en) * 2021-05-12 2022-10-18 International Business Machines Corporation Processor dependency-aware instruction execution

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6065105A (en) 1997-01-08 2000-05-16 Intel Corporation Dependency matrix
US6334182B2 (en) 1998-08-18 2001-12-25 Intel Corp Scheduling operations using a dependency matrix
US6311266B1 (en) 1998-12-23 2001-10-30 Cray Inc. Instruction look-ahead system and hardware
US6557095B1 (en) 1999-12-27 2003-04-29 Intel Corporation Scheduling operations using a dependency matrix
JP2003519833A (ja) 2000-01-03 2003-06-24 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 依存性連鎖の発行および再発行が可能なスケジューラ
US6877086B1 (en) 2000-11-02 2005-04-05 Intel Corporation Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter
US6981129B1 (en) 2000-11-02 2005-12-27 Intel Corporation Breaking replay dependency loops in a processor using a rescheduled replay queue
US6950927B1 (en) 2001-04-13 2005-09-27 The United States Of America As Represented By The Secretary Of The Navy System and method for instruction-level parallelism in a programmable multiple network processor environment
JP2007029421A (ja) 2005-07-27 2007-02-08 Aruze Corp 遊技機及び遊技システム
US20070043932A1 (en) 2005-08-22 2007-02-22 Intel Corporation Wakeup mechanisms for schedulers
CN101258469B (zh) 2005-09-05 2010-09-15 日本电气株式会社 信息处理设备
US8291431B2 (en) 2006-08-29 2012-10-16 Qualcomm Incorporated Dependent instruction thread scheduling
US9946547B2 (en) * 2006-09-29 2018-04-17 Arm Finance Overseas Limited Load/store unit for a processor, and applications thereof
US7979844B2 (en) 2008-10-14 2011-07-12 Edss, Inc. TICC-paradigm to build formally verified parallel software for multi-core chips
US8099582B2 (en) 2009-03-24 2012-01-17 International Business Machines Corporation Tracking deallocated load instructions using a dependence matrix
US8959517B2 (en) 2009-06-10 2015-02-17 Microsoft Corporation Cancellation mechanism for cancellable tasks including stolen task and descendent of stolen tasks from the cancellable taskgroup
US8453146B2 (en) * 2009-12-23 2013-05-28 Intel Corporation Apportioning a counted value to a task executed on a multi-core processor
JP5548037B2 (ja) 2010-06-11 2014-07-16 パナソニック株式会社 命令発行制御装置及び方法
US20120023314A1 (en) 2010-07-21 2012-01-26 Crum Matthew M Paired execution scheduling of dependent micro-operations
FR2965948A1 (fr) * 2010-10-07 2012-04-13 Commissariat Energie Atomique Systeme d'ordonnancement de l'execution de taches cadence par un temps logique vectoriel

Also Published As

Publication number Publication date
US20140281404A1 (en) 2014-09-18
JP6320801B2 (ja) 2018-05-09
US20160321079A1 (en) 2016-11-03
US9400653B2 (en) 2016-07-26
JP2018106760A (ja) 2018-07-05
CN104050215A (zh) 2014-09-17
KR102010312B1 (ko) 2019-08-13
US10552157B2 (en) 2020-02-04
JP2014179101A (ja) 2014-09-25
JP6604689B2 (ja) 2019-11-13
CN104050215B (zh) 2019-04-09
KR20140113304A (ko) 2014-09-24

Similar Documents

Publication Publication Date Title
DE102014103188A1 (de) System und Verfahren zum Löschen und Wiederherstellen von Abhängigkeiten
DE112017000855B4 (de) Energiesparender zeitlich gemultiplexter neurosynaptischer Kern zum Implementieren neuronaler Netze
DE112009000741B4 (de) Vektorbefehle zum Ermöglichen von effizienter Synchronisation und parallelen Reduktionsoperationen
DE3781694T2 (de) Virtuelle prozessortechniken in einem feldmultiprozessor.
DE69904083T2 (de) Anordnung und verfahren zum etikettieren und ungültig-erklären von spekulativ ausgeführten befehlen
DE102023105572A1 (de) Effiziente Matrixmultiplikation und -addition mit einer Gruppe von Warps
DE102021127153A1 (de) System und verfahren zur implementierung einer netzwerkschnittstellenbasierten allreduce-operation
DE102012220267B4 (de) Rechenarbeitsverteilungs - Referenzzähler
DE102013208558A1 (de) Verfahren und System zur Verarbeitung verschachtelter Stream-Events
DE112019002981T5 (de) Parallelberechnungsarchitektur mit rekonfigurierbarer kernebenen- und vektorebenen-parallelität
DE102019112301A1 (de) Befehls-Cache in einem Multithread-Prozessor
DE102013200508B4 (de) Ersetzungsreihenfolge von Cache-Sets auf der Grundlage von zeitbezogener Set-Aufzeichnung
DE102023105554A1 (de) Schnelle Datensynchronisation in Prozessoren und Speicher
DE112020000865T5 (de) Speicherverwaltungssystem
DE102022105725A1 (de) Verfahren und einrichtungen zur durchführung von gewichtungs- und aktivierungskomprimierung und -dekomprimierung
DE112012005014T5 (de) Ausführen arithmetischer Operationen unter Verwendung sowohl von großen als auch kleinen Gleitkommawerten
DE112010003750T5 (de) Hardware für parallele Befehlslistenerzeugung
DE112012004747T5 (de) Verborgenes automatisiertes Spiegeln von Daten für native Schnittstellen in verteilten virtuellen Maschinen
DE102022103358A1 (de) Training für maschinelles lernen im logarithmischen zahlensystem
DE112020005987B4 (de) Computersystem und prozessor zum setzen von prüfpunkten in akkumulatorregister-ergebnissen in einem mikroprozessor
DE112017007656T5 (de) Verschobene aktualisierung von datenbank-hashcode in einer blockchain
DE112019000676T5 (de) Zentraler scheduler und anweisungszuteiler für einen neuronalen inferenzprozessor
DE112020005055T5 (de) Prozessoreinheit für multiplizier- und akkumulieroperationen
DE112013000687T5 (de) Verteilte Funktionsausführung für Hybridsysteme
DE112019000382T5 (de) GANZZAHLIGER MULTIPLIKATOR MIT MEHRFACHER GENAUIGKEIT DURCH MATRIX-MATRIX-MULTIPLIKATIONEN UNTER VERWENDUNG EINES 16-BIT-FLIEßKOMMA-MULTIPLIKATORS

Legal Events

Date Code Title Description
R012 Request for examination validly filed
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee