KR101966017B1 - Grinding control method and equipment for defect analysis of semiconductor device - Google Patents

Abstract

The present invention relates to a method and a device for controlling grinding to analyze a defect of a semiconductor device and, more specifically, to a method and a device for controlling grinding to analyze a defect of a semiconductor device, which enable accurate testing and defect analysis by corresponding to the curvature of a warp generated due to lamination of different materials during a process of exposing a predetermined layer to analyze the defect of the semiconductor device. Specifically, according to the present invention, an etching area and a non-etching area are divided by image processing after an exposed surface is photographed. Also, correction information on the non-etching area is calculated, and an additional etching process is performed. Therefore, rapid and accurate etching can be performed. Also, according to the present invention, after a brightness adjusting image of the photographed image is analyzed, the etching area and the non-etching area are divided by intensity and contrast. Also, the depth of the non-etching area is calculated, and, therefore, accurate and rapid etching can be performed. So, the method and the device for controlling grinding to analyze a defect of a semiconductor device can improve reliability and competitiveness in a defect analysis field of the semiconductor device, and, specifically, not only a defect analysis field of a high concentration device such as WLCSP but also in a semiconductor manufacture field, a yield improving field of the semiconductor device, and a similar or related field.

Description

Technical Field [0001] The present invention relates to a grinding control method and apparatus for defect analysis of semiconductor devices,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a grinding control method and apparatus for failure analysis of a semiconductor device, and more particularly, So that accurate test and defect analysis can be performed by etching according to the curvature of the warp.

Particularly, the present invention distinguishes the etching region from the non-etching region by image processing after photographing the exposed surface, calculates correction information for the non-etching region, and performs an additional etching process to thereby perform rapid and accurate etching To a grinding control method and apparatus for failure analysis of semiconductor devices.

In the manufacture of semiconductor devices, defects may occur due to various reasons such as high integration of devices and complicated manufacturing processes. Such defects may cause deterioration of performance and yield of semiconductor devices. We are making a lot of effort to do this.

Conventionally, failure analysis has been performed by measuring the operation of the internal circuit, operating characteristics, thermal characteristics, and the like through a terminal provided in the semiconductor package and testing the product.

However, the high performance, low power, and thin and light trend of electronic devices such as thinner wafers and increased input / output (I / O) terminals continue to lead to limitations of existing failure analysis methods.

Particularly, as the technology of WLCSP (Wafer Level Chip Scale Package) method, which is a method of manufacturing a package by mounting a solder ball as a bump ball directly on a wafer, has been developed, Respectively.

On the other hand, it is important not only to improve the functional aspects as described above, but also to improve the price competitiveness of the product, and yield is one of the factors that greatly affect the manufacturing cost of the semiconductor chip.

As a result, in order to increase the yield, it is necessary to precisely identify the cause of the defect, and the performance and the technology can be improved by this, so methods for analyzing the failure of the semiconductor device such as the WLCSP have been required.

The method proposed by this requirement is a method of exposing a specific layer of a semiconductor element which is defective through wet etching or dry etching and confirming an exposed die or conducting a direct test.

For example, Korean Patent Laid-Open Publication No. 1995-0021303 'Failure Analysis Method of Semiconductor Device' (hereinafter, referred to as 'Prior Art 1'), which is a prior art document, discloses an etching agent such as BOE (Buffered Oxide Etchant) The wet etching method used is to etch the semiconductor device, and then to identify the cause of the defect through the exposed part.

As another example, Korean Patent Laid-Open Publication No. 10-2005-0066170 'Failure Analysis Method of Semiconductor Device' (hereinafter, referred to as 'Prior Art 2'), which is a prior art document described below, Is the method of analyzing the failure of

However, in the same method as the prior art, the degree of etching varies depending on the etching conditions. Since the etching can be performed in a completely different manner due to the minute difference in the etching conditions, unnecessary etching may occur in an unexpected portion. There were many difficulties in obtaining the results.

As a supplement to this, Korean Patent Laid-Open Publication No. 10-2006-0016630 'Failure Analysis Method of Semiconductor Device' (hereinafter, referred to as 'Prior Art 3'), which is a prior art document described below, It is a method to remove exposed rare-earth which is required for analysis, and it has an advantage that it can perform precise etching compared to dry etching using wet etching or plasma.

On the other hand, in the case of the physical etching using the grinder as in the prior art 3, the grinder is operated by the previously inputted operation information to perform the etching.

In the case of a semiconductor device, warp is inevitably generated due to the characteristics of the material. Since the shape of this shape is difficult to predict at the design stage, setting the operation of the grinder considering the shape of the grinder It was impossible.

If a certain level of etching is performed on the target semiconductor device, the operator confirms this, and if the additional etching is required, the operation information for operating the grinder must be individually re-checked or the operator must manually control the grinder manually .

In the past, it was difficult to expect an accurate etching process in the case of a skilled worker, and therefore, the reliability analysis was also inferior in reliability analysis. Even in the case of skilled workers, Warp) is a very difficult process to visually check and accurately etch, which requires a lot of time and effort.

Korean Unexamined Patent Publication No. 1995-0021303 'Method of Failure Analysis of Semiconductor Device' Korean Patent Laid-Open Publication No. 10-2005-0066170 'Failure Analysis Method of Semiconductor Device' Korean Patent Laid-Open Publication No. 10-2006-0016630 'Method of analyzing defect of semiconductor device'

In order to solve the above-described problems, the present invention provides a method of manufacturing a semiconductor device, which comprises etching a semiconductor substrate in accordance with a curvature of a warp generated due to stacking of different materials in a process of exposing a specific layer, And an object thereof is to provide a grinding control method and apparatus for failure analysis of a semiconductor device capable of accurate test and failure analysis.

Particularly, the present invention distinguishes the etching region from the non-etching region by image processing after photographing the exposed surface, calculates correction information for the non-etching region, and performs an additional etching process. Thus, And an object of the present invention is to provide a grinding control method and apparatus for failure analysis of a semiconductor device.

In addition, the present invention is characterized in that after analyzing the brightness adjustment image of the photographed image, the etching region and the non-etching region are distinguished by the intensity and the contrast, and the depth of the non-etching region is calculated, And an object thereof is to provide a grinding control method and apparatus for failure analysis of a semiconductor device capable of rapid etching.

According to another aspect of the present invention, there is provided a grinding control method for failure analysis of a semiconductor device, the grinding control method including etching a surface of the semiconductor element etched and polished by a grinder, step; The control unit receiving the etched surface image photographed by the vision camera performs image processing of the etched surface image to confirm an exposed region and an unexposed region with respect to the etched surface of the semiconductor device and obtains a grinding correction amount for exposing the unexposed region Calculating correction information calculating step; And a correction grinding step of grinding the non-exposed area by controlling the operation of the grinder in accordance with the calculated amount of grinding correction.

Also, the correction information calculation step may include: an image adjustment process of image-processing the etched surface image to emphasize the brightness difference; And an area identification process for distinguishing the color information according to the material and the brightness difference of the etched surface image into an exposed area and an unexposed area.

The correction information calculation step may identify at least one of an intensity and a contrast of the brightness adjustment image with respect to the etched surface image to distinguish the exposed area from the unexposed area.

The correction information calculation step may further include an etching thickness checking step of checking at least one of an intensity and a contrast with respect to the unexposed area to confirm a depth to be etched.

In addition, the etching thickness checking process can identify the non-exposed regions by cells and the etching depth for each cell.

In the etching thickness checking process, the thickness of the silicon remaining in the unexposed area may be optically measured to determine the etching depth for each cell.

The etching surface photographing step may include a mold etching process for removing at least a part of a mold constituting an outer shape of the semiconductor device; A layer etching process for confirming the internal structure of the semiconductor device and etching the layer to a desired layer; And an etching surface photographing process of photographing the etched layer to acquire an image of the etched surface.

The layer etching process may include: a design information verification process of receiving and confirming a design drawing of the semiconductor device; A layer selection process for selecting a layer to be analyzed; And an etching information generating process for etching the layer to be exposed.

The layer etching process may include: a design information verification process of receiving and confirming a design drawing of the semiconductor device; An analysis point selection process of selecting at least one analysis point to be analyzed; And an etch information generation process for etching the layer corresponding to the analysis point to be exposed.

In addition, a grinding control apparatus for failure analysis of a semiconductor device according to the present invention includes: a grinder for etching one side of a semiconductor element; A vision camera for photographing an etched surface of the semiconductor element; And an etching surface image photographed by the vision camera, image processing the etching surface image to identify an exposed area and an unexposed area of the etching surface of the semiconductor device, and calculate a grinding correction amount for exposing the unexposed area And controlling the operation of the grinder in accordance with the calculated grinding correction amount to grind the unexposed area.

According to the present invention, by etching in correspondence with the curvature of warp generated due to lamination of different materials in a process of exposing a specific layer for the analysis of a defect of a semiconductor device, It is advantageous to perform an optimized etching to the structural characteristics of the product.

Accordingly, the present invention has an advantage that accurate testing and defect analysis of a semiconductor device can be performed by accurately exposing a desired layer.

Particularly, the present invention has an advantage that accurate extraction of the non-etched area is possible by distinguishing the etched area from the non-etched area by image processing after photographing the exposed surface.

On the basis of this, the present invention has an advantage that rapid and accurate etching can be performed by automation by calculating correction information for an un-etched area and performing an additional etching process.

In addition, the present invention is characterized in that after analyzing the brightness adjustment image of the photographed image, the etching region and the non-etching region are distinguished by the intensity and the contrast, and the depth of the non-etching region is calculated, There is an advantage that rapid etching can be performed.

In addition, the present invention is advantageous in that the semiconductor device is divided into a plurality of regions and etching is performed for each region, thereby enabling accurate defect analysis for semiconductor devices in which various layers such as a WLCSP are stacked.

Therefore, it is possible to improve the reliability and competitiveness in the field of defect analysis of semiconductor devices, in particular, defect analysis of highly integrated devices such as WLCSP, semiconductor manufacturing field, semiconductor device yield improvement field, and similar or related fields.

1 is a flowchart showing an embodiment of a grinding control method for failure analysis of a semiconductor device according to the present invention.
FIG. 2 is a flowchart showing another specific embodiment of step 'S200' of FIG.
FIG. 3 is a flowchart showing a specific embodiment of step 'S100' of FIG.
FIG. 4 is a flowchart showing a specific embodiment of step 'S120' of FIG.
FIG. 5 is a flowchart showing another embodiment of step 'S120' of FIG.
FIG. 6 is a view showing an etching process according to FIG. 2. FIG.
FIG. 7 is a view showing an etching process according to FIGS. 3 to 5. FIG.

First, the present invention is based on dry etching among methods of etching a semiconductor device, and in particular, it can be applied to an apparatus or a system that physically etches a dry element using a grinder.

To this end, the apparatus or system may include a vision camera for photographing an etching surface of a semiconductor device, and a control unit for controlling the operation of the grinder by performing image processing.

In addition, the control method according to the present invention can be performed by forming the vision camera and the control unit into one module and merely adding the corresponding module to the existing etching apparatus or system, and the effect can be obtained .

In addition, since etching can be performed through image recognition in various fields such as a process of manufacturing a semiconductor device and a field related to defect analysis, it can be widely used.

As described above, examples of the grinding control method and apparatus for failure analysis of a semiconductor device according to the present invention can be variously applied. In the following, the most preferred embodiments will be described with reference to the accompanying drawings.

1 is a flowchart showing an embodiment of a grinding control method for failure analysis of a semiconductor device according to the present invention.

Referring to FIG. 1, a grinding control method for failure analysis of a semiconductor device may include an etching surface photographing step (S100), a correction information calculating step (S200), and a correction grinding step (S300).

First, the controller according to the present invention photographs the etched surface of the semiconductor element etched and polished by a grinder with a vision camera (S100).

To this end, the control unit removes the EMC (Epoxy Mold Compound) forming the outer shape of the semiconductor device by using the grinder, and exposes an internal die (integrated circuit).

Thereafter, the control unit receives the etched surface image captured by the vision camera, implements the etched surface image, processes the exposed surface image of the etched surface of the semiconductor device according to whether the EMC or the inner silicon, Check the unexposed area.

If an unexposed area exists in at least a part of the etched surface, a grinding correction amount for the unexposed area is calculated (S200). Here, the grinding correction amount is for exposing the die hidden by the unexposed region, and may include grinding strength depending on the material of the etching object such as EMC or silicon, etching depth, and the like.

Thereafter, the control unit controls the operation of the grinder to grind the unexposed area according to the calculated grinding correction amount, thereby allowing the entire die of the layer to be exposed (S300).

Hereinafter, each step shown in FIG. 1 will be described in more detail.

FIG. 2 is a flowchart showing another specific embodiment of step 'S200' of FIG.

Referring to FIG. 2, the correction information calculating step S200 may include an image adjusting process S210, an intensity and contrast checking process S220, an area checking process S230, and an etching thickness checking process 240. FIG.

The control unit may process the etched surface image photographed in the etching surface photographing step (S100) to generate a brightness adjusted image in which the brightness difference is highlighted (S210).

In addition, the control unit may divide the exposed region normally exposed to the exposed surface and the unexposed region requiring additional etching based on the difference in brightness between the color information and the etched surface image according to the material (S230).

For example, the control unit can distinguish the exposed region from the unexposed region according to the color of materials such as EMC, silicon, and die.

On the other hand, as the thickness of the EMC of the semiconductor device or the thickness of the internal silicon varies, the brightness of the color depends on the material.

In operation S220, the controller may identify at least one of an intensity and a contrast of the brightness adjustment image for the etched surface image in operation S220, and may separate the exposed region from the unexposed region in operation S230.

In addition, the control unit can confirm at least one of the intensity and the contrast with respect to the unexposed area to determine the etching depth (remaining thickness) (S240).

In addition, the control unit can confirm the etching depth using an apparatus capable of optically measuring the thickness of the silicon remaining in the unexposed area, for example, a thickness monitor.

At this time, the controller can confirm the etch depth by cell.

In other words, the control unit can divide the unexposed regions into cells, and determine the etching depth for each cell (S200). Based on this, the additional grinding can be performed for each cell (S300).

FIG. 3 is a flowchart showing a specific embodiment of step 'S100' of FIG.

Referring to FIG. 3, the etching surface photographing step S100 may include a mold etching process S110, a layer etching process S120, and an etching surface photographing process S130.

As described above, at least a part of the mold constituting the outer shape of the semiconductor device is removed (S110), and the inner structure of the semiconductor device is confirmed and the desired layer is etched (S120).

Thereafter, the control unit may acquire an image of the etched surface by photographing the etched layer (S130).

Hereinafter, this will be described in more detail.

FIG. 4 is a flowchart showing a specific embodiment of step 'S120' of FIG.

Referring to FIG. 4, the controller may request and receive a design drawing of the semiconductor device in the layer etching process (S121).

When a layer to be analyzed is selected to identify the cause of the defect (S122), the controller may generate etching information to be etched so that the corresponding layer is exposed (S123).

At this time, the selection of the layer to be analyzed can be selected by the operator, and can be automatically selected based on the preset data sheet according to the type of defect generated.

On the other hand, a semiconductor device to be manufactured in recent years is manufactured in such a manner that modules having various functions are formed together based on a multi-layer structure like a WLCSP, and a point causing a defect is formed in a layer Dogs can exist.

Hereinafter, a grinding method for defect analysis for a semiconductor device having a multilayer structure and a multifunctional structure such as a WLCSP will be described.

FIG. 5 is a flowchart showing another embodiment of step 'S120' of FIG.

Referring to FIG. 5, the layer etching process S120 may include a design information verification process S121, an analysis point selection process S122 ', an etching region setting process S122 ", and an etching information generating process S123 have.

Specifically, the control unit confirms the design information for receiving and confirming the design drawing of the semiconductor device (S121), and then, at least one analysis point to be analyzed can be selected through input or input from the operator or set by the operator (S122 ').

At this time, when a plurality of selected analysis points are set and a plurality of analysis points exist in different layers, an etching area can be set for each analysis point (S122 ").

The controller may generate etching information to be etched so that the layer corresponding to the analysis point is exposed. If there are a plurality of analysis points, the controller may generate etching information for each region to etch a desired layer in each etching region (S123).

Hereinafter, a grinding control method for failure analysis of a semiconductor device according to the present invention will be described through an actual semiconductor element etching process.

FIG. 6 is a view showing an etching process according to FIG. 2, and FIG. 7 is a view showing an etching process according to FIG. 3 to FIG.

First, a target semiconductor device 100 includes a base layer 110, dies 131 to 134 stacked on the base layer 110, a silicon layer 135 formed between the dies, a semiconductor device 100 The molding layer 120 may be formed of a transparent resin.

First, in order to expose the dies 133 and 134 included in the target layer, it is possible to photograph the exposed surface after etching the molding layer 120 constituting the exterior.

6, when the same image as the right center portion of FIG. 6 is photographed, the brightness and brightness of the unexposed surface (blue portion) can be adjusted to confirm the etching region and the depth. For example, in the right image of FIG. 6, the correction information can be calculated so that the bright portion is a shallow portion to be etched and the dark portion is a deep portion to be etched, with the dark portions being etched.

6, etching the silicon layer 135 formed on the dies 133 and 134 while checking the degree of etching of the exposed surface through calculation of image recognition and correction information, 133 and 134 can be exposed.

If the desired die is present in a different layer, for example, as shown in FIG. 7, the die 133 stacked on the upper portion is exposed on the left portion, and the die 132 stacked on the lower portion is exposed on the right portion 7, the control unit etches the molding layer 120 constituting the exterior as shown in the center of FIG. 7, and further etches the die 134 located at the upper side relative to the right side as shown in FIG. 7 .

Thereafter, additional correction grinding can be performed so that the desired dies 132 and 133 are exposed through the calculation of the above-described image recognition and correction information.

Therefore, it is possible to more accurately and quickly identify the cause of defects in various patterns with respect to various semiconductor elements.

In the foregoing, a grinding control method and apparatus for failure analysis of semiconductor devices according to the present invention have been described. It will be understood by those skilled in the art that the technical features of the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.

It is to be understood, therefore, that the embodiments described above are in all respects illustrative and not restrictive.

Claims (10)

An etching surface photographing step of photographing an etched surface of a semiconductor element etched and polished by a grinder with a vision camera;
The control unit receiving the etched surface image photographed by the vision camera performs image processing of the etched surface image to confirm images of the exposed and unexposed areas of the etched surface of the semiconductor device, A correction information calculation step of calculating a grinding correction amount including at least one of a grinding strength and an etching depth according to a material of the etching surface for exposing the unexposed area based on at least one of a hue and a difference in brightness between unexposed areas; And
And a correction grinding step of grinding the non-exposed area by controlling the operation of the grinder in correspondence with the calculated amount of grinding correction by the controller.
The method according to claim 1,
Wherein the correction information calculating step
An image adjusting process of image-processing the etched surface image to highlight a brightness difference; And
And an area identification step of dividing the color information into the exposed area and the unexposed area based on the difference in color information between the material and the etched surface image.
3. The method of claim 2,
Wherein the correction information calculating step
Characterized in that at least one of an intensity and a contrast of the brightness adjustment image for the etched surface image is checked to distinguish the exposed area from the unexposed area. Way.
3. The method of claim 2,
Wherein the correction information calculating step
Further comprising a step of checking at least one of an intensity and a contrast with respect to the unexposed area to determine a depth to be etched. .
5. The method of claim 4,
The etching thickness checking process may include:
Wherein the non-exposed regions are divided into cells, and a depth to be etched is determined for each cell.
5. The method of claim 4,
The etching thickness checking process may include:
And optically measuring the thickness of the silicon remaining in the unexposed region to determine the etching depth for each cell.
The method according to claim 1,
The etching surface photographing step may include:
A mold etching process for removing at least a part of a mold constituting an outer shape of the semiconductor device;
A layer etching process for confirming the internal structure of the semiconductor device and etching the layer to a desired layer; And
And an etching surface photographing step of photographing the etched layer to obtain an image of the etched surface.
8. The method of claim 7,
The layer etching process includes:
A design information checking step of receiving and confirming a design drawing of the semiconductor element;
A layer selection process for selecting a layer to be analyzed; And
And an etching information generating step of etching the layer so that the layer is exposed.
8. The method of claim 7,
The layer etching process includes:
A design information checking step of receiving and confirming a design drawing of the semiconductor element;
An analysis point selection process of selecting at least one analysis point to be analyzed; And
And an etching information generating step of etching the layer corresponding to the analysis point to expose the layer corresponding to the analysis point.
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