CN114609502A

CN114609502A - Sample preparation method for observing failure region in failure analysis

Info

Publication number: CN114609502A
Application number: CN202011341189.2A
Authority: CN
Inventors: 林倖妍; 邓雅心; 唐忠毅
Original assignee: LUXNET CORP
Current assignee: LUXNET CORP
Priority date: 2020-11-25
Filing date: 2020-11-25
Publication date: 2022-06-10

Abstract

The invention discloses a sample manufacturing method for observing a failure area in failure analysis. Secondly, the protective glue is fixed on a small substrate at the peripheral points of the chip, so that the chip cannot be damaged during grinding. Next, the chip is fixed upside down on a supporting substrate. And finally, pouring unloading glue to fix the chip on a bearing substrate, and unloading the chip after judging the failure area in failure analysis so as to confirm the failure origin. The method can be used for manufacturing a sample for observing the failure area in failure analysis so as to confirm the subsequent chip structure and failure reason of the specific failure area.

Description

Sample manufacturing method for observing failure region in failure analysis

Technical Field

The invention relates to chip failure analysis, in particular to a sample manufacturing method for observing a failure area in the failure analysis.

Background

In recent years, as semiconductor devices have been rapidly developed, reliability of semiconductor devices has become more important. In order to improve the quality and life of the product, when the semiconductor devices fail in use or reliability verification, the cause of each semiconductor device failure must be found out, and then the semiconductor devices are optimized from raw materials or manufacturing processes, even from inspection equipment. Therefore, practical test platforms and techniques have been developed to find out the failure status of the semiconductor device to determine the failure mode of the device, and the practical test platforms such as Electroluminescent (EL), Electron Beam-induced Current (EBIC), or Optical Beam-induced Current (OBIC) are used to determine the failure area of the device.

For the failure mode analysis of the LD laser diode chip, one method is to use an Electroluminescence (EL) analyzer to determine the failure region, and further to determine the failure mode. However, the analysis using an Electroluminescence (EL) analyzer can only provide the failure area and the corresponding location, and cannot further find out the actual failure reason of the failure product. In most of the documents, the observation angle of the Electroluminescence (EL) analysis is from the bottom surface of the Laser Diode (LD) chip to the front surface, and therefore, most of the operators bury the chip or the element in the burying liquid by a burying technique and polish the chip or the element to a predetermined region by polishing. Because of the limitation of the detector material of the EL camera, the LD laser diode chip should remove the portion of the non-semiconductor material at the bottom to capture the EL image. Since the chip tilt is not easy to determine the EL dark area, the flatness of the sample is especially considered, and therefore, the portion of the LD laser diode chip where the non-semiconductor material on the bottom is removed is also considered to be the flatness of the sample, so that the chip is fixed on a substrate. However, if the chip failure analysis sample is detected to be defective at a certain position when the chip failure analysis sample photographs Electroluminescence (EL), and further detection is required by cutting the defective area, the entire analysis sample is too large in volume or the adhesive used for fixing the chip covers the defective position, and thus the analysis sample cannot be further detected. Therefore, a sample manufacturing method for observing failure regions in failure analysis is required to be able to manufacture an analysis sample for Electroluminescence (EL) photographing and to remove a chip so as to perform cutting and subsequent failure analysis for a specific failure region.

Disclosure of Invention

The invention aims to provide a sample manufacturing method for observing a failure area in failure analysis, which can manufacture an analysis sample detected by an instrument in advance and can remove a chip so as to carry out cutting and subsequent failure analysis on a specific failure area.

The present invention provides a sample manufacturing method for observing failure regions in failure analysis, which comprises the following steps, firstly, providing a chip for failure analysis. Secondly, the protective glue is fixed on a small substrate at the peripheral point of the chip, so that the chip can not be damaged during grinding. Next, the chip is fixed upside down on a supporting substrate. And finally, injecting unloading glue to enable the chip to be fixed on a bearing substrate, and unloading the chip after EL image confirmation for subsequent failure analysis.

Compared with the existing sample manufacturing method for observing the failure area in failure analysis, the method has the following advantages:

1. the protective glue is arranged on the periphery of the chip and fixed on a small substrate, so that the chip cannot be damaged when the chip is thinned by a grinding procedure or a failed chip frame caused by side corrosion of polishing solution has a conduction angle, and Electroluminescence (EL) is difficult to judge.

2. After the chip is unloaded, the specific failure area is cut, the subsequent chip structure is confirmed, and the failure true factor is searched.

Drawings

FIGS. 1-2 are schematic illustrations of a sample fabrication method of the present invention for observing failure zones in failure analysis;

FIG. 3 is a schematic view of a chip failure analysis sample after completion of failure zone analysis to enable removal of the chip;

FIG. 4 is a flow chart of a sample fabrication method of the present invention for observing failure zones in failure analysis.

Description of the symbols

10: chip and method for manufacturing the same

12: protective adhesive

14: small substrate

16: supporting substrate

18: pre-fixing glue

30: bridge is derived to electrical property

50: bearing substrate

100: electrochemical element

S10-S70: step (ii) of

Detailed Description

The method can be used for manufacturing an analysis sample detected by an instrument in advance and can be used for detaching the chip so as to cut a specific failure area and perform subsequent failure analysis.

Fig. 1 to 2 are schematic views illustrating a sample fabricating method for observing a failure region in failure analysis according to the present invention. First, as shown in FIG. 1, a chip 10 is provided and failure analysis will be performed. The chip 10 may be an LED light emitting diode chip, an LD laser diode chip, or an integrated circuit chip. Secondly, the protective glue 12 is fixed on a small substrate 14 at the periphery of the chip 10, so that the chip 10 is not damaged during grinding. The protective adhesive 12 is an AB adhesive, a UV adhesive, a silicone adhesive, or an epoxy resin, and can fix the chip 10 on the small substrate 14, and also prevent the chip 10 from being damaged by an external force due to polishing. The chip 10 can be protected from the bevel of the rim of the failed chip 10 caused by the side etching of the polishing liquid.

Next, as shown in fig. 2, the chip 10 is fixed upside down on a supporting substrate 16, and an electrically conductive bridge 30 is formed on a supporting substrate 50 to electrically connect with the chip 10. The chip 10 is fixed to the support substrate 16 using a pre-cure adhesive 18. Finally, the unloading glue 20 is poured to fix the chip 10 on the carrier substrate 50, thereby completing the fabrication of the chip failure analysis sample 100. The removable glue 20 is wax, hot melt glue, UV glue or embedding liquid. The chip failure analysis sample 100 enables the chip 10 to be removed after the failure analysis is completed.

The invention can grind the prepared chip failure analysis sample 100 off the small substrate 14, unload the glue 20 and part of the chip until the part of the non-semiconductor material at the bottom of the chip is completely removed, then polish the chip, and then carry out Electroluminescence (EL) shooting, Electron Beam-induced Current (EBIC) analysis or Optical Beam-induced Current (OBIC) analysis.

Fig. 3 is a schematic diagram showing that the chip can be removed after the failure area analysis is completed on the chip failure analysis sample, and as shown in fig. 3, the small substrate 14 and the removal glue 20 above the chip 10 and part of the chip to the bottom of the chip, which is not a semiconductor material, are completely removed and then polished, so that the semiconductor layer of the chip 10 is exposed, and then the chip 10 can be removed. After the chip 10 is removed, the specific failure region can be cut and subsequently analyzed for failure. The structure inside the sample was analyzed as transmission electron microscopy, TEM.

FIG. 4 is a flow chart of a sample fabrication method of the present invention for observing failure zones in failure analysis. First, a chip is provided and failure analysis is performed, as shown in step S10. Next, a protective adhesive is applied around the chip and fixed on a small substrate, so that the chip will not be damaged during polishing, as shown in step S20. Next, the chip is fixed upside down on a supporting substrate as shown in step S30. Next, a discharging glue is poured in to fix the chip on a carrier substrate, as shown in step S40. Next, the semiconductor layer of the chip is polished until exposed, as shown in step S50. Next, a failure region determination is made for the chip for a small current, as shown in step S60. Finally, if the chip is to be analyzed, the chip is taken out from the unloading glue, as shown in step S70.

Claims

1. A method of making a sample for viewing failure zones in failure analysis, comprising the steps of:

providing a chip to be subjected to failure analysis;

the protective glue is fixed on the small substrate at the periphery of the chip, so that the chip is not damaged during grinding;

fixing the chip on a support substrate in an inverted manner; and

and pouring unloading glue to fix the chip on the bearing substrate, and unloading the chip after judging the failure area in failure analysis so as to confirm the failure reason.

2. The method of claim 1, wherein the protective adhesive is AB adhesive, UV adhesive, silicone adhesive or epoxy resin, and protects the chip from lateral erosion of the polishing solution, which may cause a corner on a frame of the failure analysis sample of the chip.

3. The method of claim 1, wherein the chip is mounted upside down on the supporting substrate by using a pre-cure adhesive.

4. The method of claim 1, wherein the removable adhesive is wax, hot melt adhesive, UV adhesive, or embedding fluid.

5. The method of claim 1, wherein the chip is an LED chip, an LD chip or an ic chip.

6. The method of claim 1, further comprising forming an electrically conductive bridge on the carrier substrate to electrically connect the chip.

7. The method of claim 1, further comprising grinding and polishing a failure analysis sample of the die, and performing an electroluminescence (el) photography, an Electron Beam Induced Current (EBIC) analysis, or an Optical Beam Induced Current (OBIC) analysis.

8. The method of claim 8, further comprising polishing after grinding to expose the semiconductor layer of the die.

9. The method of claim 1, further comprising cutting and subsequent failure analysis of the specific failure region after the step of detaching the chip.

10. The method of claim 9, further comprising determining the failure region for a small current applied to the chip.