JP2008171924A - Semiconductor wafer, test device, test method for semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer having an image-capturing element formed thereon, which semiconductor wafer allows an electric test to be conducted efficiently on the wafer without deteriorating the quality of the wafer. <P>SOLUTION: An image-capturing element 5 and a main surface side electrode 3 are formed on the main surface side of a semiconductor substrate 1, to which a reinforcing plate 2 capable of transmitting light in a frequency range that makes light receivable to the image-capturing element 5 is pasted via an adhesive resin 4. The back surface side of the semiconductor substrate 1 is polished, and then a through-hole 6 is so formed on the back surface side that the surface of the main surface side electrode 3 exposes to the through-hole 6, in which a conductive material is formed to form a back surface side electrode 8 on the back surface, the electrode 8 being connected electrically to the main surface side electrode 3 via the conductive material. The semiconductor wafer is constructed in this manner, and test subject light is emitted on the semiconductor wafer from the main surface side while a measuring prove is brought into contact with the semiconductor wafer from the back surface side. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer on which an image sensor is formed, a test method thereof, and a test apparatus for testing a semiconductor wafer.

  In a semiconductor element that is assumed to receive an optical signal from the main surface side where the element region is formed, such as an imaging element, it is necessary to perform wiring so as not to interfere with the path of incident light. For this reason, in recent years, the connection between the element region and the power supply line, the ground line, or each input / output signal line is not a connection method by wire bonding, but the back surface facing the main surface of the semiconductor wafer on which the imaging element is formed. A connection method has been developed in which a direct connection is made to a lower-layer semiconductor element or wiring board through a through-hole and a contact pad penetrating to the bottom.

  When a semiconductor wafer having such a through hole (penetration mechanism) is manufactured, the wafer back surface is polished and the wafer is thinned in the penetration process, so that the mechanical strength of the wafer is lowered. For this reason, in order to reinforce mechanical strength, it usually has a process of attaching a reinforcing plate to the main surface of the wafer.

  However, in a state where the reinforcing plate is attached to the main surface of the wafer, it is impossible to make electrical contact from the main surface of the wafer, so that an electrical test in the wafer state cannot be performed. For this reason, even in the case of a semiconductor wafer having a penetrating mechanism, an electrical test is performed by probing from the main surface side before performing the penetrating process, as in the case of a normal wafer having no penetrating mechanism. And the contact pad for taking an electrical contact from the main surface side was attached to the main surface side wafer surface. Thus, an example of the configuration of a semiconductor chip provided with a through hole penetrating from the main surface to the back surface of the wafer and contact pads on both the back surface side and the main surface side is disclosed in Patent Document 1 below.

  FIG. 11 shows a configuration example at the time of testing the semiconductor chip disclosed in Patent Document 1. The semiconductor chip 91 has contact pads 92 on the main surface side (notation A side in FIG. 11) and also has contact pads (not shown) on the back surface side (notation B side in FIG. 11). Contact pads are connected through a conductive material formed in a through hole penetrating the chip from the main surface side to the back surface side. On the back side of the semiconductor chip 91, a wiring substrate 93 having contact pads and electrical contacts formed on the back side is formed. The semiconductor chip 91 having such a configuration is placed on the test substrate 95, and is used for measurement on both the test electrode 96 on the test substrate 95 and the predetermined main surface side contact pad 92 on the semiconductor chip 91. The electrical characteristics of the semiconductor chip 91 are tested by contacting the probes P1 and P2 and measuring a physical quantity obtained under a predetermined test condition with a prober. The wiring board 93 has a bump 94 formed on the back surface side (B side), and an electrical contact between the test electrode 96 and the wiring board 93 can be formed via the bump 94.

JP 2003-92375 A

  According to the configuration shown in FIG. 11, the semiconductor chip 91 having the wiring substrate 93 formed on the back side is placed at a predetermined position on the test substrate 95, and the test electrode 96 on the test substrate 95 is provided. By bringing the measurement probes into contact with the main surface side contact pads 92 on the semiconductor chip 91, an electrical test before the package becomes possible.

  However, in the configuration of FIG. 11, in order to make electrical contact from the back surface side, a contact portion (through hole and conductive material formed in the through hole) penetrating the main surface side and the back surface side is formed. Since the wiring substrate 93 is laminated on the back side of the semiconductor chip 91, the electrical test can be performed on the semiconductor chip 91 in a state where the wiring substrate 93 is laminated, but the wiring substrate 93 is laminated. It is not possible to perform an electrical test on the semiconductor chip 91 alone (wafer state) in a state in which it is not. For this reason, the test of the wafer state after the end of the penetration process cannot be performed. Further, since the test is performed in a state where the wiring substrate 93 is laminated, if a conduction failure occurs when the wiring substrate 93 is formed, a plurality of elements formed on the chip 91 are in a defective state. End up.

  Furthermore, in the configuration of FIG. 11, it is necessary to provide the contact pad 92 on the main surface side. When an image sensor is formed in the main surface side element region of the semiconductor chip 91, the formation position of the contact pad 92 is the image sensor. On the other hand, since it is necessary to arrange it so as not to interfere with the incident light, there is a great restriction on the arrangement position.

  In addition, when an electrical test is performed on a semiconductor chip on which the image sensor is formed on the main surface side, when performing a test on the image sensor, test light is incident on the image sensor from the chip main surface side. It is necessary to let Therefore, when probing from the main surface side while the test light is incident from the main surface side, the contact needle itself of the measuring probe in addition to the contact pad is electrically charged under the conditions that do not prevent the test light from entering. As a result, the number of image pickup devices that can be subjected to electrical tests is greatly limited.

  Further, when probing is performed from the main surface side to the semiconductor chip on which the image pickup element is formed on the main surface side, it occurs from the contact portion between the metal film surface of the main surface side contact pad and the contact needle of the measurement probe Metal dust (probe dust) adheres to the light receiving region of the image sensor, which may reduce the light receiving capability of the image sensor and cause image abnormality (black defect).

  In view of the above problems, the present invention provides a semiconductor wafer on which an image sensor is formed, and capable of performing an electrical test efficiently without causing quality degradation. Objective. Furthermore, the present invention provides a test method and a test apparatus for a semiconductor wafer that enables an electrical test to be performed efficiently without degrading the quality of the semiconductor wafer on which an image sensor is formed. With the goal.

  In order to achieve the above object, a semiconductor wafer according to the present invention is a semiconductor wafer on which an image sensor is formed, and includes an element region including the image sensor and a first electrode that forms an electrical contact with the element region. A reinforcing plate that has a main surface side and a second electrode on the back surface opposite to the main surface side and that transmits light in a frequency range that can be received by the imaging device is bonded to the main surface side. The first electrode and the second electrode are electrically connected via a conductive material formed so as to penetrate the main surface side and the back surface side.

  According to the above characteristic configuration of the semiconductor wafer according to the present invention, the test target light is irradiated from the main surface side where the imaging element is formed, and is formed on the back surface side opposite to the main surface. By bringing the two electrodes into contact with the measurement probe, a physical quantity corresponding to the amount of light received by the image sensor can be measured, and the state of the semiconductor wafer can be determined based on the measurement result. That is, when performing an electrical test of a semiconductor wafer, it is not necessary to contact the measurement probe from the imaging element forming side, so that the amount of probe dust attached to the light receiving region of the imaging element can be greatly reduced. As a result, an electrical test that was previously possible only before the penetration process can be performed after the completion of the penetration process, so tests including processing defects that occur in the penetration process can be performed, reducing process defects. It becomes possible to make it.

  Note that the reinforcing plate provided in the semiconductor wafer according to the present invention has a property of transmitting light in a frequency range that can be received by the imaging device. Therefore, after the test process is completed, each chip after dicing is packaged in the subsequent mounting process. Since it can be used as a lid glass for closing the opening in order to keep confidentiality in the package, it is not necessary to remove the reinforcing plate after the end of the test. A process of bonding is also unnecessary. For this reason, a part of process process can be simplified.

  In order to achieve the above object, a test apparatus according to the present invention is a test apparatus for testing a semiconductor wafer in which an element region including an image sensor is formed on a first wafer surface, the semiconductor wafer comprising: A wafer stage for mounting, and a probe card for bringing a measurement probe into contact with a predetermined electrode formed on the second wafer surface opposite to the first wafer surface on the opposite surface of the wafer stage And a light incident means for entering target light in a frequency range that can be received by the imaging device with respect to the first wafer surface, and at least the semiconductor wafer is mounted on the wafer stage The semiconductor wafer having the property of transmitting the target light in the mounting region and mounting the target light incident from the light incident means on the wafer stage It is a first feature of the of the is configured to be irradiated with the first image pickup devices formed on the wafer surface.

  According to the first characteristic configuration of the test apparatus according to the present invention, the semiconductor wafer is placed on the wafer stage so that the second wafer surface faces the probe card, and comes into contact with the wafer stage surface from the light incident means. Electricity of a semiconductor wafer having an imaging device on the first wafer surface is obtained by irradiating target light onto the first wafer surface side and bringing a measurement probe provided on the probe card into contact with an electrode on the second wafer surface. The physical test can be performed without contacting the measurement probe from the imaging element forming side. That is, according to the first characteristic configuration of the test apparatus according to the present invention, the target semiconductor wafer is configured in advance to have the same configuration as the above-described semiconductor wafer according to the present invention, so that the imaging device is formed. It is possible to perform an electrical test of the semiconductor wafer without bringing the measuring probe into contact.

  In addition to the first characteristic configuration, the test apparatus according to the present invention is configured such that the light incident means is separated from the wafer stage by a predetermined distance in a direction opposite to the probe card installation side. A plurality of light emitting elements arranged in parallel with a stage surface; and the plurality of light emitting elements and the wafer stage for diffusing emitted light from the plurality of light emitting elements to the first wafer surface of the semiconductor wafer. And a diffusion plate interposed between the two.

  According to the second characteristic configuration of the test apparatus according to the present invention, the radiation light from the light emitting element can be reliably irradiated to the imaging element of the semiconductor wafer placed on the wafer stage. The reliability of the test result when the electrical test is performed on the wafer can be improved.

  In addition to the first or second characteristic configuration, the test apparatus according to the present invention may include an alignment adjustment electrode or an alignment adjustment electrode on the second wafer surface that is not electrically connected to the element region. A third feature is that it includes an alignment means for recognizing the formation position of the insulating film and setting the placement position on the wafer stage based on the recognition result.

  According to the third characteristic configuration of the test apparatus according to the present invention, since the semiconductor wafer to be tested is mounted on the wafer stage based on the mounting position set by the alignment means, the wafer There is no need to adjust the placement position by moving the semiconductor wafer after it is placed on the stage. For this reason, the wafer stage surface is not physically damaged by the position adjustment action of the semiconductor wafer, and it is possible to reliably irradiate the target light from the light incident means to the image pickup device included in the semiconductor wafer after placement. it can. Further, when a reinforcing plate that transmits light is bonded to the first wafer surface of the semiconductor wafer, the reinforcing plate is not physically damaged in the same manner as the wafer stage surface.

  In addition to the third characteristic configuration, the test apparatus according to the present invention has a vacuum groove on the wafer stage for fixing the semiconductor wafer placed on the wafer stage by vacuum suction. The alignment means recognizes a non-light-receiving region on the first wafer surface of the semiconductor wafer based on the recognition result of the formation position of the alignment adjustment electrode or the alignment adjustment insulating film, and A fourth feature is that the mounting position of the semiconductor wafer on the wafer stage is set so that the light receiving region faces the vacuum groove.

  According to the fourth characteristic configuration of the apparatus of the present invention, the mounting position is set by the alignment means so that the opposing region of the vacuum groove is a non-light-receiving region on the first wafer surface. Since the light emitted from the light incident means is blocked by the presence of the light, a situation in which a sufficient amount of target light is not irradiated to the image sensor does not occur. Therefore, a highly reliable test result can be obtained by irradiating the semiconductor wafer with the target light from the light incident means while stably fixing the semiconductor wafer on the wafer stage by vacuum suction. it can.

  The test method according to the present invention is a test method for conducting an electrical test on a semiconductor wafer having the above-described characteristic configuration, and is a test target for the test apparatus having the above-described third or fourth characteristic configuration. When the semiconductor wafer is set, the test apparatus places the semiconductor wafer to be tested on the wafer stage so that the wafer surface on the back side faces the probe card according to the mounting position set by the alignment means. The main surface of the semiconductor wafer is caused to enter the light from the light incident means on the main surface side of the semiconductor wafer, and the probe card contacts the predetermined second electrode and the measurement probe. A physical quantity corresponding to the amount of light received by the image sensor formed on the side is measured, and the state of the semiconductor wafer is determined based on the measurement result And wherein the door.

  According to the above characteristics of the test method according to the present invention, it is possible to efficiently perform an electrical test on a semiconductor wafer after completion of the penetration process without deteriorating quality.

  According to the present invention, it is possible to provide a semiconductor wafer provided with an image pickup device and capable of performing an electrical test efficiently without causing deterioration in quality. In addition, it is possible to efficiently perform an electrical test on a semiconductor wafer on which an image sensor is formed without degrading quality.

  Hereinafter, a semiconductor wafer according to the present invention (hereinafter referred to as “the present invention wafer” as appropriate), a test apparatus according to the present invention (hereinafter referred to as “the present invention apparatus” as appropriate), and a test of the semiconductor wafer according to the present invention. A method (hereinafter referred to as “the method of the present invention” as appropriate) will be described with reference to the drawings.

[Description of the Wafer of the Present Invention]
Hereinafter, the configuration of the wafer of the present invention and the manufacturing method thereof will be described with reference to FIGS. FIG. 1 is a diagram showing a manufacturing process when manufacturing a wafer of the present invention, and a schematic cross-sectional structure diagram is shown in the order of the manufacturing process. FIG. 2 is a flowchart of the above manufacturing process, and each step in the following sentence represents each step of the flowchart shown in FIG.

  Note that each schematic cross-sectional structure diagram in FIG. 1 is merely schematically illustrated, and the scale of the actual structure does not necessarily match the scale of the drawing. In FIG. 1, the upper direction on the paper is the main surface side, and the lower direction is the back surface side.

  First, as shown in FIG. 1A, an adhesion is made on the same main surface side of a semiconductor substrate (semiconductor wafer) 1 in which an image sensor 5 and a main surface side electrode (first electrode) 3 are formed on the main surface side. The reinforcing plate 2 is pasted through the resin 4 (step # 1). The reinforcing plate 2 has a property of transmitting light in a frequency range that can be received by the image sensor 5 and can be made of, for example, quartz glass. The reinforcing plate 2 also has a function as a lid glass for closing the opening in order to keep confidentiality in the package when each chip after dicing is stored in a package or the like in a later step.

  Next, as shown in FIG. 1B, the back side of the semiconductor substrate 1 is polished and thinned (step # 2).

  Next, in order to manage the semiconductor wafer by irradiating a pulse laser to a predetermined position on the back surface side of the semiconductor substrate 1 (however, it is set as an area other than an area where a through hole is formed in Step # 4 described later). Is written (step # 3). The wafer ID may be written in two-dimensional code format or barcode format in addition to alphanumeric characters.

  The wafer ID written in step # 3 is for recognizing a target wafer to be tested by a test apparatus (prober apparatus) used in the test process, and is a number that can be managed for each wafer. I just need it.

  Next, as shown in FIG. 1C, the through hole 6 is formed on the back surface side of the substrate 1 so that the back surface side of the electrode 3 is exposed (step # 4). Thereafter, as shown in FIG. 1 (d), after depositing an insulating film 7 on the entire back surface side, an etch back is applied to form a conductive material in the through hole 6 with the main surface side electrode 3 exposed. Then, the back surface side electrode 8 (second electrode) having electrical connection with the main surface side electrode 3 is formed on the back surface side (step # 5).

  FIG. 3 is a schematic diagram showing a schematic configuration of the semiconductor wafer 1 formed through the steps # 1 to # 5, and FIG. 4 shows a plurality of chips constituting the semiconductor wafer 1 shown in FIG. It is the figure which expanded one chip | tip C1 of the inside. 3 and 4, the upper direction on the paper is the back side, and the lower direction is the main surface side.

  As shown in FIG. 3, the wafer 1 of the present invention has a reinforcing plate 2 attached to the back surface side, and a wafer marking region 12 in which a wafer ID for managing the wafer 1 is written is formed on the main surface side. Has been.

  After step # 5, an alignment adjustment mark 14 and a test electrode 16 to be described later are formed in a predetermined region on the back side of the wafer 1. The alignment adjustment mark 14 serves as an adjustment means for adjusting the installation position on the test apparatus when the wafer 1 is installed on the test apparatus and an electrical test is performed. An insulating material or an insulating material may be used. In addition, when comprised with an electroconductive material, it is necessary to be electrically insulated from the element area | region containing the image pick-up element 5. FIG. Further, the arrangement position and pattern shape of the mark 14 are not particularly limited as long as they are within a range that can be used when adjusting the installation position on the test apparatus. In FIG. 4, the case where the mark 14 is given in L shape at each four corners on the chip C1 is illustrated.

  5 and 6 are diagrams schematically showing an electrical connection relationship between the back surface side electrode 8 and the main surface side electrode 3 when the test electrode 16 is formed on the back surface of the wafer 1. FIG. Similarly to FIG. 4, the upper direction on the paper is shown as the back surface side, and the lower direction is shown as the main surface side.

  As described above, the back surface side electrode 8 formed on the back surface of the wafer 1 is formed in the through hole 6 with the main surface side electrode 3 formed on the main surface side opposite to the wafer 1. It is electrically connected through a conductive material. When performing an electrical test, the measurement probe P1 may be in contact with the back surface side electrode 8 as shown in FIG. 5, or the back surface side as shown in FIG. It is good also as a structure which contacts the probe P1 for a measurement with the electrode 16 for a test formed in another position, having an electrical connection with the electrode 8. FIG. As shown in FIG. 6, by separating the back surface side electrode 8 and the contact position of the measurement probe P <b> 1, the probe mark formed at the probe contact portion is formed on the back surface side electrode 8 by performing an electrical test. It can be avoided. It is also useful when the size of the back electrode 8 is not large enough to contact the probe P1.

[Description of the Invention Device and the Invention Method]
Next, the apparatus of the present invention for performing an electrical test on the above-described wafer of the present invention and the method of the present invention for performing an electrical test using the apparatus of the present invention will be described below with reference to FIGS. explain.

  FIG. 7 is a schematic diagram showing a schematic configuration of the device 20 of the present invention. The inventive apparatus 20 includes a wafer loader 21, an alignment unit 22, a probe card 23, a wafer stage 24, a light incident unit 25, and a control unit 26 that controls each component unit.

  A wafer to be tested is set on the wafer loader 21. Then, one wafer 1 selected from the plurality of wafers set in the wafer loader 21 is sent to the alignment means 22.

  The alignment means 22 recognizes the alignment adjustment mark 14 formed on the back side of the wafer 1 and positions the wafer 1 on the wafer stage 24. The wafer 1 is placed on the wafer stage 24 according to the positioning determined by the alignment means 22. At this time, the stage surface of the wafer stage 24 and the main surface of the wafer 1 are brought into contact with each other, and the wafer 1 is placed so that the back surface side of the wafer 1 faces the probe card 23. Thereby, the main surface side of the wafer 1 faces the light incident means 25.

  FIG. 8 is a diagram showing a schematic configuration of the wafer stage 24 and the light incident means 25. 8A is a plan view of the wafer stage 24, FIG. 8B is a cross-sectional view taken along the line L1-L1 ′ in FIG. 8A, and FIG. 8C is the view in FIG. Cross-sectional views cut along a straight line L2-L2 ′ are respectively shown. It is assumed that a vacuum groove 31 described later is formed on the straight line L1-L1 ', and no vacuum groove 31 is formed on the straight line L2-L2'.

  As shown in FIG. 8A, the wafer stage 24 has a vacuum groove 31 on the cross shape for fixing the semiconductor wafer to be placed by vacuum suction. Further, as shown in FIG. 8B, a suction port for giving a negative pressure state from the vacuum suction device to the vacuum groove 31 between the vacuum groove 31 and a vacuum suction device (not shown). 32 are provided at predetermined intervals. That is, as a result of the negative pressure state from the vacuum suction device installed below the wafer stage being given to the vacuum groove 31 via the suction port 32, the semiconductor wafer placed on the wafer stage 24 is placed in the vacuum groove 31. It is a structure fixed by being adsorbed. At this time, for example, if the vacuum groove 31 has a width of 1 mm, a depth of 1 mm, and a length of 150 mm, and the suction port 32 has a diameter of about 1 mm, a 200 mm wafer can be sucked and fixed.

  Further, as shown in FIG. 8C, the light incident means 25 is accommodated in the housing 40, and light emission in which a plurality of light emitting elements (for example, LED elements) 41 arranged at a predetermined interval is formed. The body mounting substrate 42 is mounted at a predetermined distance from the wafer stage 24. A light diffusing plate 43 for diffusing incident light is formed between the wafer stage 24 and the light emitter mounting substrate 42, and the wafer on which the radiated light from the light emitting element 41 is placed on the wafer stage 24. It is configured to be able to enter an image pickup device that is diffused on the surface and formed on the wafer. As the light diffusing plate 43, for example, an acrylic plate or an optical polycarbonate resin plate can be used. The wafer stage 24 is placed on the semiconductor wafer 1 so that the image sensor formed on at least the main surface side of the semiconductor wafer 1 placed thereon is irradiated with the radiated light from the light incident means 25. Is configured to transmit the radiated light.

  Here, the light emitting element 41 preferably has a mounting interval as narrow as possible and a separation distance to the light diffusion plate 43 as much as possible in order to make the degree of light emission uniform. For example, in the case of the dimension example of the vacuum groove 31 and the suction port 32 described above, as an example, the LED elements can be mounted at intervals of 3 mm, and the separation distance between the light emitter mounting substrate 42 and the light diffusion plate 43 can be set to about 6 mm. . Furthermore, in order to improve the uniformity of the light emission level, a plurality of light diffusion plates 43 may be installed in parallel with a predetermined separation distance secured.

  In addition, a transparent protective plate 44 for protecting the light emitting element 41 is formed between the mounting substrate 42 and the wafer stage 24. For example, quartz glass can be used as the protective plate 44. The wafer stage 24 itself may be made of quartz glass so that the wafer stage 24 also serves as the protection plate 44.

  The case where an electrical test of the wafer 1 of the present invention is performed using the apparatus 20 of the present invention configured as described above will be described below. FIG. 9 is a flowchart of the test process, and each step in the following sentence represents each step of the flowchart shown in FIG.

  First, before setting the wafer 1 of the present invention, wafer data such as the formation positions of the alignment adjustment marks 14 and the test electrodes 16 are registered in advance in the apparatus 20 of the present invention (step # 11).

Next, the reinforcing plate 2 is formed on the main surface side, the alignment adjustment mark 14 and the test electrode 16 are formed on the back surface side, and the wafer 1 of the present invention with the wafer ID attached to the back surface side, the back surface side is the probe contact surface. Is attached to the device 20 of the present invention (step # 12). Here, when the apparatus 20 of the present invention has a wafer ID recognition function, the wafer to be tested is identified by reading the wafer ID attached to the back surface of the mounted wafer 1 of the present invention. be able to. When the wafer ID recognition function is not provided, the wafer is identified by visually confirming the wafer ID.

  The mounted wafer of the present invention 1 to be tested is set by the alignment means 22 for the position and direction when placed on the wafer stage 24 (step # 13). At this time, the alignment means 22 recognizes the formation positions of the alignment adjustment mark 14 and the test electrode 16 formed on the back side of the wafer 1 of the present invention based on the wafer data given from the control means 26, and recognizes the recognition. The position and direction are determined based on the result. At this time, for example, the alignment means 22 recognizes the scribe line position and the non-light-receiving area from the position where the alignment adjustment mark 14 is formed, and the non-light-receiving area is formed in a cruciform shape on the wafer stage 24. The control can be performed so as to be positioned at the 31 cross-point portions.

  The wafer 1 of the present invention is placed on the wafer stage 24 according to the position and direction set by the alignment means 22 in step # 13 (step # 14). At this time, by operating a vacuum suction device (not shown), the wafer 1 is adsorbed on the stage 24 by the vacuum groove 31, and thereby the wafer 1 is fixed on the stage 24.

  When the wafer 1 of the present invention to be tested is placed on the wafer stage 24, the light incident means 25 irradiates the main surface side of the wafer 1 under predetermined test conditions, and the back surface of the wafer 1 is irradiated. The physical quantity is measured by bringing the measurement probes P1 and P2 included in the probe card 23 from the side into contact with predetermined electrodes (back surface side electrode 8 and test electrode 16) (step # 15). By the step # 15, the probe card 23 measures a physical quantity corresponding to the amount of light emitted from the light incident means 25 by the imaging device 5 formed on the main surface side of the wafer 1. Then, state determination means (not shown) determines the state of the wafer 1 based on the physical quantity measured in step # 15 (step # 16).

  By performing such step # 11 to step # 16 for all of the plurality of wafers set in the wafer loader 21, for example, only the wafer determined to be in a good state in step # 16 is advanced to the next process. As a result, the yield of products can be improved.

  According to the above-described method, the measurement probes P1 and P2 are in contact with the back surface side opposite to the main surface on which the image sensor 5 is formed, so that the wafer map data indicating the state of the wafer 1 is obtained. May output data obtained by converting into coordinate information viewed from the main surface side.

  The wafer 1 that has completed the test process uses the reinforcing plate 2 as a lid glass. Therefore, after dicing with the reinforcing plate 2 attached to the main surface side, wafer level CSP (Chip Scale Package), etc. The conventional mounting method is used to perform solder mounting on the mounting substrate. An example of the structure after mounting is shown in FIG. FIG. 10 shows an example in which the chip 1 is mounted on the mounting substrate 51 via the bumps 52. Since the reinforcing plate 2 that has been bonded and formed in advance is used as the lid glass, a step of attaching the lid glass separately becomes unnecessary.

  According to the configuration of the wafer 1 of the present invention and the apparatus 20 of the present invention as described above, the test electrode 16 is provided on the back surface side different from the wafer main surface side on which the imaging element 5 is formed in advance. The measurement probe can be brought into contact with the probe card 23 from the back side of the wafer while irradiating test light for performing an electrical test by the light incident means 25 from the main surface side. That is, since it is not necessary to contact the measurement probe from the formation side of the image sensor 5, the amount of probe dust adhering to the light receiving region of the image sensor can be greatly reduced. As a result, an electrical test that was previously possible only before the penetration process can be performed after the completion of the penetration process, so tests including processing defects that occur in the penetration process can be performed, reducing process defects. It becomes possible to make it.

  Further, since the test electrode 16 or the measurement probe does not prevent the test light from entering, it is possible to increase the number of image sensor objects that can be simultaneously tested and to perform an efficient test. .

  In addition, since the wafer 1 of the present invention has a configuration in which the reinforcing plate 2 to be the lid glass is attached after the end of the penetration process, the subsequent assembly process is performed with the reinforcing plate 2 still attached. That is, the upper area of the image sensor 5 is always covered with the reinforcing plate 2 and the element area including the image sensor 5 is not exposed to the outside. Almost no damage is done. Therefore, since the wafer (chip) after mounting can be easily cleaned, the factory that performs the assembly process (post-process) requires a dust level that is as high as the factory that performs the wafer processing process (pre-process). It is possible to reduce the cost related to the assembly process.

Schematic cross-sectional structure diagram shown in the order of manufacturing steps when manufacturing a semiconductor wafer according to the present invention The flowchart which shows the manufacturing process at the time of manufacturing the semiconductor wafer which concerns on this invention The schematic diagram which shows schematic structure of the semiconductor wafer which concerns on this invention The schematic diagram which shows the chip | tip schematic structure on the semiconductor wafer which concerns on this invention The figure which shows typically the electrical connection relation with the back surface side electrode and main surface side electrode when the electrode for a test is formed on the back surface of the semiconductor wafer which concerns on this invention Another figure which shows typically the electrical connection relationship with the back surface side electrode and main surface side electrode when the electrode for a test is formed on the back surface of the semiconductor wafer which concerns on this invention The schematic diagram which shows schematic structure of the test apparatus based on this invention The figure which shows schematic structure of a wafer stage and light incident means Flow chart showing test process for testing semiconductor wafers The figure which shows schematic structure of the chip structure after a test process and solder mounting process completion Schematic showing a state where an electrical test is performed on a semiconductor chip having a conventional configuration

Explanation of symbols

1: Semiconductor substrate 2: Reinforcing plate 3: Main surface side electrode (first electrode)
4: Adhesive resin 5: Image sensor 6: Through hole 7: Insulating film 8: Back side electrode (second electrode)
12: Wafer marking area 14: Alignment adjustment mark 16: Test electrode 20: Test apparatus according to the present invention 21: Wafer loader 22: Alignment means 23: Probe card 24: Wafer stage 25: Light incident means 26: Control means 31: Vacuum groove 32: Suction port 40: Housing 41: Light emitting element 42: Light emitter mounting substrate 43: Light diffusion plate 44: Protection body 51: Mounting substrate 52: Bump C1: Chip P1: Measuring probe P2: Measuring probe 91 : Semiconductor chip 92: Contact pad 93: Wiring board 94: Bump 95: Test board 96: Test electrode

Claims (6)

A semiconductor wafer on which an image sensor is formed,
Having a first electrode on the main surface side that forms an electrical contact with the element region including the image sensor and the element region, and a second electrode on the back surface side opposite to the main surface side,
On the main surface side, a reinforcing plate that transmits light in a frequency range that can be received by the image sensor is bonded and formed,
A semiconductor wafer, wherein the first electrode and the second electrode are electrically connected via a conductive material formed so as to penetrate the main surface side and the back surface side. A test apparatus for testing a semiconductor wafer in which an element region including an imaging element is formed on a first wafer surface,
A wafer stage for mounting the semiconductor wafer;
A probe card for bringing a measuring probe into contact with a predetermined electrode formed on a second wafer surface opposite to the first wafer surface on the opposite surface of the wafer stage;
A light incident means for making incident light in a frequency range that can be received by the imaging device incident on the first wafer surface;
The wafer stage is
Having a property of transmitting the target light in at least a mounting region where the semiconductor wafer is mounted;
The target light incident from the light incident means is configured to be able to irradiate the imaging element formed on the first wafer surface on the semiconductor wafer placed on the wafer stage. Test equipment characterized by. The light incident means is
A plurality of light emitting elements arranged in parallel to the wafer stage surface at a predetermined distance in a direction opposite to the probe card installation side from the wafer stage;
A diffusion plate interposed between the plurality of light emitting elements and the wafer stage in order to diffuse the emitted light from the plurality of light emitting elements to the first wafer surface of the semiconductor wafer; The test apparatus according to claim 2.   Recognizing the formation position of the alignment adjustment electrode or alignment adjustment insulating film on the second wafer surface that is not electrically connected to the element region, and mounting on the wafer stage based on the recognition result 4. The test apparatus according to claim 2, further comprising alignment means for setting a position. A vacuum groove for fixing the semiconductor wafer placed on the wafer stage by vacuum suction is provided on the wafer stage,
The alignment means;
Based on the recognition result of the formation position of the alignment adjustment electrode or the alignment adjustment insulating film, a non-light receiving region on the first wafer surface of the semiconductor wafer is recognized, and the non-light receiving region is opposed to the vacuum groove. The test apparatus according to claim 4, wherein the mounting position of the semiconductor wafer on the wafer stage is set. A test method for conducting an electrical test of a semiconductor wafer according to claim 1,
When the semiconductor wafer to be tested is set to the test apparatus according to claim 4 or 5,
The test device is
According to the mounting position set by the alignment means, the semiconductor wafer to be tested is mounted on the wafer stage such that the wafer surface on the back side faces the probe card,
The light is incident on the main surface side of the semiconductor wafer from the light incident means, and the probe card is formed on the main surface side by bringing the predetermined second electrode and the measurement probe into contact with each other. A test method characterized by measuring a physical quantity corresponding to the amount of light received by the image sensor and determining the state of the semiconductor wafer based on the measurement result.