KR101957971B1 - Stereoscopic image display - Google Patents

Abstract

A stereoscopic image display apparatus includes a display panel including a plurality of pixels to selectively display a 2D image and a 3D image; And a pattern reliader for dividing the light from the display panel into first and second polarized light beams; Each of the pixels includes a first pixel electrode connected to a data line through a first TFT, a first common electrode supplied with a common voltage, a common voltage supply line for supplying the common voltage, A main display unit including a first storage capacitor connected to the main storage unit; A second pixel electrode connected to the data line through a second TFT, a second common electrode to which the common voltage is supplied, a reset line for supplying a reset pulse, and a second storage capacitor connected between the second pixel electrode, And an auxiliary display unit including the auxiliary display unit; The first TFT and the second TFT are switched by the same scan pulse; The reset pulse is generated at the ON level by the first time faster than the scan pulse in the 2D image implementation and is generated at the ON level later than the scan pulse by the second time in the 3D image implementation.

Description

[0001] STEREOSCOPIC IMAGE DISPLAY [0002]

The present invention relates to a stereoscopic image display apparatus capable of selectively implementing a two-dimensional plane image (hereinafter referred to as a '2D image') and a three-dimensional stereoscopic image (hereinafter, referred to as a '3D image').

A stereoscopic image display device capable of selectively implementing a 2D image and a 3D image has been developed and commercialized due to development of various contents and circuit technology. The 3D image implementation method of the stereoscopic image display device is divided into a stereoscopic technique and an autostereoscopic technique.

The binocular parallax method uses parallax images of right and left eyes with large stereoscopic effect, and both glasses and non-glasses are used, and both methods are practically used. In the non-eyeglass system, an optical plate such as a parallax barrier for separating the optical axis of left and right parallax images is installed in front of or behind the display screen. In the spectacle method, left and right parallax images having different polarization directions are displayed on a display panel, and stereoscopic images are implemented using polarized glasses or liquid crystal shutter glasses.

In the polarizing glasses system, a polarized light separating element such as a patterned retarder is attached to the display panel. The patterned retarder separates the polarization of the left eye image and the right eye image displayed on the display panel. When a viewer views a stereoscopic image in a polarizing glasses type stereoscopic image display apparatus, polarized glasses are worn to observe the polarization of the left eye image through the left eye filter of the polarized glasses, and the polarization of the right eye image is viewed through the right eye filter of the polarized glasses So you can feel the three-dimensional feeling.

In a conventional stereoscopic image display apparatus using polarizing glasses, the display panel can be applied as a liquid crystal display panel. Due to the parallax between the pixel array of the liquid crystal display panel and the patterned retarder, the upper and lower viewing angles are poor due to the thickness of the upper glass substrate and the thickness of the upper polarizing film of the liquid crystal display panel.

1, the liquid crystal display panel includes an upper glass substrate G2 on which a color filter CF and a black matrix BM are formed, a lower glass substrate G1 on which a TFT (Thin Film Transistor) array is formed, G2), and the like. The patterned retarder is bonded to the upper polarizing film of the liquid crystal display panel. The patterned retarder has a first pattern P1 opposed to the odd-numbered horizontal pixel line in the pixel array of the liquid crystal display panel, and a second pattern P2 opposed to the odd-numbered horizontal pixel line in the pixel array of the liquid crystal display panel . The optical axes of the first pattern P1 and the second pattern P2 are orthogonal to each other. The odd-numbered horizontal pixel line in the pixel array of the liquid crystal display panel can display the left-eye image L and the even-numbered horizontal pixel line can display the right-eye image R. [ In this case, the light of the left eye image displayed on the odd-numbered horizontal pixel line of the pixel array is incident on the first pattern P1 as linearly polarized light through the upper polarizing film, and the light of the right- Is incident on the second pattern P2 as linearly polarized light through the upper polarizing film. The first pattern P1 passes the light of the left eye image through the left circularly polarized light by delaying the phase of the linearly polarized light incident through the upper polarizing film by a quarter wavelength at a front viewing angle indicated by a dotted line. The second pattern P2 delays the phase of the linearly polarized light having passed through the upper polarizing film at a front viewing angle indicated by a dotted line by 3/4 wavelength to pass the light of the right eye image through the right circularly polarized light. The left eye filter of the polarizing glasses (PG) passes only the left circularly polarized light and the right eye filter passes only the right circularly polarized light. When the viewer wears the polarizing glasses (PG), only the pixels of the odd-numbered horizontal pixel lines of the pixel array in which the left eye image is displayed are displayed in the left eye of the viewer, and the right- Only pixels are visible. Thus, the viewer can view a 3D image without 3D crosstalk at the front view angle indicated by a dotted line in Fig.

On the other hand, when a viewer views a stereoscopic image displayed on the stereoscopic image display device of the polarizing glasses system at a vertical viewing angle higher or lower than the front of the liquid crystal display panel, the 3D crosstalk (left eye and right eye images) . Light of the left eye image displayed on the odd-numbered horizontal pixel line of the pixel array at the upper and lower viewing angles indicated by the solid line in FIG. 1 is incident on the first pattern P1 as linearly polarized light through the upper polarizing film, . In addition, light of the right eye image displayed on the even-numbered horizontal pixel line of the pixel array may be incident on the second pattern P2 as linearly polarized light through the upper polarizing film, and some of the light may be incident on the first pattern P1. The light of the left eye image emitted through the second pattern P2 or the light of the right eye image emitted through the first pattern P1 becomes undesired leakage light. In this case, the viewer views the pixels of the odd-numbered horizontal pixel lines of the pixel array in which the left eye image is displayed through the polarizing glasses (PG) at the vertical viewing angle in each of the left eye and right eye, Lt; / RTI > pixels of the odd-numbered horizontal pixel lines of the array. Accordingly, when a viewer views a 3D image displayed on a polarizing glasses type image display device at an upper and a lower viewing angle, 3D crosstalk in which the left eye and right eye images are superimposed can be perceived as a single eye (left eye or right eye).

In order to solve such a problem of the 3D crosstalk of the upper and lower viewing angles, Japanese Unexamined Patent Application Publication No. 2002-185983 has proposed a method of forming a black stripe on a pattern drift of a stereoscopic image display device. Alternatively, the width of the black matrix formed on the liquid crystal display panel may be increased. However, if a black stripe is formed on the patterned retarder, not only the luminance of the 2D image and the 3D image is degraded, but also the moire can be caused by the interaction of the black matrix and the black stripe. The method of increasing the width of the black matrix lowers the aperture ratio and lowers the luminance in the 2D image and the 3D image.

In order to solve the problems of the stereoscopic image display device disclosed in Japanese Unexamined Patent Application Publication No. 2002-185983, the applicant of the present application divides each of the pixels of the display panel into two, and one of them is called a Switchable Black Stripe, (Patent Application No. 10-2009-0033534 (2009. 04. 17), United States Patent Application No. 12 / 536,031 (Aug. 05, 2009)). The stereoscopic image display apparatus proposed by the present applicant can divide each of the pixels into two and write a 2D image in each of the divided pixels in the 2D mode to prevent the luminance of the 2D image from being degraded as shown in FIG. The upper and lower viewing angles can be enlarged by writing the 3D image (L or R) in one of the divided pixels and the black image (B) in the other one to shield the leakage light from the 3D image. However, this switchable black stripe technique has a disadvantage in that it is difficult to apply to a fixed high-resolution model because the pixel and signal line configuration for driving each pixel in two-divided are complicated.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a stereoscopic image display device and a stereoscopic image display method capable of improving the brightness of a 2D image and the upper and lower viewing angles of a 3D image while simplifying the configuration of pixels and signal lines, Device.

According to an aspect of the present invention, there is provided a stereoscopic image display apparatus including a display panel including a plurality of pixels to selectively display a 2D image and a 3D image; And a pattern reliader for dividing the light from the display panel into first and second polarized light beams; Each of the pixels includes a first pixel electrode connected to a data line through a first TFT, a first common electrode supplied with a common voltage, a common voltage supply line for supplying the common voltage, A main display unit including a first storage capacitor connected to the main storage unit; A second pixel electrode connected to the data line through a second TFT, a second common electrode to which the common voltage is supplied, a reset line for supplying a reset pulse, and a second storage capacitor connected between the second pixel electrode, And an auxiliary display unit including the auxiliary display unit; The first TFT and the second TFT are switched by the same scan pulse; The reset pulse is generated at the ON level by the first time faster than the scan pulse in the 2D image implementation and is generated at the ON level later than the scan pulse by the second time in the 3D image implementation.

And a controller for controlling the application timing of the first gate start pulse to control the on timing of the reset pulse and controlling the application timing of the second gate start pulse for controlling the on timing of the scan pulse.

Wherein the reset pulse includes first to n < th > reset pulses shifted by a predetermined period in a line sequential manner; Wherein the scan pulse includes first to n < th > scan pulses shifted by a predetermined period in a line sequential manner; In the 2D image realization, the first to n < th > reset pulses are generated at an on level faster than the first to n < th > scan pulses by the first time; In the 3D image realization, the first to the n-th reset pulses are generated at the ON level later than the first to the n-th scan pulses by the second time.

In the 2D image implementation, the ON period of the reset pulse is not overlapped with the ON period of the scan pulse.

In implementing the 3D image, the ON period of the reset pulse is partially overlapped with the ON period of the scan pulse.

The potential of the second pixel electrode is reset to the common voltage within a predetermined time period starting from the falling edge of the reset pulse.

The first and second pixel electrodes and the first and second common electrodes are all formed on the same substrate.

The liquid crystals of each of the pixels are driven in a normally black mode.

The stereoscopic image display device according to the present invention can drive each of the pixels in two parts by using the switchable black stripe technique and can improve the luminance of the 2D image and the vertical angle of view of the 3D image while simplifying the configuration of the pixel and the signal line. According to the present invention, since the pixels and the signal line structure for driving each pixel in two halves are simplified, it is easy to apply them to a fixed-resolution, high-resolution model.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing a vertical viewing angle at which a 3D crosstalk appears in a stereoscopic image display apparatus of a polarizing glasses system. Fig.
Figure 2 shows a conventional switchable black stripe technique for reducing 3D crosstalk.
3 and 4 are views showing a polarizing glasses type stereoscopic image display apparatus according to an embodiment of the present invention.
Fig. 5 shows an equivalent circuit of the pixel shown in Fig. 4; Fig.
FIGS. 6 and 7 are diagrams showing timings at which a reset pulse and a scan pulse are generated in the 2D mode. FIG.
FIGS. 8 and 9 are diagrams showing timing of generation of a reset pulse and a scan pulse in the 3D mode. FIG.
10 is an equivalent circuit diagram of vertically adjacent pixels sequentially receiving a scan pulse and a reset pulse;
11 is a diagram showing waveform changes of a first pixel voltage and a second pixel voltage in a 2D mode.
12 is a diagram showing waveform changes of a first pixel voltage and a second pixel voltage in a 3D mode;
13 is a view showing a voltage-transmittance characteristic curve in a normally black mode;
14 is a view showing an image displayed on a pixel in a 2D mode and a 3D mode;
15A and 15B are diagrams showing simulation results according to 2D driving and 3D driving, respectively.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to FIGS. 3 to 15B.

3 and 4 show a polarizing glasses type stereoscopic image display apparatus according to an embodiment of the present invention.

3 and 4, the stereoscopic image display apparatus includes a display device 10, a pattern drift detector 20, a controller 30, a panel driving circuit 40, and polarizing glasses 50.

The display device 10 may include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an inorganic electroluminescent device, A flat panel display device such as an electroluminescence device (EL) including an organic light emitting diode (OLED), and an electrophoresis (EPD) device. Hereinafter, the display element 10 will be described mainly with reference to a liquid crystal display element.

The display element 10 includes a display panel 11, an upper polarizing film 11a, and a lower polarizing film 11b.

The display panel 11 displays a 2D image in the 2D mode and a 3D image in the 3D mode. The display panel 11 includes two glass substrates and a liquid crystal layer LC formed therebetween. The lower glass substrate of the display panel 11 is provided with a plurality of data lines DL, a plurality of gate lines GL respectively intersecting with the data lines DL, a plurality of reset lines V3DL), a common voltage supply line for supplying the common voltage Vcom, and the like are formed. A TFT (Thin Film Transistor) is provided for each intersection of the data lines DL and the gate lines GL, a pixel electrode for charging a data voltage to the liquid crystal cell, And a storage capacitor connected to the electrode to maintain the voltage of the liquid crystal cell.

On the upper glass substrate of the display panel 11, a color filter array is formed. The color filter array includes a black matrix, a color filter, and the like. An upper polarizing film 11a is attached to the upper glass substrate, a lower polarizing film 11b is attached to the lower glass substrate, and an alignment film is formed on the inner surface contacting the liquid crystal layer to set the pretilt angle of the liquid crystal. A column spacer for maintaining a cell gap of the liquid crystal cell may be formed between the glass substrates.

A common electrode to which the common voltage Vcom is supplied is formed on the lower glass substrate. The common electrode is electrically in contact with the common voltage supply line formed on the lower glass substrate, and receives the common voltage Vcom from the common voltage supply line. A horizontal electric field is formed between the common electrode and the pixel electrode, and the transmittance of the liquid crystal cell is determined by the horizontal electric field. The liquid crystal cell can be driven in a normally black mode in which the transmittance or the gray level is increased as the potential difference between the data voltage applied to the pixel electrode and the common voltage Vcom applied to the common electrode is greater.

The display device 10 of the present invention can be implemented in any form such as a transmissive display device, a transflective display device, and a reflective display device. In the transmissive display element and the semi-transmissive display element, the backlight unit 12 is required. The backlight unit 12 may be implemented as a direct type backlight unit or an edge type backlight unit.

A pixel array including a plurality of unit pixels is formed on the display panel 11 by the intersection structure of the signal lines DL and GL. The unit pixels each include a first pixel PIX for a red (R) implementation, a second pixel PIX for a green (G) implementation, and a third (PIX) implementation of blue (B). Each of the pixels PIX is divided into a main display part and an auxiliary display part. In the 2D mode, the main display unit and the auxiliary display unit display the same 2D image. In the 2D mode, the auxiliary display unit is first reset to the common voltage (Vcom) before charging the 2D image together with the main display unit. In the 3D mode, the main display unit displays the 3D image and the auxiliary display unit displays the black image. In the 3D mode, the auxiliary display unit is reset to the common voltage Vcom after charging the 3D image together with the main display unit. The auxiliary display unit functions as a switchable black stripe to display black images only in the 3D mode.

The patterned retarder 20 is attached to the upper polarizing film 11a of the display panel 11. [ A first pattern 22 is formed on the odd number lines of the pattern reliader 20 and a second pattern 24 is formed on the even lines of the pattern reliader 20. [ The light absorption axis of the first pattern 22 and the light absorption axis of the second pattern 24 are orthogonal to each other. The first pattern 22 faces the odd-numbered horizontal pixel lines of the pixel array and the second pattern 24 faces the odd-numbered horizontal pixel lines of the pixel array. The first pattern 22 delays the phase of the linearly polarized light incident through the upper polarizing film 11a by a quarter wavelength to pass through the first polarized light (for example, left circularly polarized light). The second pattern 24 passes the phase of the linearly polarized light incident through the upper polarizing film 11a by the third polarized light by the third polarized light (for example, right circularly polarized light).

The controller 30 controls the operation of the panel driving circuit 40 in the 2D mode or the 3D mode according to the mode selection signal SEL. The controller 30 receives the mode selection signal SEL through a user interface such as a touch screen, an on-screen display (OSD), a keyboard, a mouse and a remote controller, And 3D mode operation can be switched. The controller 30 receives a 2D / 3D identification code, for example, an EPG (Electronic Program Guide) of a digital broadcasting standard or an ESG (Electronic Service Guide) To distinguish the 2D mode from the 3D mode.

The controller 30 separates the RGB data of the left eye image and the RGB data of the right eye image from the data driver 41 after separating the 3D image data input from the video source in the 3D mode into RGB data of the left eye image and RGB data of the right eye image, . To this end, the controller 30 may include a 3D formatter. The controller 30 supplies the RGB data of the 2D image input from the video source to the data driver 41 under the 2D mode.

The controller 30 controls the operation of the panel driving circuit 40 using timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DE, and a dot clock DCLK And generates control signals for controlling the timing.

The data control signal for controlling the operation timing of the data driver 41 includes a source start pulse (SSP), a rising (Rising) signal indicating a start point of data in one horizontal period in which data for one horizontal pixel line is displayed, A source sampling clock (SSC) for controlling the latch operation of the data on the basis of the rising edge or the falling edge of the data signal, a source output enable signal SOE for controlling the output of the data driver 41, A polarity control signal POL for controlling the polarity of the data voltage to be supplied to the liquid crystal cells of the liquid crystal display 11, and the like.

The gate control signal for controlling the operation timing of the gate driver 42 includes a second gate start pulse (GSP2) indicating a starting horizontal pixel line from which a scan starts in one vertical period in which one screen is displayed, A gate shift clock signal GSC for sequentially shifting the second gate start pulse GSP2 inputted to the shift register in the driver 42 and a gate output signal for controlling the output of the gate driver 42 A gate output enable (GOE) signal, and the like.

The reset control signal for controlling the operation timing of the reset driver 43 includes a first gate start pulse GSP1 indicating a start horizontal pixel line at which reset is started in one vertical period in which one screen is displayed, A gate shift clock signal (GSC) for sequentially shifting the first gate start pulse GSP1 input to the shift register in the driver 43 and a gate output signal for controlling the output of the reset driver 43 A gate output enable (GOE) signal, and the like.

The controller 30 controls the application timing of the first gate start pulse GSP1 and the second gate start pulse GSP2 to control the on timing of the scan pulse and the reset pulse in 2D driving, Of the scan pulse and the reset pulse.

The controller 30 multiplies the timing signals (Vsync, Hsync, DE, DCLK) synchronized with the input frame frequency to generate a frame frequency of Nxf (where N is a positive integer of 2 or more and f is the input frame frequency) The operation of the drive circuit 40 can be controlled. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) system and 50 Hz in the PAL (Phase-Alternating Line) system.

The panel driver circuit 40 includes a data driver 41 for driving the data lines DL of the display panel 11 and a gate driver 42 for driving the gate lines GL of the display panel 11 And a reset driver 43 for driving the reset lines V3DL of the display panel 11.

Each of the data ICs of the data driver 41 includes a shift register, a latch, a digital to analog converter (DAC), an output buffer, and the like. The data driver 41 latches the RGB data of the 2D or 3D image according to the data control signals SSP, SSC and SOE. The data driver 41 converts the RGB data of the 2D or 3D image into the analog positive gamma compensation voltage and the negative gamma compensation voltage in response to the polarity control signal POL to reverse the polarity of the data voltage. The data driver 41 outputs the data voltage to the data lines DL in synchronization with the scan pulse (or gate pulse) output from the gate driver 42. [ The data ICs of the data driver 41 can be bonded to the lower glass substrate of the display panel 11 by a TAB (Tape Automated Bonding) process.

The gate driver 42 generates a scan pulse swinging between a gate high voltage (turn-on level) and a gate low voltage (turn-off level) according to the gate control signals GSP2, GSC and GOE. Then, a scan pulse is supplied to the gate lines GL in a line sequential manner in accordance with the gate control signals GSP2, GSC, and GOE. The gate driver 42 includes a gate shift register array and the like. The gate shift register array of the gate driver 42 may be formed in a non-display area outside the display area in which the pixel array is formed in the display panel 11, using a GIP (Gate Driver In Panel) method. With the GIP scheme, gate shift registers can be formed with a pixel array in a TFT (Thin Film Transistor) process of a pixel array. The gate driver 42 may be implemented with gate ICs bonded to the lower glass substrate of the display panel 11 by a TAB process.

The reset driver 43 generates a reset pulse that swings between the gate high voltage (turn-on level) and the gate low voltage (turn-off level) according to the gate control signals GSP1, GSC and GOE. Then, a reset pulse is supplied to the reset lines V3DL in a line-sequential manner in accordance with the gate control signals GSP1, GSC, and GOE. The reset driver 43 includes a reset shift register array and the like. The reset shift register array of the reset driver 43 may be formed in a non-display area outside the display area where the pixel array is formed in the display panel 11 by a GIP (Gate Driver In Panel) method. With the GIP scheme, the reset shift registers can be formed with a pixel array in a TFT (Thin Film Transistor) process of a pixel array. In the GIP scheme, the reset driver 43 can be integrated with the gate driver 42. The reset driver 43 may be implemented by separate ICs connected to the lower glass substrate of the display panel 11 by a TAB process.

The polarizing glasses 50 include a left eye 50L having a left eye polarization filter and a right eye 50R having a right eye polarization filter. The left eye polarizing filter has the same light absorption axis as the first pattern 22 of the patterned retarder 20 and the right eye polarizing filter has the same light absorption axis as the second pattern 24 of the patterned retarder 20. [ For example, the left eye polarizing filter of the polarizing glasses 50 may be selected as a left circular polarization filter, and the right eye polarizing filter of the polarizing glasses 50 may be selected as a right circular polarization filter. When the viewer wears the polarizing glasses 50, only the left eye image is displayed in the left eye of the viewer, and only the right eye image is displayed in the right eye of the viewer. As a result, the viewer can feel the stereoscopic effect through the binocular parallax.

Fig. 5 shows an equivalent circuit of the pixel PIX shown in Fig.

Referring to FIG. 5, the pixel PIX of the present invention is divided into a main display MP and an auxiliary display SP.

The main display unit MP includes a first pixel electrode Ep1 constituting a first liquid crystal capacitor Clc1 and a first common electrode Ec1 opposed to each other. The first pixel electrode Ep1 is connected to the data line DL through the first TFT ST1. The first TFT ST1 applies a data voltage Vdata on the data line DL to the first pixel electrode Ep1 by being turned on in response to the scan pulse SCAN from the gate line GL. The gate electrode of the first TFT ST1 is connected to the gate line GL, the drain electrode thereof is connected to the data line DL, and the source electrode thereof is connected to the first pixel electrode Ep1. The source electrode of the first TFT (ST1) overlaps the common voltage supply line (VCL) with at least one insulating film interposed therebetween to form a first storage capacitor (Cst1). The first storage capacitor Cst1 is connected to the first pixel electrode Ep1 through the first node N1 and maintains the charge voltage of the first liquid crystal capacitor Clc1 constant for a predetermined period of time. The first common electrode Ec1 is electrically connected to the common voltage supply line VCL charged with the common voltage Vcom and is supplied with the common voltage Vcom from the common voltage supply line VCL.

The auxiliary display unit SP includes a second pixel electrode Ep2 and a second common electrode Ec2 which oppose each other and constitute a second liquid crystal capacitor Clc2. And the second pixel electrode Ep2 is connected to the data line DL through the second TFT ST2. The second TFT ST2 applies a data voltage Vdata on the data line DL to the second pixel electrode Ep2 by being turned on in response to the scan pulse SCAN from the gate line GL. The gate electrode of the second TFT ST2 is connected to the gate line GL, the drain electrode thereof is connected to the data line DL, and the source electrode thereof is connected to the second pixel electrode Ep2. The source electrode of the second TFT ST2 overlaps the reset line V3DL with at least one insulating film interposed therebetween to form a second storage capacitor Cst2. The second storage capacitor Cst2 is connected to the second pixel electrode Ep2 through the second node N2 to couple the reset control line V3DL and the second liquid crystal capacitor Clc2. The second common electrode Ec2 is electrically connected to the common voltage supply line VCL charged with the common voltage Vcom and is supplied with the common voltage Vcom from the common voltage supply line VCL.

The auxiliary display unit SP performs a reset operation in accordance with the reset pulse V3D applied to the reset line V3DL. The reset start timing in the auxiliary display section SP is synchronized with the falling edge of the reset pulse V3D.

6 and 7 show the timing of generation of the reset pulse and the scan pulse in the 2D mode.

Referring to FIG. 6, in the 2D mode, the controller generates the first gate start pulse GSP1 by a first time T1 as compared with the second gate start pulse GSP2. As described above, the first gate start pulse GSP1 is used to control the generation timing of the reset pulse V3D in one vertical period, and the second gate start pulse GSP2 is used to control the generation timing of the scan pulse SCAN ), The reset pulse V3D is generated at the ON level earlier than the scan pulse SCAN by the first time T1. On the other hand, the reset pulse V3D may be non-overlapping with the ON period of the scan pulse SCAN for securing the reset time.

Referring to FIG. 7, the reset pulse V3D includes first to n-th reset pulses V3D (1) to V3D (n) shifted by a predetermined period in a line sequential manner. The scan pulse SCAN includes first to nth scan pulses SCAN (1) to SCAN (n) that are shifted by a predetermined period in a line sequential manner. The first to n-th reset pulses V3D (1) to V3D (n) are turned on for the first time T1 in comparison with the first to nth scan pulses SCAN (1) to SCAN (n) Level.

FIGS. 8 and 9 show timing of generation of the reset pulse and the scan pulse in the 3D mode.

8, in the 2D mode, the controller supplies a first gate start pulse GSP1 for controlling the generation timing of the reset pulse V3D to a second gate start pulse GSP2 for controlling the timing of generation of the scan pulse SCAN GSP2) by a second time (T2). Therefore, the reset pulse V3D is generated at the on level at a later time by the second time T2 than the scan pulse SCAN. On the other hand, the reset pulse V3D may partially overlap with the ON period of the scan pulse SCAN.

Referring to FIG. 9, the reset pulse V3D includes first to n-th reset pulses V3D (1) to V3D (n) that are shifted by a predetermined period in a line sequential manner. The scan pulse SCAN includes first to nth scan pulses SCAN (1) to SCAN (n) that are shifted by a predetermined period in a line sequential manner. The first to n-th reset pulses V3D (1) to V3D (n) are delayed by a second time T2 in comparison with the first to nth scan pulses SCAN (1) to SCAN (n) Level.

Fig. 10 shows a vertically adjacent two-pixel equivalent circuit used in the operation description. 11 shows waveform changes of the first pixel voltage of the main display unit and the second pixel voltage of the auxiliary display unit in the 2D mode. 12 shows waveform changes of the first pixel voltage and the second pixel voltage in the 3D mode. 13 shows the voltage-transmittance characteristic curve in the normally black mode, and FIG. 14 shows the image displayed on the pixels in the 2D mode and the 3D mode.

Each pixel circuit configuration in Fig. 10 is substantially the same as that described in Fig. Referring to FIGS. 10, 11, 13, and 14, the operation of any one of the pixels arranged in the n-th horizontal pixel line in the 2D mode will now be described.

In the 2D mode, the reset pulse V3D (n) is generated at an on level earlier than the scan pulse SCAN (n), so that the reset period P1 precedes the charge period P2.

The reset period P1 is extended by a predetermined time from the falling edge of the reset pulse V3D (n) which changes from on level to off level. During the reset period P1, the scan pulse SCAN (n) has an off level. The second pixel electrode Vp2 is connected to the reset pulse V3D (n) because the second pixel electrode Ep2 of the auxiliary display unit is coupled to the reset line V3DL (n) through the second storage capacitor Cst2. In synchronization with the falling edge of the reset pulse V3D (n). When the second pixel voltage Vp2 is lowered, the potential of the source electrode of the second TFT (ST2) is also lowered. Therefore, the second TFT (ST2) of the auxiliary display section is turned on. The 'slit-on' state means a state in which the channel resistance of the TFT is larger (that is, a state in which the amount of current flowing between the source and the drain of the TFT is small) compared to the 'full on' state. The gate-source voltage Vgs of the second TFT (ST2) in the slit-on state is larger than the threshold voltage (Vth) of the second TFT (ST2) by a predetermined value. When the second TFT ST2 is turned on, the second pixel voltage Vp2 is reset to the common voltage Vcom within a predetermined period (e.g., one horizontal period 1H).

The charge period P2 corresponds to the ON period of the scan pulse SCAN (n). In the charging period P2, the first TFT (ST1) and the second TFT (ST2) are simultaneously turned on, and as a result, the main display portion and the auxiliary display portion charge the same data voltage. The first pixel voltage Vp1 charged in the main display unit and the second pixel voltage Vp2 charged in the auxiliary display unit are substantially the same.

The first pixel voltage Vp1 and the second pixel voltage Vp2 are held constant at a set value at the time when the scan pulse SCAN (n) is polled. The voltage VClc2 applied to the second liquid crystal capacitor Clc2 during the holding period in the 2D mode is equal to the voltage VClc1 applied to the first liquid crystal capacitor Clc1. As a result, in the 2D mode, the main display unit and the auxiliary display unit display the same 2D image as shown in Fig. 14 with the gradation according to the voltage-transmittance characteristic of Fig.

Next, referring to FIGS. 10, 12, 13, and 14, the operation of any one of the pixels arranged in the n-th horizontal pixel line in the 3D mode will be described.

In the 3D mode, the reset pulse V3D (n) is generated at an on level later than the scan pulse SCAN (n), so that the reset period P1 lags behind the charge period P2.

The first TFT ST1 and the second TFT ST2 are simultaneously turned on in the charging period P2 corresponding to the ON period of the scan pulse SCAN (n), and as a result, the main display portion and the auxiliary display portion receive the same data Charge the voltage. The first pixel voltage Vp1 and the second pixel voltage Vp2 are set to the same value when the scan pulse SCAN (n) is polled.

The reset pulse V3D (n) is generated at an on level later than the scan pulse SCAN (n) but partially (for example, in a half horizontal period (0.5H)) with the on period of the scan pulse SCAN ) Overlap. The reset period P1 is extended by a predetermined time from the falling edge of the reset pulse V3D (n). In the reset period P1, the scan pulse SCAN (n) has an off level. The second pixel electrode Vp2 is connected to the reset pulse V3D (n) because the second pixel electrode Ep2 of the auxiliary display unit is coupled to the reset line V3DL (n) through the second storage capacitor Cst2. In synchronization with the falling edge of the reset pulse V3D (n). When the second pixel voltage Vp2 is lowered, the potential of the source electrode of the second TFT (ST2) is also lowered. Therefore, the second TFT (ST2) of the auxiliary display section is turned on. When the second TFT ST2 is turned on, the second pixel voltage Vp2 is reset to the common voltage Vcom within a predetermined period (for example, four horizontal periods 4H). On the other hand, in the reset period P1, the main display unit maintains the voltage level set in the charging period P2.

The voltage VClc2 applied to the second liquid crystal capacitor Clc2 during the holding period after the reset period P1 in the 3D mode becomes substantially "0 " due to the reset. In the 3D mode, the auxiliary display unit displays a black image as shown in Fig. 14 according to the voltage-transmittance characteristic of Fig. In the 3D mode, the main display unit displays the gradation according to the voltage (VClc1) applied to the first liquid crystal capacitor Clc1 according to FIG. 13, thereby displaying the 3D image with FIG.

Thus, the auxiliary display unit displays the same image as the main display unit in the 2D mode to increase the aperture ratio and brightness of the 2D image, and displays the black image in the 3D mode to enlarge the vertical viewing angle of the 3D image.

15A and 15B show simulation results according to 2D driving and 3D driving, respectively.

Referring to FIG. 15A, after resetting the auxiliary display unit to the common voltage Vcom by applying a reset pulse V3D at an ON level higher than the scan pulse SCAN by three horizontal periods or more in the 2D driving, , The auxiliary display section and the main display section are charged with the same pixel voltage.

Referring to FIG. 15B, the same pixel voltage is applied to the auxiliary display unit and the main display unit by applying the reset pulse V3D to the scan pulse SCAN at the ON level later than the scan pulse SCAN, Then, only the pixel voltage Vp2 of the sub display unit is reset to the common voltage.

According to the above-described configuration, the stereoscopic image display apparatus according to the present invention is capable of driving each of the pixels in a two-divided manner through the switchable black stripe technique, while simplifying the configuration of pixels and signal lines and improving the luminance of the 2D image and the upper and lower viewing angles of the 3D image Can be improved. According to the present invention, since the pixels and the signal line structure for driving each pixel in two halves are simplified, it is easy to apply them to a fixed-resolution, high-resolution model.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: display element 11: display panel
20: pattern-retarder 30: controller
40: panel driving circuit 41: data driver
42: gate driver 43: reset driver
50: polarized glasses

Claims (9)

A display panel including a plurality of pixels to selectively display a 2D image and a 3D image; And
And a patterned retarder for dividing the light from the display panel into lights of a first polarization and a second polarization;
Wherein each of the pixels comprises:
A first common electrode supplied with a common voltage, a common voltage supply line for supplying the common voltage, and a second common electrode connected to the first storage electrode connected between the first pixel electrode and the data line, A main display section including a capacitor;
A second pixel electrode connected to the data line through a second TFT, a second common electrode to which the common voltage is supplied, a reset line for supplying a reset pulse, and a second storage capacitor connected between the second pixel electrode, And an auxiliary display unit including the auxiliary display unit;
The first TFT and the second TFT are switched by the same scan pulse;
Wherein the reset pulse is generated at an on level for a first time faster than the scan pulse in the 2D image implementation and is generated at an on level for a second time later than the scan pulse in the 3D image implementation,
And the second pixel electrode is coupled to the reset line through the second storage capacitor. The method according to claim 1,
And a controller for controlling the application timing of the first gate start pulse to control the on timing of the reset pulse and controlling the application timing of the second gate start pulse for controlling the on timing of the scan pulse Dimensional image display device. The method according to claim 1,
Wherein the reset pulse includes first to n < th > reset pulses shifted by a predetermined period in a line sequential manner;
Wherein the scan pulse includes first to n < th > scan pulses shifted by a predetermined period in a line sequential manner;
In the 2D image realization, the first to n < th > reset pulses are generated at an on level faster than the first to n < th > scan pulses by the first time;
Wherein the first to n < th > scan pulses are generated at an ON level later than the first to the n < th > scan pulses by the second time. The method according to claim 1,
Wherein the ON period of the reset pulse is non-overlapping with the ON period of the scan pulse in the 2D image implementation. The method according to claim 1,
Wherein the ON period of the reset pulse is partially overlapped with the ON period of the scan pulse in the 3D image realization. The method according to claim 1,
And the potential of the second pixel electrode is reset to the common voltage within a predetermined time period starting from a falling edge of the reset pulse. The method according to claim 1,
Wherein the first and second pixel electrodes and the first and second common electrodes are formed on the same substrate. 8. The method of claim 7,
Wherein the liquid crystals of each of the pixels are driven in a normally black mode. The method according to claim 1,
The second TFT connected to the second pixel electrode is turned on in synchronization with the falling edge of the reset pulse, and the light-on state is larger than the full-on state according to the scan pulse of the on level, And the three-dimensional image display device.

Images